WO2012083689A1

WO2012083689A1 - Digital-to-analog unit circuit and digital-to-analog converter

Info

Publication number: WO2012083689A1
Application number: PCT/CN2011/077525
Authority: WO
Inventors: 郭书苞; 雷工; 李定
Original assignee: 华为技术有限公司
Priority date: 2011-07-25
Filing date: 2011-07-25
Publication date: 2012-06-28
Also published as: CN102388537A; CN102388537B

Abstract

A digital-to-analog unit circuit and a digital-to-analog converter are provided. A redundant branch similar to the structure of the digital-to-analog branch is added in the digital-to-analog unit circuit. The control signal of the redundant branch is redundant to the control signal of the digital-to-analog branch reciprocally, which makes the same charge is transferred in each default period. The second harmonic led by the DC bias of OUTP and OUTN is changed to the high frequency noise. Therefore the harmonic is disappeared in the input signal bandwidth, and the quality of the output signal is improved.

Description

Digital-to-analog conversion unit circuit and digital-to-analog converter

Embodiments of the present invention relate to the field of electronic technologies, and in particular, to a digital-to-analog conversion unit circuit and a digital-to-analog converter. Background technique

With the rapid development of the communications market, modules between digital and analog interfaces in integrated circuits are becoming more and more important. In video and wireless applications, Digital-to-Analog Converter (DAC) requires high-speed and high-precision. Current steer DACs are widely used in integrated circuits. The current steering structure has the advantages of fast, high-precision, and easy-to-complementary complementary metal oxide semiconductor (CMOS) current integration. When the DAC accuracy is higher than 12 bits, the calibration circuit is usually needed. The calibration circuit based on Dynamic Element Matching (DEM) technology can better solve the harmonic problem caused by the matching between the current units. However, DEM technology cannot overcome the pattern-related errors introduced by the switch, and these will lead to the generation of the third harmonic.

There is an improvement in the prior art, through the feedback loop, the signal change of the output of the current steering, that is, the output positive terminal (0UTP) and the output negative terminal (OUTN) is not coupled to the summing point, thereby reducing the third harmonic. .

However, when there is a DC offset (DCOffset) between the 0UTP and the OUTN voltage, the DC offset is coupled to the summing point, especially in the dynamic weighted average (A) mode of the DEM. Larger second harmonic. Summary of the invention

Embodiments of the present invention provide a digital-to-analog conversion unit circuit and a digital-to-analog converter for solving the existing In the technology, the DC offset of the output positive terminal and the output negative terminal in the DWA mode causes a problem of the second harmonic. In one aspect, an embodiment of the present invention provides a digital to analog conversion unit circuit, including:

Digital to analog conversion branch and redundant branch;

The digital to analog conversion branch includes a current source, a first metal oxide semiconductor field effect transistor MOSFET and a second MOSFET, the current source being respectively connected to the first MOSFET, the source of the second MOSFET through a first summing point The drains of the first MOSFET and the second MOSFET are respectively connected to the output positive terminal and the output negative terminal, and the gates of the first MOSFET and the second MOSFET are respectively connected to the first input terminal and the second input terminal;

The redundant branch includes a second summing point in a high resistance state, a third MOSFET and a fourth MOSFET, and the second summing point is respectively connected to sources of the third MOSFET and the fourth MOSFET, The drains of the third MOSFET and the fourth MOSFET are respectively connected to the output positive terminal and the output negative terminal, and the gates of the third MOSFET and the fourth MOSFET are respectively connected to the third input terminal and the fourth input terminal; The MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET are negative polarity (N-type) MOSFETs of the same parameter, and the third control signal input by the third input terminal and the first control signal input by the first input terminal The fourth control signal input by the fourth input terminal and the second control signal input by the second input terminal are mutually redundant.

In another aspect, an embodiment of the present invention provides a digital to analog converter, including:

At least one digital-to-analog conversion unit circuit, the digital-to-analog conversion unit circuit is a circuit as described above; a switch driving unit, the input end of the switch driving unit inputs a digital signal to be converted, and the output end of the switch driving unit is connected a first input end, a second input end, a third input end, and a fourth input end of the at least one digital to analog conversion unit.

One of the above technical solutions has the following advantages or benefits:

The embodiment of the invention adopts a redundant branch similar to the digital-to-analog conversion branch structure in the digital-to-analog conversion unit circuit, and the control signals of the redundant branch and the control signals of the digital-to-analog conversion branch are mutually redundant. The same charge transfer is performed for each preset period, and the second harmonic caused by the DC offset of 0UTP and OUTN is converted into high frequency noise, so that harmonics are not seen in the output signal bandwidth, and the output is improved. The quality of the signal. DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description of the drawings used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.

FIG. 1 is a schematic diagram of a circuit for adding a feedback loop in a current steering type DAC in the prior art.

FIG. 2 is a schematic circuit diagram of Embodiment 1 of a digital-to-analog conversion unit circuit according to an embodiment of the present invention.

FIG. 3 is a timing diagram of a clock signal and each control signal in the embodiment shown in FIG. FIG. 4 is a schematic circuit diagram of Embodiment 2 of a digital-to-analog conversion unit circuit according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a schematic diagram of an embodiment of a digital to analog converter according to an embodiment of the present invention. detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Some embodiments, rather than all of the embodiments, are invented. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

In order to explain the technical solutions of the embodiments of the present invention in detail, the techniques related to the embodiments of the present invention are briefly introduced herein. The current steering type DAC includes a pair of metal-oxide-semiconductor field-effect transistor (MOSFET) differential pair tubes, and the differential pair tube is controlled by converting the input digital signal into a switch control signal. , the current of the summing point can be directed to OUTP or OUTN, and OUTP and OUTN are connected to the resistor. The array converts the output current into a voltage to form an analog signal for the output. The current rudder type DAC has a disadvantage that the drain voltage of the current source unit, that is, the summing point voltage, changes with the switching of the switch, and the change value is related to the OUTP and OUTN voltage difference of the current rudder output. The change of the sum point voltage causes the node capacitance of the summing point to charge and discharge. When the switch is switched, the charge on the node capacitor is transferred from one end of the current steering unit to the other end of the output (charge transfer). When it is related to the pattern, harmonics are generated and the output signal is degraded.

Dynamic performance and high quality signal output can be achieved by reducing the voltage variation at the summing junction. FIG. 1 is a schematic diagram of a circuit for adding a feedback loop in a current steering type DAC in the prior art. As shown in Figure 1, the circuit consists of two sets of feedback control circuits, such as the 230Ρ and 230Ν modules in Figure 1, to reduce the voltage change of the summing node (ie, S fSN ) due to the voltage change at the output, Figure 1 The 210-Γ210-Ν in the DAC unit. The 230P module includes an operational amplifier 240P, M0S tubes M5P and M6P, current sources 242P and 244P; M5P is a diode connection method that provides a stable reference voltage for the positive terminal of 240P; the source of the M6P tube is connected to 240P Negative terminal, since the drain of M6P is connected to the positive terminal OUTP of the output, the negative terminal voltage of 240P has a certain linear relationship with the 0UTP voltage, thus forming a negative feedback system; the 240P output voltage controls the substrate of M6P, thereby changing The threshold voltage of M6P, so that the source voltage of M6P becomes more stable. In other words, the source voltage of M6P is substantially unchanged by changing the threshold voltage of M6P; the output of 240P is simultaneously coupled to the switching transistors Μ3ΓΜ3Ν of each differential unit, so the source voltage of Μ3ΓΜ3Ν remains substantially unchanged through the feedback control logic. Similarly, the 230N module includes an operational amplifier 240N, MOSFETs M5N and M6N, current sources 242N and 244N, and the source voltage of the M41-M4N is held constant by feedback control logic. In addition, D1_DN, D8 TD8N is a control signal for controlling the gate of the M0S tube in each DAC unit by converting the output digital signal through the switch driving unit, wherein the two control signals of each DAC unit are "non-" relationship , such as D1 and D81, DN and D8N.

The above scheme can make the signal changes of 0UP and OUTN not coupled to the summing point through the feedback loop, thereby reducing the third harmonic; however, when the 0UTP and the OUTN voltage have a DC offset, the deviation is coupled to the summing point. In the mode of A, the deviation will cause a larger second harmonic; The operational amplifier itself also introduces deviations and deteriorates the output signal; and the above scheme is not suitable for the R&S switch, because the substrates of the conventional process are all Psub, which cannot be controlled separately; in addition, the added operational amplifier pair Larger bandwidth requirements will increase the power consumption of the circuit.

In the A mode, in the negative half cycle of the input signal, each DAC unit used is not repeated. For example, if there are eight DAC units, the first input code is 2, and the first and second of the dac cell array are turned on. Unit; the next input code is 3, open the 3rd, 4th, and 5th units, the first and second units are turned off; during the positive half cycle of the input signal, the DAC unit will be repeated according to the input code, such as the input code. When it is 6 and 7, there are 5 DAC units that are repeated, that is, remain open.

In the NRZ type of cur rent s teer ing DAC structure, a major type of pattern-related error is the charge transfer due to the parasitic capacitance charge and discharge at the drain of the current source. Referring to Figure 1, the current source is connected to the differential pair of nodes S 1 with parasitic capacitance. If the node voltage changes, it will charge and discharge to 0UTP or OUTN. For example, if the DC offset of the 0UTP and OUTN voltages makes 0UTP>0UTN, then 0UTP is charged to S1 when D1 transitions from low to high, and S1 is discharged to 0UTN when D81 transitions from low to high. Suppose Q _e — _sl is the amount of charge transferred from node S 1 to 0UTP or OUTN, C _S1 is the capacitance of the parasitic capacitance of node S 1 , and AV _S1 is the voltage change value of node S 1 , then:

Q _e — _sl = C _S1 * AV _S1 ( 1 )

Since the above charge transfer is periodic and related to the frequency of the input signal, these pattern-related errors produce harmonics that degrade the quality of the output signal.

The embodiment of the present invention has the same circuit as the existing DAC unit, so that each preset cycle has the same charge transfer, so that the charge transfer error is independent of the frequency of the input signal, that is, through each The preset charge is injected with the same charge energy, and the original harmonic can be converted into high-frequency noise. This part of the noise can be filtered by the post-stage filter to obtain a high-performance output signal.

FIG. 2 is a schematic circuit diagram of Embodiment 1 of a digital-to-analog conversion unit circuit according to an embodiment of the present invention. As shown in FIG. 2, this embodiment includes:

Digital to analog conversion branch 21 and redundant branch 22; The digital-to-analog conversion branch 21 includes a current source 211, a first MOSFET 212, and a second MOSFET 213. The current source 211 is connected to the source of the first MOSFET 212, the second MOSFET 213, the first MOSFET 212, and the second MOSFET 213 through the first summing point 214, respectively. The drains are connected to the first input terminal inpl and the second input terminal inp2, respectively, connecting the gates of the first MOSFET 212 and the second MOSFET 213;

The redundancy branch 22 includes a second summing point 221 in a high resistance state, a third MOSFET ²²² and a fourth MOSFET 223. The second summing point is respectively connected to the third MOSFET ²²² , the source of the fourth MOSFE, and the third MOSFET ²²² . The drains of the fourth MOSFET ²² 3 are respectively connected to the OUTP, 0UTN, and the gates of the third MOSFET ²²² and the fourth MOSFET ²² 3 are respectively connected to the third input terminal inp3 and the fourth input terminal inp ⁴ ;

The first MOSFET 212, the second MOSFET 213, the third MOSFET 222, and the fourth MOSFET 223 are N-type MOSFETs having the same parameter, and the third control signal p_duml input by the third input terminal inp3 and the first control signal pi input by the first input terminal inpl are Redundantly, the fourth control signal n_duml input by the fourth input terminal inp4 and the second control signal n1 input by the second input terminal inp2 are mutually redundant.

The current source 211 in this embodiment can be implemented by any current source in the prior art, such as the current sources of AVDD, Mi l and M21 shown in FIG. 1 , which is not limited in this embodiment. In addition, the first control signal pi and the second control signal n1 may be complementary as in the prior art, that is, a relationship of "Non" to each other, that is, when pl is at a high level, nl is at a level of C, and vice versa. The same is true for the relationship between the third control signal p-duml and the fourth control signal n_duml. The second summing point 221 in the high resistance state can be implemented by a method in the prior art, such as connecting the second summing point 221 to the drain of the fifth MOSFET, and the source and the gate of the fifth MOSFET are grounded. The fifth MOSFET is a positive (P-type) MOSFET, which is not limited in this embodiment.

The third control signal P-duml input by the third input terminal inp 3 and the first control signal pl input by the first input terminal inpl are mutually redundant, meaning that the third control signal p-ckiml and each preset period The sum of the number of times of the same level jump of the first control signal pl is equal to 1, that is, there is a same level jump of pl or p-ckiml in each preset period, that is, each preset period And a sum of the third control signal and the first control signal from a low to a high level transition is equal to 1, or the third control signal and the first control signal are jumped from a high to a low level The sum of the variables is equal to 1; the fourth input is inp4 input The redundancy between the fourth control signal n_duml and the second control signal n1 input by the second input terminal inp2 means that, in each preset period, the fourth control signal n_duml and the second control signal n1 are in the same level jump. The sum of the number of times is equal to 1, that is, there is a 111 or 11_ (1 let 1 of the same level jump in each preset period, that is, the fourth control signal and the said The sum of the number of level transitions of the second control signal from low to high is equal to 1 or the sum of the number of level transitions of the fourth control signal and the second control signal from high to low is equal to one.

The first MOSFET 212, the second MOSFET 213, the third MOSFET 222, and the fourth MOSFET 223 have the same parameters such that the capacitance of the parasitic capacitance of the first summing point 214 in the digital-to-analog conversion branch 21 and the second summing point in the redundant branch 22 The capacitance of the parasitic capacitance of 221 is equal. Assuming that the capacitance values of the parasitic capacitances of the first summing point 214 and the second summing point 221 are both C, the absolute value of the voltage change of each preset period pi or p-duml is AV, correspondingly, each preset The absolute value of the voltage change of the period 111 or 11_(1111111 is also AV, and the amount of charge transferred from the 0UTP through the first summing point 114 or the second summing point 221 to the OUTN for each preset period is C*?V Or, the amount of charge transferred from 0UTN through the first summing point 214 or the second summing point 221 to the 0UTP for each preset period is C*ΔV.

The preset period here can be preferably set to 2 times the clock period. In the application, the control signal jump can be realized without strictly following the preset period. The specific timing of the clock signal and each control signal can be as shown in FIG. 3, where CLK is a clock signal, and pi and nl are control digital-to-analog conversion branches 21 The switching signal of the M0SFET, P-dumWmi_duml is the switching signal of the MOSFET controlling the redundant branch 22, and a charge transfer occurs whenever the switching signal is switched from low to high or high to low. After the redundant branch 22 is added, the p_duml and the pi signal form a mutually redundant relationship: that is, as long as the digital-to-analog conversion branch 21 has no charge transferred to the OUTP or the OUTN, the redundant branch 22 transfers the charge to the 0UTP or the OUTN. . The charge transfer energy generated by the timing shown in Figure 3 is mainly concentrated at approximately Fs/2, where Fs is the clock frequency, which is the sampling frequency; this part of the energy can be filtered by the post-stage low-pass filter.

The embodiment of the invention adopts a redundant branch similar to the digital-to-analog conversion branch structure in the digital-to-analog conversion unit circuit, and the control signals of the redundant branch and the control signals of the digital-to-analog conversion branch are mutually redundant. So that each preset cycle has the same charge transfer, which will result in the DC offset of 0UTP and OUTN. The subharmonic is converted to high frequency noise, so that harmonics are not seen in the output signal bandwidth, improving the quality of the output signal.

FIG. 4 is a schematic circuit diagram of Embodiment 2 of a digital-to-analog conversion unit circuit according to an embodiment of the present invention. As shown in FIG. 4, the embodiment includes:

Digital to analog conversion branch 41 and redundant branch 42;

The digital-to-analog conversion branch 41 includes a current source 411, a first MOSFET 412, and a second MOSFET 4113. The current source 41 1 is connected to the source of the first MOSFET 412 and the second MOSFET 41 through the first summing point 414, respectively, the first MOSFET 412, The drains of the second MOSFETs 41 are connected to the first input terminal inpl and the second input terminal inp2, respectively. The gates of the first MOSFETs 412 and the second MOSFETs are connected to the first input terminal inpl and the second input terminal inp2;

The digital-to-analog conversion branch 41 further includes: a current sink 431, a sixth MOSFET 432, and a seventh MOSFET 433. The current sink 431 is connected to the source of the sixth MOSFET 432, the seventh MOSFET 433, the sixth MOSFET 432, and the seventh MOSFET 433 through the third summing point 434, respectively. The drains are respectively connected to the 0TPP, 0UTN, and the sixth MOSFET 432, and the gates of the seventh MOSFET 433 are respectively connected to the second input terminal inp2 and the first input terminal inpl;

The redundancy branch 42 includes a second summing point 421 in a high resistance state, a third MOSFET ⁴²² and a fourth MOSFET ⁴²³ , and the second summing point 1 is connected to the sources of the third MOSFET ⁴²² and the fourth MOSFET ⁴² 3, respectively. The drains of the MOSFETs ⁴²² and the fourth MOSFETs ⁴² are respectively connected to the OUTP, 0UTN, and the gates of the third MOSFET ⁴²² and the fourth MOSFET ⁴² are respectively connected to the third input terminal inp3 and the fourth input terminal inp ⁴ ;

The redundancy branch 42 further includes: an eighth MOSFET 441, a ninth MOSFET 442, and a tenth MOSFET 443. The eighth MOSFET 441 is connected to the ninth MOSFET442, the source of the tenth MOSFET 443, the ninth MOSFET442, and the tenth MOSFET 443 through the fourth summing point 444, respectively. The drains are respectively connected to the first input terminal inp4 and the third input terminal inp3, respectively, connecting the 0UTP, 0UTN, and the ninth MOSFET 442, and the gate of the tenth MOSFET 443;

The first MOSFET 412, the second MOSFET 41, the third MOSFET 422, and the fourth MOSFET 423 are N-type MOSFETs of the same parameter, and the third control signal p_duml input by the third input terminal inp3 is mutually coupled with the first control signal pi input by the first input terminal inpl. For redundancy, the fourth control signal input to the fourth input terminal inp4 The number n_duml and the second control signal n1 input by the second input terminal inp2 are mutually redundant;

The sixth MOSFET 432, the seventh MOSFET 433, the ninth MOSFET 442, and the tenth MOSFET 443 are N-type MOSFETs having the same parameters, and the eighth MOSFET is an N-type MOSFET.

The current sink 431 can be implemented by any current sink in the prior art, for example, by an N-type MOSFET. Specifically, a third summing point 434 can be connected to the drain of the N-type MOSFET, and the source of the N-type MOSFET. Grounding, the gate is connected to a bias voltage, which is not limited in this embodiment.

In this embodiment, on the basis of the first embodiment shown in FIG. 2, the digital-to-analog conversion branch and the redundant branch symmetrically add circuits similar to those shown in FIG. 2, forming a fully differential digital-to-analog conversion branch. Roads and redundant branches can increase the amplitude of the output signal. In addition, the case of charge transfer in this embodiment is similar to that of the first embodiment shown in FIG. 2, except that the amount of charge transfer of the added partial circuit is superimposed with the charge transfer amount of the first embodiment, and details are not described herein again.

FIG. 5 is a schematic diagram of a schematic diagram of an embodiment of a digital to analog converter according to an embodiment of the present invention. As shown in FIG. 5, the digital-to-analog converter includes:

At least one digital-to-analog conversion unit circuit 50f 50N, the digital-to-analog conversion unit circuit 50Γ50Ν is a circuit of the digital-to-analog conversion unit circuit embodiment 1 or the second embodiment provided by the embodiment of the invention;

The input end of the switch drive unit 51 inputs the digital signal to be converted, and the output end of the switch drive unit 51 is connected to the first input end of the at least one digital-to-analog conversion unit 50f 50N, the second input end inp ² , and the third Input end inp3, fourth input end inp ⁴ .

Specifically, the switch driving unit 51 outputs a switching signal for controlling the MOSFET in each of the digital-to-analog conversion units 50f to 50N according to the digital signal to be converted, for example, outputting to each of the digital-to-analog conversion units as shown in FIG. Pi, nl, p-dum n-duml.

In an optional embodiment of the present invention, the digital-to-analog converter further includes a resistor array 52. The input end of the resistor array 52 is connected to the OUTP and the OUTN of the at least one digital-to-analog conversion unit 50f 50N, and the output of the resistor array 52 is output. The converted analog signal. The resistor array here can be implemented by a method in the prior art, as long as the current output from the digital-to-analog conversion unit circuit 50Γ50Ν can be converted into a corresponding electric current. It can be pressed, and this embodiment does not limit this.

In still another alternative embodiment of the invention, the digital to analog converter further includes a filter 53 coupled to the output of the resistor array 52. Specifically, the filter 53 is used to filter out high frequency noise generated by charge transfer in each of the digital to analog conversion units 50 Γ 50 。.

In the embodiment of the present invention, a redundant branch similar to the digital-to-analog conversion branch structure is added in the digital-to-analog conversion unit circuit, and the control signals of the redundant branch and the control signals of the digital-to-analog conversion branch are redundant with each other, so that each Each preset cycle has the same charge transfer, and the second harmonic caused by the DC offset of 0UTP and OUTN is converted into high frequency noise, so that harmonics are not seen in the output signal bandwidth, and the quality of the output signal is improved. Further, the high frequency noise can also be filtered by a filter to finally obtain a high performance output signal.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

It should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: The technical solutions described in the foregoing embodiments are modified, or some of the technical features are equivalently replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

Claim

A digital-to-analog conversion unit circuit, comprising: a digital-to-analog conversion branch and a redundant branch;

The digital-to-analog conversion branch includes a current source, a first metal-oxide-semiconductor field-effect transistor MOSFET, and a second MOSFET, wherein the current source is respectively connected to the source of the first MOSFET and the second MOSFET through a first summing point The drains of the first MOSFET and the second MOSFET are respectively connected to the output positive terminal and the output negative terminal, and the gates of the first MOSFET and the second MOSFET are respectively connected to the first input terminal and the second input terminal;

The redundant branch includes a second summing point in a high resistance state, a third MOSFET and a fourth MOSFET, and the second summing point is respectively connected to sources of the third MOSFET and the fourth MOSFET, The drains of the third MOSFET and the fourth MOSFET are respectively connected to the output positive terminal and the output negative terminal, and the gates of the third MOSFET and the fourth MOSFET are respectively connected to the third input terminal and the fourth input terminal;

The first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET are negative polarity (N-type) MOSFETs having the same parameter, and the third control signal input by the third input terminal is input to the first input terminal The first control signals are redundant with each other, and the fourth control signal input by the fourth input terminal and the second control signal input by the second input terminal are mutually redundant.

2. The circuit according to claim 1, wherein the sum of the number of times the third control signal and the first control signal transition from low to high is equal to 1 in each preset period. The sum of the number of levels of the fourth control signal and the second control signal from low to high is equal to one.

3. The circuit according to claim 1, wherein the sum of the number of times the third control signal and the first control signal transition from high to low is equal to 1 in each preset period. A sum of the number of levels of the fourth control signal and the second control signal from high to low is equal to one.

The circuit according to any one of claims 1 to 3, wherein the second summing point is connected to the drain of the fifth MOSFET, and the source and the gate of the fifth MOSFET are grounded, the The five MOSFETs are positive (P-type) M0SFETs.

The circuit according to any one of claims 1 to 3, wherein the digital to analog conversion branch The method further includes: a current sink, a sixth MOSFET, and a seventh MOSFET, wherein the current sink is respectively connected to the sources of the sixth MOSFET and the seventh MOSFET through a third summing point, and the drains of the sixth MOSFET and the seventh MOSFET are respectively respectively Connecting the output positive terminal and the output negative terminal, the gates of the sixth MOSFET and the seventh MOSFET are respectively connected to the second input end and the first input end;

The redundancy branch further includes: an eighth MOSFET, a ninth MOSFET, and a tenth MOSFET, wherein the drain of the eighth MOSFET is respectively connected to the sources of the ninth MOSFET and the tenth MOSFET through a fourth summing point, The drains of the ninth MOSFET and the tenth MOSFET are respectively connected to the output positive terminal and the output negative terminal, and the gates of the ninth MOSFET and the tenth MOSFET are respectively connected to the fourth input terminal and the third input terminal. The source and the gate of the eighth MOSFET are grounded;

The sixth MOSFET, the seventh MOSFET, the ninth MOSFET, and the tenth MOSFET are N-type MOSFETs of the same parameter, and the eighth MOSFET is an N-type MOSFET.

A digital-to-analog converter, comprising: at least one digital-to-analog conversion unit circuit, wherein the digital-to-analog conversion unit circuit is the circuit according to any one of claims 1 to 5;

a switch driving unit, the input end of the switch driving unit inputs a digital signal to be converted, and the output end of the switch driving unit is connected to the first input end, the second input end, and the third input of the at least one digital-to-analog conversion unit End, fourth input.

The digital-to-analog converter according to claim 6, further comprising a resistor array, wherein an input end of the resistor array is connected to an output positive terminal and an output negative terminal of the at least one digital-to-analog conversion unit, The output of the resistor array outputs the converted analog signal.

8. The digital to analog converter of claim 7 further comprising a filter coupled to the output of said resistor array.