WO2012091582A1

WO2012091582A1 - System for direct discrete hilbert transform

Info

Publication number: WO2012091582A1
Application number: PCT/PL2011/000144
Authority: WO
Inventors: Włodzimierz Pogribny; Mariusz SULIMA
Original assignee: Uniwersytet Techniczno-Przyrodniczy Im. Jana I Jędrzeja Śniadeckich W Bydgoszczy
Priority date: 2010-12-31
Filing date: 2011-12-28
Publication date: 2012-07-05
Also published as: PL393534A1

Abstract

The subject of the invention is a multi-channel system for direct Discrete Hilbert Transform (DHT) in PCM format (pulse-code modulation) based on a parallel structure. The system enables determination of all 2N + 1 output samples of DHT within time that does not exceed one sampling period T _s of analogue/digital converter /4/ immediately after the last sample of input signal is received. It also enables the application of weighted impulse response (formule I) to ensure higher resolution of DHT. The system according to the invention wherein at input side, it has one analogue/digital converter /4/, with output parallelly connected to inputs of 2N+1 multiplication units /3_-N/-/3_N/ The second input of each multiplication unit is connected to specific output of the cyclic register /2/. The cyclic register has 2N + 1 outputs from which weight factors are collected. In each (formule II) channel, output of the multiplication unit /3_j/ is connected with an individual input of each accumulator channel /5_j/, where products of input signal samples and relevant weight factors are added. Finally, after processing 2N + 1 samples of input signal (formule III), complete DHT result (formule IV) appears at outputs of channel accumulators /5_j/. A common element for all channels is controller (clock) /1/, whose signals come at Τ _s ^-1frequency.

Description

System for direct Discrete Hilbert Transform

The subject of the invention is a multi-channel system for direct Discrete Hilbert Transform (DHT) in PCM format (pulse-code modulation) based on a parallel structure. The system enables determination of all 2N + 1 output samples of DHT within time period that does not exceed one sampling interval T_x of analogue/digital converter /4/ immediately after the last sample of input signal is received. It also enables the application of weighted impulse response } "__2N ^t0 ensure high resolution of DHT.

A. D. Poularikas„The transforms and applications handbook ", CRC Press, IEEE Press, 2000 and A. V. Oppenheim, R. W. Schafer, J. R. Buck, "Discrete-time signal processing ", Prentice hall, 1998 describe implementation of DHT based on direct method and FFT method. Solutions based on direct algorithm without weight windows and parallel calculations require (2N + 1)² operations and do not ensure high resolution of DHT. Solutions based on FFT require at least (2N + l) log₂(2N + 1) complex multiplication operations; however, processing can only be started after all samples of input signal loaded to the processor memory.

Patents US380013 1 A, GB2150719A and JP1 15761 1 A describe serial DHT systems where, apart from input signal, quadrature signal is also fed to input. Such solutions require serial operations and additional multiplication of input signal by quadrature components, which slow them down and limit their versatility.

Patent TP 1 136407 describes a system for direct DHT with a parallel structure of the DHT processor based on non-cyclic register and two wide-band filters that offer enhancement of DHT resolution. Each channel of such a system contains a multiplication unit. An accumulator constitutes a common block of all channels. With such a parallel-serial solution, the first DHT output sample can be obtained after N time steps, while each subsequent DHT output sample is obtained in a serial manner in each subsequent time step. This feature limits the use of this solution in real-time systems. The key feature of the invention based on the system described herein is that in order to increase their speed while maintaining high resolution of direct DHT, each sample x_l of input signal _w is fed simultaneously to 27V + 1 parallel channels, where it is multiplied by corresponding (channel-related) weight factor taken from a cyclic register 121. The product obtained in each parallel channel is sent to an accumulator separate for each channel. As a consequence, when subsequent input signal samples arrive and weight factor is moved by one position in the cyclic register, each accumulator collects relevant products of samples with relevant weight factors. The accumulation ends when 2N + 1 products arrive in each channel, which corresponds to the end of processing of the last 2N + 1 sample. Finally, all DHT output samples appear simultaneously at outputs of accumulators (channels) immediately alter the end of accumulation of products of the last x_N sample with relevant weight factor in each channel. The characteristic feature of the system according to the invention is the fact that each parallel channels forms a separate DHT output sample.

The advantage of the system according to the invention is the possibility to calculate all 2N+1 DHT output samples with a delay no longer than one sampling period T_s.

Direct DHT enables calculation of all 2/V + l DHT output samples based on convolution of input signal samples {x, }^__N with impulse response {h_t }^~"__{2 N} in the fol lowing manner:

} .

1

m≠ n

and factors of impulse response h_n__m = n - m

0, m = n

More precise specification of the convolution for various DHT output samples x_n enables formulation of a parallel operation mode of direct DHT, which can be described with products of signal samples and weight factors matrices. For example, the results of operation of the proposed system for extreme and middle DHT output samples, i.e. __w , _n and _w , are given below.

(2.1 )

] ;

o - (2.3)

where H

(2.4)

where

As determined by the principles of the system operation and the above formulas, in each channel input samples are multiplied by a set of weight factors relevant for a given channel . For calculation of each of the above 2N + 1 DHT output samples (2.1 ) - (2.4), a separate ordered subset 2N + 1 of weight factors

among 4N + 1 all of those factors is used.

The system according to the invention is presented in the below block diagram of sample embodiment without limitation to its application. A multi-channel system for direct DHT according to the invention, wherein at input side, it has one analogue/digital converter /4/, with output parallelly connected to inputs of 27V + 1 multiplication units 3_N - 3N - The second input of each multiplication unit is connected to specific output of the cyclic register 121. The cyclic register has 2N + 1 outputs from which weight factors are collected. In each j = - N, N channel, output of the multiplication unit /3 is connected with an individual input of each accumulator channel /5 , where products of input signal samples and relevant weight factors are added. Finally, after processing 2N + 1 samples of input signal (x, , complete DHT result _N appears at outputs of channel accumulators /5 . A common element for all channels is controller whose signals controlling the cyclic register 121 come at T^~l frequency. The controller l\l uses separate signal to set the cyclic register 121 to the initial position and restart values of all accumulators after the processing cycle for each subsequent signal realization. The controller also synchronizes operation of multiplication units and accumulators in all channels.

The operation of the system according to the invention is characterized in that input signal in time domain x{i) is subject to sampling in analogue/digital converter 74/ with sampling period T_x and as a consequence, input time series

is created. Each digitized ssaammppllee xx,, ooff tthhee ssiiggnnaall iiss ppaarraalllleellllyy mmuullttiipplliieedd iinn eeaacchh //^'' == --NN,, NN cchhaannnneell bbyy rreelleevvaanntt wweeiigghhtt ffaaccttoorr iinn ddiiggiittaall ffoorrmmaatt tthhaatt iiss ssuupppplliieedd ffrroomm aann oouuttppuutt ooff tthhee ccyycclliicc rreeggiisstteerr sseeppaarraattee ttoo eeaacchh cchhaannnneell 112211;; eevveerryy ttiimmee aafftteerr aa ppaarraalllleell ccoolllleeccttiioonn ooff 22NN ++ ]] wweeiigghhtt ffaaccttoorrss ffrroomm ssppeecciiffiicc oouuttppuuttss ooff tthhee rreeggiisstteerr 112211 ffaaccttoorrss iinn tthhee ccyycclliicc rreeggiisstteerr 112211 aarree mmoovveedd oonn oonnee ppoossiittiioonn.. PPrroodduuccttss oobbttaaiinneedd iinn eeaacchh mmuullttiipplliiccaattiioonn uunniitt //33jj// aarree aaccccuummuullaatteedd sseeppaarraatteellyy iinn rreelleevvaanntt aaccccuummuullaattoorrss

1155))11 iinn eeaacchh ooff jj == --NN,, NN cchhaannnneellss.. TThhiiss pprroocceedduurree tthhaatt ssttaarrtt wwhheenn tthhee ffiirrsstt ssaammppllee ooff iinnppuutt ssiiggnnaall iiss rreecceeiivveedd aanndd eennddss wwiitthh aann aaccccuummuullaattiioonn ooff rreelleevvaanntt pprroodduucctt iinn eeaacchh jj == -- NN,, NN cchhaannnneell iiss rreeppeeaatteedd ffoorr eeaacchh ssuubbsseeqquueenntt ssaammppllee ooff tthhee iinnppuutt sseerriieess uunnttiill tthhee ccoommpplleettiioonn ooff tthhee aaccccuummuullaattiioonn ooff aallll pprroodduuccttss ccoorrrreessppoonnddiinngg ttoo aallll ssaammpplleess ooff iinnppuutt sseerriieess {{xx,, iinn eeaacchh cchhaannnneell.. FFrroomm tthhee bbeeggiinnnniinngg ooff aa ssiiggnnaall ttoo iittss llaasstt ssaammppllee 22ΝΝ aaddddiittiioonnss aarree mmaaddee iinn eeaacchh aaccccuummuullaattoorr aanndd wwhheenn tthheeyy aarree ccoommpplleetteedd ttoottaall DDHHTT

of accumulators /5V - 5M . After the last sample of signal is processed and DHT result is collected from outputs of accumulators /5_N/ - /5 , each accumulator is reset and the cyclic register 121 is moved to the initial position as a result of control signals from the controller /! /.

Claims

Patent claim

The system for direct Discrete Hilbert Transform with multiplication units in all channels, characterized in that it consists of a controller, cyclic register with weight factors recorded from h.₂N to h_2N and a separate accumulator in each channel; all 2N+1 DHT output samples are calculated simultaneously in 2N+1 channels, where input signal samples are fed to the multiplication units from analogue/digital converter and weight factors are fed from an output, specific for each channel, of the cyclic register that, during one time step, moves weight factors by one factor synchronically with the arrival of each sample of the input series, and then in each channel a multiplication operation is performed and its result is transferred from the output of the multiplication unit to a specific accumulator and after completion of 2N+1 simultaneous multiplication operations in 2N+1 channels, the products are accumulated in 2N+1 channel accumulators, while after the arrival of next sample x, of the input series, weight factors are moved in the cyclic register and new products are calculated and accumulated and after the arrival of the last 2N+1 sample and completion associated multiplication operations and accumulation, at outputs of 2N+1 accumulators, all DHT output samples {x_y }^W_ _w are obtained with indexes that match indexes of accumulators (channels), which after the controller signal are read and then the content of all accumulators is reset and the cyclic register is set to the initial position and prepares for processing of new signal realization.