WO2012106311A2 - Esd clamp for multi-bonded pins - Google Patents
Esd clamp for multi-bonded pins Download PDFInfo
- Publication number
- WO2012106311A2 WO2012106311A2 PCT/US2012/023281 US2012023281W WO2012106311A2 WO 2012106311 A2 WO2012106311 A2 WO 2012106311A2 US 2012023281 W US2012023281 W US 2012023281W WO 2012106311 A2 WO2012106311 A2 WO 2012106311A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- coupled
- segments
- clamp
- bond pad
- bonded
- Prior art date
Links
- 239000004020 conductor Substances 0.000 abstract 3
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
Abstract
A circuit comprises a plurality of segments and a clamp circuit. Each of the plurality of segments comprises a bond pad coupled to a multi-bonded pin via a respective bond wire and a conductor coupling the bond pad to a respective internal connection. The bond pad from each of the plurality of segments is coupled to the same multi-bonded pin. The clamp circuit comprises a plurality of input pins and a plurality of clamp transistors. Each input pin is coupled to the bond pad of a respective one of the plurality of segments via the respective conductor. Each clamp transistor is coupled to a respective one of the input pins, wherein each of the plurality of clamp transistors is configured to prevent a voltage on the respective conductor from exceeding a respective voltage limit.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161439420P | 2011-02-04 | 2011-02-04 | |
US61/439,420 | 2011-02-04 | ||
US13/223,482 US8427799B2 (en) | 2011-02-04 | 2011-09-01 | ESD clamp for multi-bonded pins |
US13/223,482 | 2011-09-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2012106311A2 true WO2012106311A2 (en) | 2012-08-09 |
WO2012106311A3 WO2012106311A3 (en) | 2012-10-18 |
Family
ID=46600501
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2012/023281 WO2012106311A2 (en) | 2011-02-04 | 2012-01-31 | Esd clamp for multi-bonded pins |
Country Status (3)
Country | Link |
---|---|
US (1) | US8427799B2 (en) |
TW (1) | TW201236136A (en) |
WO (1) | WO2012106311A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2550977B (en) * | 2016-05-31 | 2020-07-22 | Cirrus Logic Int Semiconductor Ltd | Monitoring of devices |
JP7426702B2 (en) | 2020-02-13 | 2024-02-02 | ザインエレクトロニクス株式会社 | semiconductor equipment |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5239440A (en) * | 1989-12-19 | 1993-08-24 | National Semiconductor Corporation | Electrostatic discharge protection for integrated circuits |
US5900643A (en) * | 1997-05-19 | 1999-05-04 | Harris Corporation | Integrated circuit chip structure for improved packaging |
US6424028B1 (en) * | 1999-09-28 | 2002-07-23 | Koninklijke Philips Electronics N.V. | Semiconductor devices configured to tolerate connection misalignment |
US20060092589A1 (en) * | 2004-10-29 | 2006-05-04 | Dipankar Bhattacharya | Electrostatic discharge protection in a semiconductor device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6873505B2 (en) * | 1999-09-14 | 2005-03-29 | United Microelectronics Corp. | Electrostatic discharge protective circuitry equipped with a common discharge line |
US6678133B2 (en) * | 2001-03-09 | 2004-01-13 | Micron Technology, Inc. | Electrostatic discharge protection with input impedance |
US6842318B2 (en) * | 2001-03-15 | 2005-01-11 | Microsemi Corporation | Low leakage input protection device and scheme for electrostatic discharge |
KR100800152B1 (en) * | 2006-06-30 | 2008-02-01 | 주식회사 하이닉스반도체 | Electrostatic discharge protection circuit |
-
2011
- 2011-09-01 US US13/223,482 patent/US8427799B2/en active Active
-
2012
- 2012-01-31 WO PCT/US2012/023281 patent/WO2012106311A2/en active Application Filing
- 2012-02-03 TW TW101103486A patent/TW201236136A/en unknown
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5239440A (en) * | 1989-12-19 | 1993-08-24 | National Semiconductor Corporation | Electrostatic discharge protection for integrated circuits |
US5900643A (en) * | 1997-05-19 | 1999-05-04 | Harris Corporation | Integrated circuit chip structure for improved packaging |
US6424028B1 (en) * | 1999-09-28 | 2002-07-23 | Koninklijke Philips Electronics N.V. | Semiconductor devices configured to tolerate connection misalignment |
US20060092589A1 (en) * | 2004-10-29 | 2006-05-04 | Dipankar Bhattacharya | Electrostatic discharge protection in a semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US8427799B2 (en) | 2013-04-23 |
US20120200962A1 (en) | 2012-08-09 |
WO2012106311A3 (en) | 2012-10-18 |
TW201236136A (en) | 2012-09-01 |
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