WO2012119380A1

WO2012119380A1 - Code implementing method, system and device for reset vector

Info

Publication number: WO2012119380A1
Application number: PCT/CN2011/078181
Authority: WO
Inventors: 雷镇
Original assignee: 华为技术有限公司
Priority date: 2011-08-10
Filing date: 2011-08-10
Publication date: 2012-09-13
Also published as: CN102326145A; CN102326145B

Abstract

A code implementing method, system and device for a reset vector, applied to the technical field of electronics. The code implementing method for a reset vector includes: when the current core needs to enter a corresponding processing branch, invoking a jump instruction in a reset vector shared by a plurality of cores, with the jump instruction including jmp (processing branch ingress) for indicating that a jump register serves as a processing branch ingress, and the logic addresses of the on-chip private memories corresponding to the plurality of cores being identical; reading a global variable value in the on-chip private memory of the current core, with the global variable value being used for indicating the address of the processing branch ingress corresponding to the current core; and using the read global variable value as the content of the processing branch ingress in the jump instruction, and jumping to the corresponding processing branch ingress in the off-chip shared memory. Therefore, the code implementation process for the reset vector is performed.

Description

Code implementation method, system and device for reset vector

Technical field

The present invention relates to the field of electronic technologies, and in particular, to a code implementation method, system and device for a reset vector.

Background technique

Generally, the processing system includes a processor such as a digital signal processor (DSP), or a central processing unit (CPU), and the like, and the processor may be a single core processor, or It is a multi-core processor. When the processing system enters the business layer for business processing, it needs to be started by the underlying operation, and the code in the executable file (Image file) is loaded into the memory, and the code loaded by the processor to execute the execution in the memory is gradually completed. Kernel hardware resources, BSS (Block Started by Symbol section, libc library, etc. initialization, and finally call the main (main) function in the Image file to enter the business layer for business processing. In the Image file includes code to achieve some functions The processor calls the execution of the code in memory as the implementation of the code.

For a processor that includes a single core, the memory includes a reset vector for power-on or reset-initiation. Before the processor enters the service layer, part of the code of the Image file needs to be loaded into the reset vector. The core processor calls the code loaded in the reset vector to enter the business layer.

For a processor that includes multiple cores, the memory is divided into two types, namely, off-chip shared memory of each core, such as secondary memory (L2), and on-chip private memory corresponding to each core, such as Primary memory (Ll). In one case, a corresponding reset vector may be included in the on-chip private memory of each core, and a specific code in the image file corresponding to each core may be loaded, and each core may be separately from the corresponding on-chip private memory. The reset vector is started to enter the service layer; in another case, at least one reset vector may be included in the off-chip shared memory, and the shared code in the image file corresponding to multiple cores is loaded, and each core can be shared from off-chip. The reset vector in memory is started to enter the service layer, and each core needs to enter the respective processing branches by calling the code of the reset vector. The existing scheme is:

During the execution of the shared reset vector code by each core call, if the current core needs to enter the corresponding processing branch, the core (ie, one processing unit in the processor) will read from the hardware register. The identifier of the pre-core (ID), the jump instruction in the reset vector is called jmp (the image file branch entry name corresponding to the current core identifier), and jumps to the corresponding image file branch entry address, thus realizing the current nuclear jump. Go to the corresponding processing branch.

In the prior art, the implementation of the code in the reset vector is directly bound to the service layout. For example, in service scenario 1, CPU1 executes Image1, and in service scenario 2, CPU1 executes Image0, if a business scenario occurs. When switching, you need to modify the jump instruction in the reset vector, that is, the original jmp ( Image 1 ) is modified to jmp ( Image 0 ), so that each core can be jumped to the correct processing after processing the shared reset vector. Branch; and the underlying layer also needs to release a new Lib library to the business layer. In this way, when the service scenario changes, the code in the reset vector needs to be modified and reloaded into the memory of the processing system to enter the service layer, which is complicated.

Summary of the invention

The embodiment of the invention provides a code implementation method, system and device for a reset vector, which realizes that the implementation of the code in the reset vector shared by multiple cores of the multi-core processor is independent of the service layout, thereby simplifying the reset vector when the service scene changes. The implementation process of the code.

Embodiments of the present invention provide a code implementation method for a reset vector, including:

When the current core needs to enter the corresponding processing branch, the jump instruction in the reset vector of the multiple cores is called, and the jump instruction includes jmp (processing branch entry), and the register for indicating the jump is the processing branch entry. The logical addresses of the on-chip private memory corresponding to the plurality of cores are the same;

Reading a global variable value in the on-chip private memory of the current core, where the global variable value is used to indicate a processing branch entry address corresponding to the current core;

The read global variable value is used as the processing branch entry in the jump instruction, and jumps to the corresponding processing branch entry in the off-chip shared memory.

The embodiment of the invention provides a processor core, which includes:

a function calling unit, configured to invoke a jump instruction in a reset vector of a plurality of cores when the current core needs to enter a corresponding processing branch, where the jump instruction includes jmp (processing branch entry), a register for indicating a jump To process the branch entry, the logical addresses of the on-chip private memory corresponding to the multiple cores are the same;

a variable reading unit, configured to read a global variable value in the on-chip private memory of the current core, where the global variable value is used to indicate a processing branch entry address corresponding to the current core; And a jump unit, configured to use the global variable value read by the variable reading unit as the processing branch entry in the jump instruction, and jump to a corresponding processing branch entry in the off-chip shared memory.

An embodiment of the present invention provides a multi-core processor, including: multiple cores, on-chip private memory corresponding to each core, and off-chip shared memory;

The core, when the current core needs to enter a corresponding processing branch, invokes a jump instruction in a reset vector shared by multiple cores, where the jump instruction includes jmp (processing branch entry), a register for indicating a jump In order to process the branch entry, the logical addresses of the on-chip private memory corresponding to the multiple cores are the same; the global variable value in the on-chip private memory of the current core is read, and the global variable value is used to indicate the current core Corresponding processing branch entry address; using the read global variable value as the processing branch entry in the jump instruction, and jumping to a corresponding processing branch entry in the off-chip shared memory;

The on-chip private memory is used to store a global variable value of the corresponding core;

The off-chip shared memory is used to load a reset vector shared by the plurality of cores, and a processing branch of each core.

The embodiment of the invention further provides a processing system, including the multi-core processor described above.

Embodiments of the present invention provide a computer system including an external interface, a chip shared memory, and a bus, wherein the computer system further includes the multi-core processor.

In the embodiment of the present invention, when a reset vector is shared by multiple cores in a multi-core processor, in the code implementation process of the reset vector, each core calls a jump instruction in the reset vector, and reads a global variable in the corresponding on-chip private memory. The value, the global variable value to be read is used as the content of the jump register in the jump instruction, so that the current core jumps to the corresponding processing branch entry.

Since the logical addresses of the on-chip private memory corresponding to the multiple cores are the same, the global read in the reset vector is the same for the jumps in the jump instruction for the multiple cores, and the processing branches in the reset vector jump to the respective cores. The code for the entry will not change as the core changes. Therefore, if the business scenario changes, there is no need to modify the code of the reset vector, but the global variable value stored in the on-chip private memory of the corresponding core needs to be updated. The realization of the code in the reset vector shared by multiple cores in the multi-core processor is independent of the service layout, thereby simplifying the implementation process of the code in the reset vector when the service scene changes.

DRAWINGS In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.

1 is a schematic structural diagram of a multi-core processor according to an embodiment of the present invention;

2 is a flowchart of a code implementation method of a reset vector according to an embodiment of the present invention; FIG. 3 is a schematic structural diagram of loading an executable file into a memory according to an embodiment of the present invention; When two cores share a reset vector, the code implementation of the reset vector is implemented during the startup of each core from the off-chip shared memory;

5 is a schematic structural diagram of a processor core according to an embodiment of the present invention;

6 is a schematic structural diagram of another processor core according to an embodiment of the present invention;

7 is a schematic structural diagram of a multi-core processor according to an embodiment of the present invention;

8 is a schematic structural diagram of a chip of a processing system in an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a computer system according to an embodiment of the present invention.

detailed description

BRIEF DESCRIPTION OF THE DRAWINGS The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative work are within the scope of the present invention.

A code implementation method for a reset vector provided by an embodiment of the present invention is applicable to a case where multiple cores share a reset vector in a multi-core processor.

Referring to FIG. 1 , for a multi-core processor, a memory and a plurality of cores, that is, multiple processing units, wherein the core in the processor may be a CPU, a DSP, a CPU, and a DSP may also be used. The other cores are illustrated by two CPUs and two DSPs in Figure 1. The memory can be divided into two types, namely, the on-chip private memory corresponding to each core (such as L1), and the off-chip shared by each core. Shared memory (such as L2).

In the embodiment of the present invention, at least one reset vector is included in the off-chip shared memory. In FIG. 1, two reset vectors are taken as an example, that is, a first reset vector shared by two CPUs and a second reset shared by two DSPs. vector. In these shared reset vectors, you can load image files corresponding to multiple cores. In the shared code, each core can be started from the reset vector in the off-chip shared memory to enter the service layer, and each core needs to enter the respective processing branches by calling the code of the reset vector, specifically:

Each core can be implemented by the code implementation method of the reset vector of the present invention, thereby entering the respective processing branches. The method flow chart is as shown in FIG. 2, and includes:

Step 101: When the current core needs to enter the corresponding processing branch, call a jump instruction in the reset vector of the multiple cores, where the jump instruction includes jmp (processing branch entry).

It can be understood that, as shown in FIG. 3, before the processing system is powered on, each core needs to first load the code of the corresponding Image file into the on-chip private memory and the off-chip shared memory, specifically, the image file. The content of the on-chip private memory (in the case of L1 is loaded) is loaded into the on-chip private memory of the corresponding core (as shown in Figure 3 with black dots), including the value of the global variable, where the global variable can be recorded. The image file process (Image Dispatch), and the value of the global variable is used to indicate the processing branch entry address corresponding to the corresponding core; the content of the off-chip shared memory in the Image file is loaded into the off-chip shared memory, including the corresponding processing of each core. Branch code and data; Load the code of the reset vector in the Image file (the portion filled with the slash in Figure 3) into the reset vector in the off-chip shared memory.

After loading the code of the Image file, each core is started from the reset vector in the off-chip shared memory (ie, the code implementation process of the reset vector). Specifically, each core will call the code loaded in the execution reset vector to be completed step by step. Kernel hardware resources, BSS segments, libc libraries, etc. are initialized, and finally the main function is called to enter the business layer for business processing.

In the above process of entering the service layer, each core needs to enter the respective processing branches by calling the code of the reset vector. For one of the cores, if the current core needs to enter the corresponding processing branch, it needs to call the jump instruction in the reset vector and execute the jump instruction to enter the processing branch. The jump instruction includes jmp ( X ), where X represents a jump register, and in the embodiment of the present invention, the jump register is a processing branch entry, which can be recorded as an image file process entry (Image Dispatch Entry), then the implementation In the example, the jump instruction is used to indicate that the jump register is the processing branch entry. For multiple cores sharing a reset vector, the register X of the jump in the jump instruction is the same, and the binary code of the jump instruction of the multiple cores to the corresponding processing branch is the same.

Step 102: Read a global variable value in the on-chip private memory of the current core, where the global variable value is used. Indicates the processing branch entry address corresponding to the current core.

It can be understood that, in the embodiment of the present invention, the logical addresses of global variables loaded in the on-chip private memory of each core are the same, but the global variable values are different. Before each core performs the above loading process, the access to the on-chip private memory and L2 is a link technology, which is directly linked to the corresponding space through the link script, and multiple cores access the corresponding on-chip private memory. The logical address is the same. For multiple cores, the code segment of the reset vector is the same during the process of reading the global variable value.

Step 103: The global variable value read in step 102 is used as the processing branch entry in the jump instruction, and jumps to the corresponding processing branch entry in the off-chip shared memory.

When the core executes the jump instruction, the read global variable value is used as the jump register in the jump instruction, that is, the content of the branch entry is processed. Specifically, the core reads the value of the global variable read in step 102 to the jump. The register that jumps in the instruction is processed in the branch entry, that is, the X in jmp ( X ), and the jump is implemented according to the specific content in the jump register X, thereby realizing the current core jump to the corresponding processing branch entry. .

It can be seen that, in the embodiment of the present invention, when multiple cores share a reset vector in the multi-core processor, in the code implementation process of the reset vector, each core calls a jump instruction in the reset vector, and reads the corresponding in-chip private memory. The global variable value is used as the content of the jump register in the jump instruction, so that each core jumps to the corresponding processing branch entry.

Since the logical addresses of the on-chip private memory corresponding to the multiple cores are the same, the code for reading the global variable value in the reset vector does not change with the change of the branch entry address of each core corresponding processing branch; and for multiple cores If the jump register in the jump instruction is the same, the code in the reset vector that jumps to the processing branch entry of each core will not change with the change of the core. Therefore, if the business scenario changes, such as in business scenario 1, CPU1 executes Image1, and in business scenario 2, CPU2 executes Image1, and when switching from service scenario 1 to business scenario 2, in the reset vector. The code segment for reading the global variable value and the jump does not change, and there is no need to modify the code of the reset vector, but it is necessary to update the value of the global variable stored in the on-chip private memory of the corresponding core. The implementation of the code in the reset vector shared by multiple cores in the multi-core processor is independent of the service layout, thereby simplifying the implementation process of the code in the reset vector when the service scene changes.

It should be noted that multiple cores can be simultaneously activated from the reset vector in the off-chip shared memory. The lines may also be sequentially executed. The above steps 101 to 103 are only the code implementation methods of the reset vector in the process of one of the core starts. Before performing the above steps, the processing branch entry addresses corresponding to the cores are respectively stored as global variable values in the on-chip private memory of each core.

Referring to FIG. 4, when two cores 0 and 1 share a reset vector, in the process of starting each core from the L2 layer, a code implementation diagram of the reset vector is obtained, in which each core is read from its own on-chip private memory. Take the value of the global variable, use this value as the processing branch entry address of each core and jump to the processing branch entry. And in the reset vector, the two cores 0 and 1 are identical for reading the global variable values in the respective on-chip private memory and jumping to the code segment of the processing branch entry. The embodiment of the invention provides a processor core, which may be a CPU or a DSP. The schematic diagram of the structure is as shown in FIG. 5, and includes:

The function invoking unit 10 is configured to invoke a jump instruction in a reset vector of the plurality of cores when the current core needs to enter the corresponding processing branch, where the jump instruction includes jmp (processing branch entry), and is used to indicate the jump The register is a processing branch entry, and the logical addresses of the on-chip private memory corresponding to the multiple cores are the same;

The variable reading unit 11 is configured to read a global variable value in the on-chip private memory of the current core, where the global variable value is used to indicate a processing branch entry address corresponding to the current core;

The jump unit 12 is configured to use the global variable value read by the variable reading unit 10 as the processing branch entry in the jump instruction called by the function calling unit 11 to jump to the corresponding content in the off-chip shared memory. Process branch entries.

Specifically, the jump unit 12 reads the value of the global variable read by the variable reading unit 11 into the jump register in the jump instruction, that is, processes the branch entry, and implements according to the specific content in the jump register. Jump, thereby implementing the current core jump to the corresponding processing branch entry.

It should be noted that the multiple cores sharing the reset vector have the same global logical address stored in the private memory of the slice, and the difference is the specific value of the global variable; and multiple cores execute the jump instruction of the reset vector. The binary code of the jump instruction called is the same.

It can be seen that, when the processor core of the embodiment of the present invention shares the reset vector with other processor cores, in the code implementation process of the reset vector, the function calling unit 10 of each core calls the jump instruction in the reset vector, and the variable reading unit 11 reads the value of the global variable in the private memory corresponding to the slice, and the jump unit 12 uses the value of the global variable read as the content of the jump register in the jump instruction, thereby implementing the core jump Go to the corresponding processing branch entry.

Since the logical addresses of the on-chip private memory corresponding to the multiple cores are the same, the code for reading the global variable value in the reset vector does not change with the change of the processing branch entry of each core; and for multiple cores The registers that jump in the jump instruction are the same, and the code in the reset vector that jumps to the processing branch entry of each core does not change as the core changes. Therefore, if the business scenario changes, the code segment that reads the global variable value and the jump in the reset vector does not change, and the code of the reset vector does not need to be modified. The implementation of the code in the reset vector of multiple cores shared by the multi-core processor is independent of the service layout, thereby simplifying the implementation process of the code in the reset vector when the service scene changes.

Referring to FIG. 6, in other specific processor core embodiments, the processor core includes, in addition to the structure shown in FIG. 5, an address storage unit 13 and a variable value updating unit 14, wherein:

The address storage unit 13 is configured to store the processing branch entry address corresponding to the current core as a global variable value in the on-chip private memory of the current core;

The variable value updating unit 14 is configured to update the global variable value stored in the on-chip private memory of the current core.

The address storage unit 13 in this embodiment may store the global variable value in the on-chip private memory of the core as the processing branch entry address corresponding to the core; if the service scenario changes, for example, in the service scenario 1, the CPU 1 executes correspondingly. Image 1 , and in the business scenario 2, the CPU 2 executes Image 1 correspondingly. When switching from the business scenario 1 to the business scenario 2, the variable value updating unit 14 may update the global variable value stored in the on-chip private memory of the core. The embodiment provides a multi-core processor, which may be a CPU or a DSP. The schematic diagram of the structure is as shown in FIG. 7, and includes a plurality of cores 20, on-chip private memory 21 corresponding to each core, and off-chip shared memory 22. among them:

The core 20 is configured to invoke a jump instruction in a reset vector shared by multiple cores when the current core needs to enter a corresponding processing branch, where the jump instruction includes jmp (processing branch entry), and is used to indicate a jump. The register is a processing branch entry, and the logical addresses of the on-chip private memory corresponding to the plurality of cores are the same;; reading a global variable value in the on-chip private memory of the current core, the global variable value is used to indicate the Processing branch entry address corresponding to the current core; using the read global variable value as the The jump instruction processes the contents of the branch entry, and jumps to the corresponding processing branch entry in the off-chip shared memory;

The on-chip private memory 21 (illustrated by L1 in FIG. 7) is used to store the global variable value of the corresponding core;

The off-chip shared memory 22 (illustrated by L2 in FIG. 7) is used to load the reset vector code of the plurality of core shares, and the processing branches of the cores.

It can be understood that the structure of the core 20 in this embodiment is similar to the processor core structure shown in FIG. 5 or 6, and in the process of starting the core 20 from the off-chip shared memory, the code implementation method of the reset vector is as shown in FIG. 2 . The flow chart is not mentioned here.

It should be noted that, in the multi-core processor of the embodiment, the plurality of cores 20, the on-chip private memory 21 corresponding to each core, and the off-chip shared memory 22 may be integrated on one chip. The embodiment of the present invention further provides a processing system, which may include at least one multi-core processor as shown in FIG.

The multi-core processor in the processing system of this embodiment may be a CPU or a DSP; and may further include a CPU and a digital signal processor DSP. In this case, multiple CPUs may share the first reset vector, multiple DSPs. The second reset vector can be shared. The first reset vector and the second reset vector referred to herein do not represent a sequential relationship, but rather illustrate the difference in the reset vector. The plurality of CPUs share the first reset vector and/or the plurality of digital signal processors DSP share the second reset vector.

Referring to FIG. 8, in a specific embodiment, a chip of a processing system includes: 2 clusters, that is, a CPU cluster and a DSP cluster, wherein: for each cluster, a multi-core processor includes 4 cores, each core has a corresponding on-chip private memory such as L1, and 4 cores share an off-chip shared memory, that is, L2. The chip can also include off-chip shared memory of all multi-core processors on the chip, namely three-level memory (L3) and double data rate (DDR).

The structure of the DSP and the CPU in the chip can be as shown in Fig. 5 or Fig. 6, and will not be mentioned here. The embodiment of the present invention further provides a computer system, which is a processing system in a specific application. The schematic diagram of the structure is as shown in FIG. 9, including: external interfaces (interfaces) 30, chip shared memory (memory) 32 such as DDR, bus ( Bus) 31 and multi-core processor 33.

Wherein the bus 31 is used to connect all the hardware in the computer system; and the external interface 30 is connected to On the bus 31, an external device for connecting to the computer system; the chip shared memory 32 is connected to the bus 31, which is a shared memory of all the processor cores in the computer system; the structure of the multi-core processor can be as shown in FIG. 5 or 6, This is not a comment.

A person skilled in the art may understand that all or part of the various steps of the foregoing embodiments may be completed by a program instructing related hardware. The program may be stored in a computer readable storage medium, and the storage medium may include: ROM, RAM, disk or CD, etc.

The code implementation method, system and device for the reset vector provided by the embodiment of the present invention are described above. The description of the above embodiment is only for helping to understand the method and core idea of the present invention; meanwhile, it is for those skilled in the art. The present invention is not limited by the scope of the present invention.

Claims

Rights request

A code implementation method for a reset vector, comprising:

When the current core needs to enter the corresponding processing branch, the jump instruction in the reset vector of the multiple cores is called, and the jump instruction includes jmp (processing branch entry), and the register for indicating the jump is the processing branch entry; The logical addresses of the on-chip private memory corresponding to the plurality of cores are the same;

2. The method according to claim 1, wherein the reading the global variable value in the on-chip private memory of the current core comprises:

The processing branch entry address corresponding to the current core is stored as a global variable value in the on-chip private memory of the current core.

3. The method according to claim 1 or 2, further comprising:

Updating the global variable value stored in the on-chip private memory of the current core.

The method according to any one of claims 1 to 3, wherein the core comprises: a central processor CPU, and/or a digital signal processor DSP;

The reset vector includes a first reset vector, and/or a second reset vector;

The plurality of CPUs share the first reset vector and/or the plurality of digital signal processors DSP share the second reset vector.

5. A processor core, comprising:

a variable reading unit, configured to read a global variable value in the on-chip private memory of the current core, where the global variable value is used to indicate a processing branch entry address corresponding to the current core;

And a jump unit, configured to use the global variable value read by the variable reading unit as the processing branch entry in the jump instruction, and jump to a corresponding processing branch entry in the off-chip shared memory.

The processor core of claim 5, further comprising:

The address storage unit is configured to store the processing branch entry address corresponding to the current core as a global variable value in the on-chip private memory of the current core.

The processor core according to claim 5 or 6, further comprising:

And a variable value updating unit, configured to update a global variable value stored in the on-chip private memory of the current core.

8. A multi-core processor, comprising: a plurality of cores, on-chip private memory corresponding to each core, and off-chip shared memory;

The multi-core processor according to claim 8, wherein the core is the processor core according to any one of claims 5 to 7.

The multi-core processor according to claim 8 or 9, wherein the core is: a central processing unit CPU, or a digital signal processor DSP.

A processing system, comprising at least one multi-core processor according to claim 8 or 9.

The processing system according to claim 11, wherein the multi-core processor is a central processor CPU, and/or a digital signal processor DSP;

The reset vector includes a first reset vector, and/or a second reset vector;

13. A computer system comprising an external interface, a chip shared memory, and a bus, wherein The computer system also includes the multi-core processor of claim 8 or 9.