WO2013117155A1 - Semiconductor structure and method for forming same - Google Patents

Semiconductor structure and method for forming same Download PDF

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Publication number
WO2013117155A1
WO2013117155A1 PCT/CN2013/071398 CN2013071398W WO2013117155A1 WO 2013117155 A1 WO2013117155 A1 WO 2013117155A1 CN 2013071398 W CN2013071398 W CN 2013071398W WO 2013117155 A1 WO2013117155 A1 WO 2013117155A1
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Prior art keywords
substrate
single crystal
crystal semiconductor
layer
semiconductor layer
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PCT/CN2013/071398
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French (fr)
Inventor
Lei Guo
Yuan Li
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Lei Guo
Yuan Li
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Priority claimed from CN201210027809.4A external-priority patent/CN103247516B/en
Priority claimed from CN201210027752.8A external-priority patent/CN103247724B/en
Application filed by Lei Guo, Yuan Li filed Critical Lei Guo
Publication of WO2013117155A1 publication Critical patent/WO2013117155A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present disclosure relates to semiconductor design and fabrication field, and more particularly to a semiconductor structure and a method for forming the same.
  • heterogeneous semiconductor materials are required to be obtained on a single substrate.
  • these materials are significantly different from a material of the substrate in characteristics. For example, a difference of a lattice structure or a lattice constant may result in a high dislocation density which seriously affects a device performance; a difference of thermal expansion coefficient may result in cracks of a heterogeneous material film on the substrate, even of the whole wafer, during a cooling stage of an epitaxy process.
  • a technique for forming heterogeneous semiconductor materials on a single substrate is urgently needed.
  • the present disclosure is aimed to solve at least one of the defects.
  • a method for forming a semiconductor structure comprises steps of: providing a substrate; forming a first single crystal semiconductor layer on the substrate; etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate; etching the substrate through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate, thus forming a patterned structure on the porous structure; and depositing a single crystal semiconductor material to form a second single crystal semiconductor layer on the patterned structure.
  • depositing a single crystal semiconductor material to form a second single crystal semiconductor layer on the patterned structure comprises: epitaxially laterally growing a single crystal semiconductor material on a lateral surface of the first single crystal semiconductor layer exposed in the plurality of holes or trenches.
  • the method further comprises: epitaxially longitudinally growing and then epitaxially laterally over-growing the single crystal semiconductor material on a top surface of the first single crystal semiconductor layer to form the second single crystal semiconductor layer.
  • epitaxial lateral overgrowth ELOG
  • a dislocation density is significantly reduced.
  • the substrate has a patterned surface.
  • the method before forming a first single crystal semiconductor layer on the substrate, the method further comprises: forming a buffer layer on the substrate.
  • the buffer layer has a single-layer structure, a multi-layer superlattice structure or a multi-layer interlaced structure.
  • etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate comprises: forming a mask layer on the first single crystal semiconductor layer; etching the mask layer to form a plurality of openings; and etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate.
  • a material of the substrate comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga 2 0 3 , A1 2 0 3 , A1N, ZnO, LiGa0 2 and LiA10 2 .
  • etching the substrate through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate comprises: etching the substrate by an electrochemical etch when the substrate is conductive; and etching the substrate by a wet etch when the substrate is nonconductive.
  • the method further comprises: implanting different types and/or different concentrations of doping elements into the substrate to form a plurality of etch resistant structures below a top surface of the substrate, which enables a lateral etching during a process of forming the porous structure.
  • a material of the first single crystal semiconductor layer comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga 2 0 3 , ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof.
  • the method further comprises: if a material of the substrate is Si, after etching the substrate through the plurality of holes or trenches to form a porous structure, processing the substrate in a nitrogenous and/or oxygenous ambience to enable the porous structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation layer.
  • a material of the isolation layer is Si0 2 , SiON or SiN.
  • single crystal Si becomes amorphous oxide or nitride, which is more advantageous for releasing a thermal mismatch stress; in another aspect, the isolation layer may be helpful to separate the Si substrate from the first single crystal semiconductor layer during a late fabrication process of a device (such as an LED) so that the Si substrate can be recycled.
  • the first single crystal semiconductor layer and/or the second single crystal semiconductor layer have a multi-layer compound semiconductor structure.
  • the method further comprises: dividing the substrate into a plurality of blocks by deep trench etching to prevent a stress accumulation in a large scale.
  • the substrate may use a low cost rough material (such as a Si wafer), a high quality heterogeneous thin film may be obtained, and a process is simple and realizable.
  • a stress resulted from thermal mismatch may be effectively released by the porous structure, which is advantageous for further fabricating a large size of single crystal semiconductor layer thereon, such as the second single crystal semiconductor layer with a very large thickness (above dozens of microns) and a large diameter (a basic size may be up to 8-12 inches even 18 inches).
  • the porous structure is formed subsequent to forming the first single crystal semiconductor layer, and thus many unfavorable factors resulted from a direct epitaxy of heterogeneous materials on the porous structure are avoided. Therefore, a perfect interface between the porous structure and the first single crystal semiconductor layer can be ensured. Meanwhile, a growth quality of the first single crystal semiconductor layer and the second single crystal semiconductor layer can be ensured.
  • a semiconductor structure comprises: a substrate; a porous structure formed on a top surface of the substrate; a first single crystal semiconductor layer formed on the porous structure, a plurality of holes or trenches buried in the first single crystal semiconductor layer and extending to the porous structure; and a second single crystal semiconductor layer formed on the first single crystal semiconductor layer, covering and extending to the plurality of holes or trenches.
  • the substrate has a patterned surface.
  • the semiconductor structure further comprises a buffer layer formed on the substrate.
  • the buffer layer has a single-layer structure, a multi-layer superlattice structure or a multi-layer interlaced structure.
  • the semiconductor structure further comprises a mask layer formed on the first single crystal semiconductor layer, wherein the mask layer is divided into a plurality of discrete masks by the plurality of holes or trenches.
  • a material of the substrate comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga 2 0 3 , A1 2 0 3 , A1N, ZnO, LiGa0 2 , and LiA10 2 .
  • the porous structure is formed by an electrochemical etch when the substrate is conductive; and the porous structure is formed by a wet etch when the substrate is nonconductive.
  • the semiconductor structure further comprises a plurality of etch resistant structures formed below the top surface of the substrate by implanting different types and/or different concentrations of doping elements in the substrate.
  • a material of the first single crystal semiconductor layer comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga 2 0 3 , ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof.
  • the semiconductor structure further comprises an isolation layer formed by a reaction of the porous structure with a nitrogenous and/or oxygenous ambience, if a material of the substrate is Si.
  • the first single crystal semiconductor layer and/or the second single crystal semiconductor layer have a multi-layer compound semiconductor structure.
  • the substrate further comprises a plurality of deep trenches, by which the substrate is divided into a plurality of blocks to prevent a stress accumulation in a large scale.
  • the semiconductor structure according to embodiments of the present disclosure has advantages of low dislocation density, high quality thin film and low material cost. Moreover, a stress resulted from thermal mismatch may be effectively released by the porous structure.
  • Figs. 1-10 are schematic cross- sectional views of intermediate statuses of a semiconductor structure formed in steps of a method for fabricating a semiconductor structure according to a first embodiment of the present disclosure
  • Figs. 11-20 are schematic cross-sectional views of intermediate statuses of a semiconductor structure formed in steps of a method for fabricating a semiconductor structure according to a second embodiment of the present disclosure
  • Fig. 21 is a schematic cross-sectional view of the semiconductor structure according to the first embodiment of the present disclosure.
  • Fig. 22a is a schematic cross-sectional view of the semiconductor structure according to another embodiment of the present disclosure.
  • Fig. 22b is a schematic top view of the semiconductor structure according to the another embodiment of the present disclosure.
  • Fig. 23 is a schematic cross-sectional view of the semiconductor structure according to the second embodiment of the present disclosure.
  • phraseology and terminology used herein with reference to device or element orientation are only used to simplify description of the present invention, and do not alone indicate or imply that the device or element referred to must have or operated in a particular orientation.
  • first and second are used herein for purposes of description and are not intended to indicate or imply relative importance or significance or imply a number of technical features indicated. Therefore, a “first” or “second” feature may explicitly or implicitly comprise one or more features. Further, in the description, unless indicated otherwise, "a plurality of refers to two or more.
  • FIGs. 1-10 are schematic cross-sectional views of intermediate statuses of the semiconductor structure formed in steps of the method for forming the semiconductor structure according to a first embodiment.
  • the method for forming the semiconductor structure comprises following steps.
  • step S101 as shown in Fig. 1, a substrate 100 is provided.
  • the substrate 100 may have a patterned surface.
  • the substrate 100 may be a patterned Si substrate or a patterned sapphire substrate.
  • Such patterned substrate may be favorable for a reduction of a dislocation density of an epitaxial layer formed thereon, as well as for an emission of LED light.
  • a material of the substrate 100 may comprise any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga 2 0 3 , A1 2 0 3 , A1N, ZnO, LiGa0 2 and LiA10 2 .
  • the substrate 100 is a Si substrate, which is not only low-cost and easy to be doped, but also easy to react to form a hetero isolation layer.
  • etch resistant structures 1001 below a top surface of the substrate 100. More preferably, different types and/or different concentrations of doping elements are implanted in the substrate 100 to form a large area of etch region 1002.
  • the plurality of etch resistant structures 1001 and the etch region 1002 enables a following etch to be lateral-oriented. Specifically, as shown in Fig.
  • the substrate 100 is n-type locally doped by an ion implantation to form the plurality of n-type etch resistant structures 1001 at a certain depth below the top surface of the substrate 100, and then the substrate 100 is p-type heavily doped at a smaller depth below the top surface of the substrate 100 to form the large area of etch region 1002, while a bottom region of the substrate 1000 remaining unchanged.
  • this embodiment is explanatory and illustrative, but not construed to limit the present disclosure.
  • a first single crystal semiconductor layer 200 is formed on the substrate 100.
  • a material of the first single crystal semiconductor layer 200 comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga 2 0 3 , ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof, such as a combination of a AIN/GaN layer and a GaAs/AlGaAs layer.
  • the first single crystal semiconductor layer 200 may have a multi-layer compound structure.
  • the multi-layer compound structure may be a superlattice structure, a compound structure with gradient distribution (gradually increasing) of composition (such as a SiGe layer with gradient distribution of Ge), or a compound structure with different compositions distributed alternatively (such as GaN and A1N distributed alternatively).
  • step SI 03 as shown in Fig. 4, the first single crystal semiconductor layer 200 is etched to form a plurality of openings.
  • the plurality of openings are in alignment with the plurality of etch resistant structures 1001 in a vertical direction respectively.
  • the first single crystal semiconductor layer 200 becomes a plurality of first single crystal semiconductor structures (still denoted as 200).
  • step S104 the substrate 100 is etched from the plurality of openings to form a plurality of holes or trenches extending into the substrate 100.
  • a depth of each hole or trench is greater than a width of each hole or trench.
  • this step may be skipped.
  • the plurality of openings formed in step SI 03 are equal to the plurality of holes or trenches formed in step SI 04, that is, the plurality of holes or trenches extends to the top surface of the substrate 100.
  • step S105 as shown in Fig. 6, the substrate 100 is etched through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate 100, thus forming a patterned structure on the porous structure.
  • the substrate 100 When the substrate 100 is conductive, the substrate 100 may be etched by an electrochemical etch; and when the substrate 100 is nonconductive, the substrate 100 may be etched by a wet etch.
  • the porous structure is formed by the electrochemical etch with HF as an etching reagent. Since the smaller a resistivity is, the deeper the etch is, by controlling the resistivity of the Si substrate 100 and the first single crystal semiconductor layer 200, the porous structure can be formed on the surface of the substrate 100 while the first single crystal semiconductor layer 200 is hardly etched.
  • an etch resistant layer may be formed at a bottom of the etch region 1002 by implanting different types and/or different concentrations of doping elements in different regions below the top surface of the substrate 100.
  • the etch resistant layer has a conductive type different from the etch region 1002 and/or a resistivity higher than that of the etch region 1002, thus inducting a lateral expansion of the electrochemical etch to form the porous structure in the whole etch region 1002.
  • the porous structure is formed by the wet etch.
  • the substrate Prior to the wet etch, the substrate may be processed by an ion implantation so that a crystal structure of a local surface region of the substrate is damaged or denatured, which is favorable for the formation of the porous structure using the wet etch.
  • step S106 as shown in Fig. 7, if the material of the substrate is Si, after etching the substrate through the plurality of holes or trenches to form the porous structure, under a high temperature condition or in a plasma ambience with a relative high temperature, the substrate is processed in a nitrogenous and/or oxygenous ambience (such as any one of 0 2 , H 2 0, NH 3 , N 2 , 0 3 , oxygen plasma, nitrogen plasma and a combination thereof) to enable the porous structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation layer (arrows shown in Fig. 7 represent inputting a reaction gas).
  • a nitrogenous and/or oxygenous ambience such as any one of 0 2 , H 2 0, NH 3 , N 2 , 0 3 , oxygen plasma, nitrogen plasma and a combination thereof
  • exposed parts of the porous structure react with the nitrogenous and/or the oxygenous ambience to form the isolation layer (Si0 2 , SiON or SiN).
  • the isolation layer Si0 2 , SiON or SiN.
  • NH 3 is input to react with porous Si or SiGe to form amorphous SiN, while the first single crystal semiconductor layer (such as GaN or A1N) remaining unchanged.
  • the porous structure thus becomes the hetero isolation layer.
  • the step SI 06 is an optional step, which can be skipped when the material of the substrate 100 is not Si or SiGe.
  • the isolation layer formed in this step is different from the substrate in material.
  • the amorphous isolation layer (such as amorphous SiN), in one aspect, is more favorable for a release of the thermal mismatch stress, in another aspect, may be served as a lift-off layer to separate the substrate from the first single crystal semiconductor layer, thus conveniently realizing a transfer of an epitaxial film and a recycling of the substrate.
  • step S107 as shown in Figs. 8-10, a single crystal semiconductor material is deposited to form a second single crystal semiconductor layer 300 on the patterned structure.
  • the single crystal semiconductor material may be firstly epitaxially laterally grown on a lateral surface of the first single crystal semiconductor layer 200 exposed in the plurality of holes or trenches. After a while, the plurality of holes or trenches are filled with the single crystal semiconductor material, and the single crystal semiconductor material may be epitaxially longitudinally grown and then continuously epitaxially laterally over-grown until the second single crystal semiconductor layer 300 is formed on the patterned structure.
  • bold-faced arrows represent a flow of a gas source of the single crystal semiconductor material
  • light-faced arrows represent a growth direction of the single crystal semiconductor material.
  • a material of the second single crystal semiconductor layer 300 may also comprise any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga 2 0 3 , ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof.
  • the second single crystal semiconductor layer 300 may have a multi-layer compound structure.
  • the single crystal semiconductor material may be directly deposited on the patterned structure.
  • the plurality of openings are covered by a thick epitaxial layer, thus forming the whole second single crystal semiconductor layer 300.
  • the second single crystal semiconductor layer 300 may be formed based on a characteristic that a lateral growth rate is greater than a longitudinal growth rate in a special process. Specifically, during the deposition of GaN, InGaN or A1N, the single crystal semiconductor material is firstly laterally epitaxially grown on a lateral surface of the first single crystal semiconductor layer 200 exposed in the plurality of holes or trenches.
  • the plurality of holes or trenches are filled with the single crystal semiconductor material, and the single crystal semiconductor material is first longitudinally epitaxially grown and then laterally epitaxially grown, until the whole second single crystal semiconductor layer 300 is formed on the patterned structure, in which an epitaxial lateral overgrowth (ELOG) process is adopted.
  • ELOG epitaxial lateral overgrowth
  • the second single crystal semiconductor layer 300 is mainly formed by lateral growth, the second single crystal semiconductor layer 300 has a very low dislocation density, thus improving a growth quality thereof.
  • the ELOG process may be replaced by a one-step epitaxial growth or other deposition process.
  • the method may further comprise: dividing the substrate into a plurality of blocks by deep trench etching to prevent a stress accumulation in a large scale.
  • This step may be performed prior to any of the above steps.
  • this step is performed accompany with step SI 03 and step SI 04. Because deep trenches are wide, the second single crystal semiconductor layer 300 is disconnected at each deep trench to reduce the stress accumulation.
  • Figs. 11-20 are schematic cross-sectional views of intermediate statuses of the semiconductor structure formed in steps of the method for forming the semiconductor structure according to a second embodiment.
  • the method for forming the semiconductor structure comprises following steps.
  • step S201 as shown in Fig. 11, a substrate 100 is provided.
  • etch resistant structures 1001 below a top surface of the substrate. More preferably, different types and/or different concentrations of doping elements are implanted in the substrate to form a large area of etch region 1002. Forming the plurality of etch resistant structures 1001 and the etch region 1002 enables a following etch to be lateral-oriented. Specifically, as shown in Fig.
  • the substrate 100 is n-type locally doped by ion implantation to form the plurality of n-type etch resistant structures 1001 at a certain depth below the top surface of the substrate, and then the substrate 100 is p-type heavily doped at a smaller depth below the top surface of the substrate to form the large area of etch region 1002, while a bottom region of the substrate 1000 remaining unchanged.
  • this embodiment is explanatory and illustrative, but not construed to limit the present disclosure. Other doping processes may be adopted in practice, provided that when etching different regions, respective etching rate satisfies
  • step S202 as shown in Fig. 13, a buffer layer 110, a first nitride semiconductor layer 200 and a mask layer 210 are sequentially formed on the substrate 100.
  • the buffer layer 110 may have a single-layer low temperature structure (such as an A1N layer), a multi-layer superlattice structure (such as an AIN/AlGaN multi-layer) or a multi-layer interlaced structure (such as a multi-layer combination of AlN/GaN).
  • a material of the first nitride semiconductor layer 200 comprises any one of GaN, InGaN, A1N, AlGaN, InN, AlGalnN and a combination thereof (such as a multi-layer combination of AIN/AlGaN or AlN/GaN).
  • the first nitride semiconductor layer 200 is the A1N layer or the double-layer combination of AlN/GaN.
  • a material of the mask layer 210 comprises any one of Si0 2 , Si x Ni- x , Hf0 2 , Zr0 2 , A1 2 0 3 and a photoresist.
  • step S202 may comprise: sequentially forming a first nitride semiconductor layer 200 and a mask layer 210 on the substrate 100.
  • step S203 as shown in Fig. 14, a plurality of openings are formed by etching the mask layer 210.
  • the plurality of openings are in alignment with the plurality of etch resistant structures 1001 in a vertical direction respectively.
  • the mask layer 210 becomes a plurality of discrete masks.
  • step S204 as shown in Fig. 15, the first nitride semiconductor layer 200, the buffer layer 110 and the substrate 100 are etched from the plurality of openings to form a plurality of holes or trenches extending into the substrate 100 (that is, extending into the etch region 1002).
  • a depth of each hole or trench is greater than a width of each hole or trench.
  • the first nitride semiconductor layer 200 and the buffer layer 110 are etched from the plurality of openings to form a plurality of holes or trenches extending to the top surface of the substrate 100.
  • step S205 the substrate 100 is etched through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate 100, thus forming a patterned structure, that is, the etch region 1002 becomes the porous structure.
  • the substrate 100 may be etched by any one of electrochemical etch, wet etch, dry etch and a combination thereof.
  • step S206 as shown in Fig. 17, if the material of the substrate is Si, after step S205, under a high temperature condition or in a plasma ambience with a relative high temperature, the substrate is processed in a nitrogenous and/or oxygenous ambience (such as any one of 0 2 , H 2 0, NH 3 , N 2 , O3, oxygen plasma, nitrogen plasma and a combination thereof) to enable the porous structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation layer (arrows shown in Fig. 17 represent inputting a reaction gas).
  • exposed parts of the porous structure (Si or SiGe) react with the nitrogenous and/or the oxygenous ambience to form the isolation layer (Si0 2 or SiN).
  • NH 3 is input to react with porous Si or SiGe to form amorphous SiN, while the first nitride semiconductor layer (such as GaN or A1N) remaining unchanged.
  • the porous structure thus becomes the hetero isolation layer.
  • the step S206 is an optional step, which can be skipped when the material of the substrate 100 is not Si or SiGe.
  • the isolation layer formed in this step is different from the substrate in material.
  • the amorphous isolation layer (such as amorphous SiN), in one aspect, is more favorable for a release of the thermal mismatch stress, in another aspect, may be served as a lift-off layer to separate the substrate from the first single crystal semiconductor layer, thus conveniently realizing a transfer of an epitaxial film and a recycling of the substrate.
  • a nitride semiconductor material is deposited to form a second nitride semiconductor layer 300 on the patterned structure.
  • the nitride semiconductor material is firstly epitaxially laterally grown on a lateral surface of the first nitride semiconductor layer 200 exposed in the plurality of holes or trenches.
  • the plurality of holes or trenches are filled with the nitride semiconductor material, and the nitride semiconductor material may be epitaxially longitudinally grown and then continuously epitaxially laterally over-grown until the second nitride semiconductor layer 300 is formed on the patterned structure. Because the second nitride semiconductor layer 300 is formed by a lateral growth, the second nitride semiconductor layer 300 has a very low dislocation density, thus improving a growth quality thereof.
  • a material of the second nitride semiconductor layer 300 may also comprise any one of GaN, InGaN, A1N, AlGaN, InN, AlGalnN and a combination thereof (such as a multi-layer combination of AlGaN/InGaN, AlGaN/GaN, AlGaN/GaN/InGaN or InGaN/GaN).
  • the second nitride semiconductor layer 300 is a GaN layer. It should be noted that, when the mask layer 210 is a photo resist layer, it needs to be removed after step S205. In step S207, alternatively, the second nitride semiconductor layer 300 may be directly formed on the first nitride semiconductor layer 300 by the ELOG process.
  • the lateral epitaxial growth of the second nitride semiconductor layer 300 may be realized by controlling a growth condition.
  • bold-faced arrows represent a flow of a gas source of the nitride semiconductor material
  • light-faced arrows represent a growth direction of the nitride semiconductor material.
  • a growth mode of GaN mainly depends on a growth temperature and a pressure in a growth chamber. The higher the growth temperature is and the lower the pressure is, the more dominant the lateral growth is. Contrariwise, the longitudinal growth is more dominant.
  • a preferred growth condition of GaN may be as follows: the growth temperature is 1100°C, the pressure in the growth chamber is lOOTorr, trimethylgallium is as a gallium source, and NH 3 is as a nitrogen source. If GaN needs to be doped, a certain amount of SiH 4 may be used as an n-type doping source, and a certain amount of Cp 2 Mg may be used as a p-type doping source. As shown in Fig.
  • GaN is continuously grown on the plurality of discrete masks by the ELOG process to form the whole second nitride semiconductor layer 300.
  • the lateral growth is favorable for a reduction of a dislocation density of GaN, thus improving a thickness and a growth quality of the film.
  • the second single crystal semiconductor layer may be formed on the first single crystal semiconductor layer by the lateral growth.
  • the dislocation density of the epitaxial film can be reduced, and the film quality is improved.
  • the first single crystal semiconductor layer is not a porous structure but a single crystal, an epitaxial growth quality of the second single crystal semiconductor layer is further improved.
  • the plurality of holes or trenches and the porous structure are advantageous for releasing the thermal mismatch stress resulted from the film growth process, thus preventing the film from cracking when the epitaxial thickness of the film is larger, and improving the epitaxial thickness and growth quality of the film. It means that it is possible to use the low cost but high thermal mismatch material (such as Si) as the substrate, and it is also favorable for an LED vertical structure. More importantly, since the plurality of holes or trenches and the porous structure are formed after a formation of the first single crystal semiconductor layer, the growth quality of the first single crystal semiconductor layer is not affected by a surface problem of the plurality of holes or trenches and the porous structure. Thus, the high quality first single crystal semiconductor layer may be obtained. Accordingly, the high quality second single crystal semiconductor layer may also be obtained.
  • the surface of the substrate is etched into the porous structure, so that the semiconductor structure obtained is easy to be separated from the substrate.
  • the porous structure reacts to form the hetero isolation layer to further release stress.
  • the isolation layer is favorable for the separation of the substrate.
  • the substrate is divided into a plurality of blocks by deep trench etching, which in one aspect, prevents the stress accumulation in the large scale, and in another aspect, is favorable for division of device.
  • the low cost material (such as Si) is used as the substrate material.
  • the process is simple and the fabrication cost is low.
  • Fig. 21 is a schematic cross-sectional view of the semiconductor structure according to the first embodiment of the present disclosure.
  • the semiconductor structure comprises: a substrate 100, a first single crystal semiconductor layer 200, a porous structure, a second single crystal semiconductor layer 300 and a plurality of holes or trenches.
  • the porous structure is formed on a top surface of the substrate 100 for reducing a thermal stress resulted from a growth process of semiconductor materials.
  • the first single crystal semiconductor layer 200 is formed on the porous structure.
  • the plurality of holes or trenches are buried in the first single crystal semiconductor layer 200 and extend to the porous structure.
  • the second single crystal semiconductor layer 300 is formed on the first single crystal semiconductor layer 200, covering and extending to the plurality of holes or trenches.
  • the substrate 100 may have a patterned surface.
  • the substrate 100 may be a patterned Si substrate or a patterned sapphire substrate.
  • Such patterned substrate may be favorable for a reduction of a dislocation density of an epitaxial layer formed thereon, as well as for an emission of LED light.
  • a material of the substrate 100 may comprise any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga 2 0 3 , A1 2 0 3 , A1N, ZnO, LiGa0 2 and LiA10 2 .
  • the porous structure is formed by an electrochemical etch when the substrate 100 is conductive; and the porous structure is formed by a wet etch when the substrate 100 is nonconductive.
  • Materials of the first single crystal semiconductor layer 200 and the second single crystal semiconductor layer 300 may comprise any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga 2 0 3 , ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof, such as a combination of a AIN/GaN layer and a GaAs/AlGaAs layer.
  • a plurality of etch resistant structures are formed below the top surface of the substrate 100 by implanting different types and/or different concentrations of doping elements in the substrate 100 for introducing a lateral expansion rather than a longitudinal expansion of the electrochemical etch so as to form the porous structure on the whole surface of the substrate.
  • a material of the substrate is Si or SiGe
  • an isolation layer is formed by a reaction of the porous structure with a nitrogenous and/or oxygenous ambience (such as any one of 0 2 , H 2 0, NH 3 , N 2 , 0 3 , oxygen plasma, nitrogen plasma and a combination thereof).
  • the isolation layer is favorable for the separation of the substrate in a following process.
  • the substrate 100 further comprises a plurality of deep trenches, by which the substrate 100 is divided into a plurality of blocks.
  • Figs. 22a and 22b are a schematic cross-sectional view and a top view of the semiconductor structure respectively according to an embodiment of the present disclosure. As shown in Fig. 22a, the substrate 100 is divided into a plurality of blocks. It can be seen from Fig. 22b, besides the second single crystal semiconductor layer 300 which is exposed at a top layer, the substrate 100 is also exposed from the deep trenches. When the substrate 100 is a Si substrate and there is a hetero isolation layer on the top surface of the substrate 100, the hetero isolation layer is exposed from the deep trenches.
  • the semiconductor structure with deep trench isolation prevents the stress accumulation in the large scale, prevents the film from cracking when the epitaxial thickness of the film is larger, and is also favorable for division of device.
  • Fig. 23 is a schematic cross-sectional view of the semiconductor structure according to the second embodiment of the present disclosure.
  • the semiconductor structure comprises: a substrate 100, a buffer layer 110, a first nitride semiconductor layer 200, a mask layer 210, a porous structure, a second nitride semiconductor layer 300 and a plurality of holes or trenches.
  • the porous structure or the porous structure with a hetero isolation layer is formed on a top surface of the substrate 100.
  • the buffer layer 110 is formed on the substrate 100, and an interface between the substrate 100 and the buffer layer 110 is a plane or a patterned structure.
  • the first nitride semiconductor layer 200 is formed on the buffer layer 110.
  • the mask layer 210 is formed on the first nitride semiconductor layer 200 and has a plurality of openings, in which the mask layer 210 is divided into a plurality of discrete masks by the plurality of openings.
  • the plurality of holes or trenches are buried in the first nitride semiconductor layer 200 and extend to the porous structure.
  • the second nitride semiconductor layer 300 is formed on the mask layer 210, covering and extending to the plurality of holes or trenches.
  • the substrate 100 may have a patterned surface.
  • the substrate 100 may be a patterned Si substrate or a patterned sapphire substrate.
  • Such patterned substrate may be favorable for a reduction of a dislocation density of an epitaxial layer formed thereon, as well as for an emission of LED light.
  • a material of the substrate 100 may comprise any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga 2 0 3 , A1 2 0 3 , A1N, ZnO, LiGa0 2 and LiA10 2 .
  • the buffer layer 110 may have a single-layer low temperature structure (such as an A1N layer), a multi-layer superlattice structure (such as an AIN/AlGaN multi-layer) or a multi-layer interlaced structure (such as a multi-layer combination of AIN/GaN).
  • Materials of the first nitride semiconductor layer 200 and the second nitride semiconductor layer 300 may comprise any one of GaN, InGaN, A1N, AlGaN, InN, AlGalnN and a combination thereof (such as a multi-layer combination of AlGaN/InGaN, AlGaN/GaN, AlGaN/GaN/InGaN or InGaN/GaN).
  • a material of the mask layer 210 may comprise any one of Si0 2 , Si x N 1-x , Hf0 2 , Zr0 2 , amorphous A1 2 0 3 and a photoresist.
  • the buffer layer 110 or the mask layer 210 is optional.
  • the semiconductor structure may comprise: a substrate 100, a first nitride semiconductor layer 200, a mask layer 210, a second nitride semiconductor layer 300 and a plurality of holes or trenches.
  • the semiconductor structure may comprise: a substrate 100, a buffer layer 110, a first nitride semiconductor layer 200, a second nitride semiconductor layer 300 and a plurality of holes or trenches.
  • the semiconductor structure according to embodiments of the present disclosure has following advantages.
  • the second single crystal semiconductor layer may be formed on the first single crystal semiconductor layer by the lateral growth.
  • the dislocation density of the epitaxial film can be reduced, and the film quality is improved. More importantly, since the first single crystal semiconductor layer is not a porous structure but a single crystal, the epitaxial growth quality of the second single crystal semiconductor layer is further improved.
  • the plurality of holes or trenches and the porous structure are advantageous for releasing the thermal mismatch stress resulted from the film growth process, thus preventing the film from cracking when the epitaxial thickness of the film is larger, and improving the epitaxial thickness and growth quality of the film. It means that it is possible to use the low cost but high thermal mismatch material (such as Si) as the substrate, and it is also favorable for an LED vertical structure. More importantly, since the plurality of holes or trenches and the porous structure are formed after a formation of the first single crystal semiconductor layer, the growth quality of the first single crystal semiconductor layer is not affected by a surface problem of the plurality of holes or trenches and the porous structure. Thus, the high quality first single crystal semiconductor layer may be obtained. Accordingly, the high quality second single crystal semiconductor layer may be obtained.
  • the surface of the substrate is etched into the porous structure, so that the semiconductor structure obtained is easy to be separated from the substrate.
  • the porous structure reacts to form the hetero isolation layer to further release stress.
  • the isolation layer is favorable for the separation of the substrate.
  • the substrate is divided into a plurality of blocks by deep trench etching, which in one aspect, prevents the stress accumulation in the large scale, and in another aspect, is favorable for division of device.
  • the low cost material (such as Si) is used as the substrate material.
  • the process is simple and the fabrication cost is low.

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Abstract

A method for forming a semiconductor structure is provided. The method comprises steps of: providing a substrate (100); forming a first single crystal semiconductor layer (200) on the substrate (100); etching the first single crystal semiconductor layer (200) to form a plurality of holes or trenches extending to a top surface of the substrate (100), or etching the first single crystal semiconductor layer (200) and the substrate (100) to form a plurality of holes or trenches extending into the substrate (100); etching the substrate (100) through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate (100), thus forming a patterned structure on the porous structure; and depositing a single crystal semiconductor material to form a second single crystal semiconductor layer (300) on the patterned structure.

Description

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to and benefits of the following applications:
( 1 ) Chinese Patent Application Serial No. 201210027752.8, filed with the State Intellectual Property Office of P. R. China on Feb. 8, 2012; and
( 2 ) Chinese Patent Application Serial No. 201210027809.4, filed with the State Intellectual Property Office of P. R. China on Feb. 8, 2012.
The entire contents of which are incorporated herein by reference.
FIELD
The present disclosure relates to semiconductor design and fabrication field, and more particularly to a semiconductor structure and a method for forming the same.
BACKGROUND
Recently, with a development of semiconductor technique, an integration of different types of heterogeneous semiconductor materials on one substrate has attracted more attentions, such as GaN on Si, GaAs on Si, Ge on Si, etc. Different applications such as a power semiconductor device, a photoelectric device or a high speed logic device, generally need different semiconductor materials. For example, taking into account of a breakdown voltage, a large band gap semiconductor material such as SiC or GaN is required by the power semiconductor device, a direct band gap semiconductor material such as GaAs or GaN is required by the photoelectric device, a semiconductor material such as SiGe is required by the high speed logic device.
In order to enable more complex functions on one chip, high quality heterogeneous semiconductor materials are required to be obtained on a single substrate. However, these materials are significantly different from a material of the substrate in characteristics. For example, a difference of a lattice structure or a lattice constant may result in a high dislocation density which seriously affects a device performance; a difference of thermal expansion coefficient may result in cracks of a heterogeneous material film on the substrate, even of the whole wafer, during a cooling stage of an epitaxy process. To this end, a technique for forming heterogeneous semiconductor materials on a single substrate is urgently needed. SUMMARY
The present disclosure is aimed to solve at least one of the defects.
According to an aspect of the present disclosure, a method for forming a semiconductor structure is provided. The method comprises steps of: providing a substrate; forming a first single crystal semiconductor layer on the substrate; etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate; etching the substrate through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate, thus forming a patterned structure on the porous structure; and depositing a single crystal semiconductor material to form a second single crystal semiconductor layer on the patterned structure.
In one embodiment, depositing a single crystal semiconductor material to form a second single crystal semiconductor layer on the patterned structure comprises: epitaxially laterally growing a single crystal semiconductor material on a lateral surface of the first single crystal semiconductor layer exposed in the plurality of holes or trenches.
In one embodiment, after epitaxially laterally growing a single crystal semiconductor material on a lateral surface of the first single crystal semiconductor layer exposed in the plurality of holes or trenches, the method further comprises: epitaxially longitudinally growing and then epitaxially laterally over-growing the single crystal semiconductor material on a top surface of the first single crystal semiconductor layer to form the second single crystal semiconductor layer. By such an epitaxial lateral overgrowth (ELOG) process, a dislocation density is significantly reduced.
In one embodiment, the substrate has a patterned surface.
In one embodiment, before forming a first single crystal semiconductor layer on the substrate, the method further comprises: forming a buffer layer on the substrate.
In one embodiment, the buffer layer has a single-layer structure, a multi-layer superlattice structure or a multi-layer interlaced structure.
In one embodiment, etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate comprises: forming a mask layer on the first single crystal semiconductor layer; etching the mask layer to form a plurality of openings; and etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate.
In one embodiment, a material of the substrate comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga203, A1203, A1N, ZnO, LiGa02 and LiA102.
In one embodiment, etching the substrate through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate comprises: etching the substrate by an electrochemical etch when the substrate is conductive; and etching the substrate by a wet etch when the substrate is nonconductive.
In one embodiment, the method further comprises: implanting different types and/or different concentrations of doping elements into the substrate to form a plurality of etch resistant structures below a top surface of the substrate, which enables a lateral etching during a process of forming the porous structure.
In one embodiment, a material of the first single crystal semiconductor layer comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga203, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof.
In one embodiment, the method further comprises: if a material of the substrate is Si, after etching the substrate through the plurality of holes or trenches to form a porous structure, processing the substrate in a nitrogenous and/or oxygenous ambience to enable the porous structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation layer. In this embodiment, a material of the isolation layer is Si02, SiON or SiN. In one aspect, single crystal Si becomes amorphous oxide or nitride, which is more advantageous for releasing a thermal mismatch stress; in another aspect, the isolation layer may be helpful to separate the Si substrate from the first single crystal semiconductor layer during a late fabrication process of a device (such as an LED) so that the Si substrate can be recycled.
In one embodiment, the first single crystal semiconductor layer and/or the second single crystal semiconductor layer have a multi-layer compound semiconductor structure.
In one embodiment, the method further comprises: dividing the substrate into a plurality of blocks by deep trench etching to prevent a stress accumulation in a large scale. With the method according to embodiments of the present disclosure, the substrate may use a low cost rough material (such as a Si wafer), a high quality heterogeneous thin film may be obtained, and a process is simple and realizable. Moreover, a stress resulted from thermal mismatch may be effectively released by the porous structure, which is advantageous for further fabricating a large size of single crystal semiconductor layer thereon, such as the second single crystal semiconductor layer with a very large thickness (above dozens of microns) and a large diameter (a basic size may be up to 8-12 inches even 18 inches). What is more important, the porous structure is formed subsequent to forming the first single crystal semiconductor layer, and thus many unfavorable factors resulted from a direct epitaxy of heterogeneous materials on the porous structure are avoided. Therefore, a perfect interface between the porous structure and the first single crystal semiconductor layer can be ensured. Meanwhile, a growth quality of the first single crystal semiconductor layer and the second single crystal semiconductor layer can be ensured.
According to another aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure comprises: a substrate; a porous structure formed on a top surface of the substrate; a first single crystal semiconductor layer formed on the porous structure, a plurality of holes or trenches buried in the first single crystal semiconductor layer and extending to the porous structure; and a second single crystal semiconductor layer formed on the first single crystal semiconductor layer, covering and extending to the plurality of holes or trenches.
In one embodiment, the substrate has a patterned surface.
In one embodiment, the semiconductor structure further comprises a buffer layer formed on the substrate.
In one embodiment, the buffer layer has a single-layer structure, a multi-layer superlattice structure or a multi-layer interlaced structure.
In one embodiment, the semiconductor structure further comprises a mask layer formed on the first single crystal semiconductor layer, wherein the mask layer is divided into a plurality of discrete masks by the plurality of holes or trenches.
In one embodiment, a material of the substrate comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga203, A1203, A1N, ZnO, LiGa02, and LiA102.
In one embodiment, the porous structure is formed by an electrochemical etch when the substrate is conductive; and the porous structure is formed by a wet etch when the substrate is nonconductive.
In one embodiment, the semiconductor structure further comprises a plurality of etch resistant structures formed below the top surface of the substrate by implanting different types and/or different concentrations of doping elements in the substrate.
In one embodiment, a material of the first single crystal semiconductor layer comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga203, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof.
In one embodiment, the semiconductor structure further comprises an isolation layer formed by a reaction of the porous structure with a nitrogenous and/or oxygenous ambience, if a material of the substrate is Si.
In one embodiment, the first single crystal semiconductor layer and/or the second single crystal semiconductor layer have a multi-layer compound semiconductor structure.
In one embodiment, the substrate further comprises a plurality of deep trenches, by which the substrate is divided into a plurality of blocks to prevent a stress accumulation in a large scale.
The semiconductor structure according to embodiments of the present disclosure has advantages of low dislocation density, high quality thin film and low material cost. Moreover, a stress resulted from thermal mismatch may be effectively released by the porous structure.
Additional aspects and advantages of the embodiments of the present disclosure will be given in part in the following descriptions, become apparent in part from the following descriptions, or be learned from the practice of the embodiments of the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other aspects and advantages of the disclosure will become apparent and more readily appreciated from the following descriptions taken in conjunction with the drawings in which:
Figs. 1-10 are schematic cross- sectional views of intermediate statuses of a semiconductor structure formed in steps of a method for fabricating a semiconductor structure according to a first embodiment of the present disclosure;
Figs. 11-20 are schematic cross-sectional views of intermediate statuses of a semiconductor structure formed in steps of a method for fabricating a semiconductor structure according to a second embodiment of the present disclosure;
Fig. 21 is a schematic cross-sectional view of the semiconductor structure according to the first embodiment of the present disclosure;
Fig. 22a is a schematic cross-sectional view of the semiconductor structure according to another embodiment of the present disclosure;
Fig. 22b is a schematic top view of the semiconductor structure according to the another embodiment of the present disclosure; and
Fig. 23 is a schematic cross-sectional view of the semiconductor structure according to the second embodiment of the present disclosure.
DETAILED DESCRIPTION
Embodiments of the present disclosure will be described in detail in the following descriptions, examples of which are shown in the accompanying drawings, in which the same or similar elements and elements having same or similar functions are denoted by like reference numerals throughout the descriptions. The embodiments described herein with reference to the accompanying drawings are explanatory and illustrative, which are used to generally understand the present disclosure. The embodiments shall not be construed to limit the present disclosure.
It is to be understood that phraseology and terminology used herein with reference to device or element orientation (such as, terms like "longitudinal", "lateral", "front", "rear", "right", "left", "lower", "upper", "horizontal", "vertical", "above", "below", "up", "top", "bottom" as well as derivative thereof such as "horizontally", "downwardly", "upwardly", etc.) are only used to simplify description of the present invention, and do not alone indicate or imply that the device or element referred to must have or operated in a particular orientation.
In addition, terms such as "first" and "second" are used herein for purposes of description and are not intended to indicate or imply relative importance or significance or imply a number of technical features indicated. Therefore, a "first" or "second" feature may explicitly or implicitly comprise one or more features. Further, in the description, unless indicated otherwise, "a plurality of refers to two or more.
Terms concerning attachments, coupling and the like, such as "connected" and "interconnected", refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
A semiconductor structure is provided according to the present disclosure. Figs. 1-10 are schematic cross-sectional views of intermediate statuses of the semiconductor structure formed in steps of the method for forming the semiconductor structure according to a first embodiment.
As shown in Figs. 1-10, the method for forming the semiconductor structure comprises following steps.
In step S101, as shown in Fig. 1, a substrate 100 is provided.
The substrate 100 may have a patterned surface. For example, the substrate 100 may be a patterned Si substrate or a patterned sapphire substrate. Such patterned substrate may be favorable for a reduction of a dislocation density of an epitaxial layer formed thereon, as well as for an emission of LED light.
A material of the substrate 100 may comprise any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga203, A1203, A1N, ZnO, LiGa02 and LiA102. Preferably, the substrate 100 is a Si substrate, which is not only low-cost and easy to be doped, but also easy to react to form a hetero isolation layer.
Alternatively, after the step S101, different types and/or different concentrations of doping elements are implanted in the substrate 100 to form a plurality of etch resistant structures 1001 below a top surface of the substrate 100. More preferably, different types and/or different concentrations of doping elements are implanted in the substrate 100 to form a large area of etch region 1002. The plurality of etch resistant structures 1001 and the etch region 1002 enables a following etch to be lateral-oriented. Specifically, as shown in Fig. 2, taking a p-type lightly doped Si substrate as an example, the substrate 100 is n-type locally doped by an ion implantation to form the plurality of n-type etch resistant structures 1001 at a certain depth below the top surface of the substrate 100, and then the substrate 100 is p-type heavily doped at a smaller depth below the top surface of the substrate 100 to form the large area of etch region 1002, while a bottom region of the substrate 1000 remaining unchanged. It should be noted that, this embodiment is explanatory and illustrative, but not construed to limit the present disclosure. Other doping processes may also be adopted in practice, provided that when etching different regions, respective etching rate satisfies "Vioo2>Viooo
Figure imgf000008_0001
In step SI 02, as shown in Fig. 3, a first single crystal semiconductor layer 200 is formed on the substrate 100.
A material of the first single crystal semiconductor layer 200 comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga203, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof, such as a combination of a AIN/GaN layer and a GaAs/AlGaAs layer.
The first single crystal semiconductor layer 200 may have a multi-layer compound structure. In this embodiment, the multi-layer compound structure may be a superlattice structure, a compound structure with gradient distribution (gradually increasing) of composition (such as a SiGe layer with gradient distribution of Ge), or a compound structure with different compositions distributed alternatively (such as GaN and A1N distributed alternatively).
In step SI 03, as shown in Fig. 4, the first single crystal semiconductor layer 200 is etched to form a plurality of openings. The plurality of openings are in alignment with the plurality of etch resistant structures 1001 in a vertical direction respectively. By this means, the first single crystal semiconductor layer 200 becomes a plurality of first single crystal semiconductor structures (still denoted as 200).
In step S104, as shown in Fig. 5, the substrate 100 is etched from the plurality of openings to form a plurality of holes or trenches extending into the substrate 100. Preferably, a depth of each hole or trench is greater than a width of each hole or trench. Alternatively, this step may be skipped. In this case, the plurality of openings formed in step SI 03 are equal to the plurality of holes or trenches formed in step SI 04, that is, the plurality of holes or trenches extends to the top surface of the substrate 100.
In step S105, as shown in Fig. 6, the substrate 100 is etched through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate 100, thus forming a patterned structure on the porous structure.
When the substrate 100 is conductive, the substrate 100 may be etched by an electrochemical etch; and when the substrate 100 is nonconductive, the substrate 100 may be etched by a wet etch. For example, for the Si substrate, the porous structure is formed by the electrochemical etch with HF as an etching reagent. Since the smaller a resistivity is, the deeper the etch is, by controlling the resistivity of the Si substrate 100 and the first single crystal semiconductor layer 200, the porous structure can be formed on the surface of the substrate 100 while the first single crystal semiconductor layer 200 is hardly etched. In order to prevent an over-deep electrochemical etch, an etch resistant layer may be formed at a bottom of the etch region 1002 by implanting different types and/or different concentrations of doping elements in different regions below the top surface of the substrate 100. The etch resistant layer has a conductive type different from the etch region 1002 and/or a resistivity higher than that of the etch region 1002, thus inducting a lateral expansion of the electrochemical etch to form the porous structure in the whole etch region 1002. For the nonconductive substrate, the porous structure is formed by the wet etch. Prior to the wet etch, the substrate may be processed by an ion implantation so that a crystal structure of a local surface region of the substrate is damaged or denatured, which is favorable for the formation of the porous structure using the wet etch.
In step S106, as shown in Fig. 7, if the material of the substrate is Si, after etching the substrate through the plurality of holes or trenches to form the porous structure, under a high temperature condition or in a plasma ambiance with a relative high temperature, the substrate is processed in a nitrogenous and/or oxygenous ambience (such as any one of 02, H20, NH3, N2, 03, oxygen plasma, nitrogen plasma and a combination thereof) to enable the porous structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation layer (arrows shown in Fig. 7 represent inputting a reaction gas). In this embodiment, exposed parts of the porous structure (Si or SiGe) react with the nitrogenous and/or the oxygenous ambience to form the isolation layer (Si02, SiON or SiN). Preferably, NH3 is input to react with porous Si or SiGe to form amorphous SiN, while the first single crystal semiconductor layer (such as GaN or A1N) remaining unchanged. The porous structure thus becomes the hetero isolation layer.
It should be noted that, the step SI 06 is an optional step, which can be skipped when the material of the substrate 100 is not Si or SiGe. The isolation layer formed in this step is different from the substrate in material. Moreover, the amorphous isolation layer (such as amorphous SiN), in one aspect, is more favorable for a release of the thermal mismatch stress, in another aspect, may be served as a lift-off layer to separate the substrate from the first single crystal semiconductor layer, thus conveniently realizing a transfer of an epitaxial film and a recycling of the substrate. In step S107, as shown in Figs. 8-10, a single crystal semiconductor material is deposited to form a second single crystal semiconductor layer 300 on the patterned structure. The single crystal semiconductor material may be firstly epitaxially laterally grown on a lateral surface of the first single crystal semiconductor layer 200 exposed in the plurality of holes or trenches. After a while, the plurality of holes or trenches are filled with the single crystal semiconductor material, and the single crystal semiconductor material may be epitaxially longitudinally grown and then continuously epitaxially laterally over-grown until the second single crystal semiconductor layer 300 is formed on the patterned structure. In Figs. 8-10, bold-faced arrows represent a flow of a gas source of the single crystal semiconductor material, while light-faced arrows represent a growth direction of the single crystal semiconductor material.
A material of the second single crystal semiconductor layer 300 may also comprise any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga203, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof. Alternatively, the second single crystal semiconductor layer 300 may have a multi-layer compound structure.
For the semiconductor of diamond structure (such as Ge, SiGe or SiC) or semiconductor of sphalerite structure (such as GaAs, GaP), as shown in Fig. 10, the single crystal semiconductor material may be directly deposited on the patterned structure. By this means, the plurality of openings are covered by a thick epitaxial layer, thus forming the whole second single crystal semiconductor layer 300.
For the semiconductor of wurtzite structure (such as GaN, InGaN or A1N), as shown in Figs. 8-10, the second single crystal semiconductor layer 300 may be formed based on a characteristic that a lateral growth rate is greater than a longitudinal growth rate in a special process. Specifically, during the deposition of GaN, InGaN or A1N, the single crystal semiconductor material is firstly laterally epitaxially grown on a lateral surface of the first single crystal semiconductor layer 200 exposed in the plurality of holes or trenches. After a while, the plurality of holes or trenches are filled with the single crystal semiconductor material, and the single crystal semiconductor material is first longitudinally epitaxially grown and then laterally epitaxially grown, until the whole second single crystal semiconductor layer 300 is formed on the patterned structure, in which an epitaxial lateral overgrowth (ELOG) process is adopted. Because the second single crystal semiconductor layer 300 is mainly formed by lateral growth, the second single crystal semiconductor layer 300 has a very low dislocation density, thus improving a growth quality thereof. Alternatively, the ELOG process may be replaced by a one-step epitaxial growth or other deposition process.
Preferably, except all above steps, the method may further comprise: dividing the substrate into a plurality of blocks by deep trench etching to prevent a stress accumulation in a large scale. This step may be performed prior to any of the above steps. Preferably, this step is performed accompany with step SI 03 and step SI 04. Because deep trenches are wide, the second single crystal semiconductor layer 300 is disconnected at each deep trench to reduce the stress accumulation.
Figs. 11-20 are schematic cross-sectional views of intermediate statuses of the semiconductor structure formed in steps of the method for forming the semiconductor structure according to a second embodiment.
As shown in Figs. 11-20, the method for forming the semiconductor structure comprises following steps.
In step S201, as shown in Fig. 11, a substrate 100 is provided.
Alternatively, after the step S201, different types and/or different concentrations of doping elements are implanted in the substrate to form a plurality of etch resistant structures 1001 below a top surface of the substrate. More preferably, different types and/or different concentrations of doping elements are implanted in the substrate to form a large area of etch region 1002. Forming the plurality of etch resistant structures 1001 and the etch region 1002 enables a following etch to be lateral-oriented. Specifically, as shown in Fig. 12, taking a p-type lightly doped Si substrate as example, the substrate 100 is n-type locally doped by ion implantation to form the plurality of n-type etch resistant structures 1001 at a certain depth below the top surface of the substrate, and then the substrate 100 is p-type heavily doped at a smaller depth below the top surface of the substrate to form the large area of etch region 1002, while a bottom region of the substrate 1000 remaining unchanged. It should be noted that, this embodiment is explanatory and illustrative, but not construed to limit the present disclosure. Other doping processes may be adopted in practice, provided that when etching different regions, respective etching rate satisfies
Figure imgf000012_0001
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In step S202, as shown in Fig. 13, a buffer layer 110, a first nitride semiconductor layer 200 and a mask layer 210 are sequentially formed on the substrate 100.
Specifically, the buffer layer 110 may have a single-layer low temperature structure (such as an A1N layer), a multi-layer superlattice structure (such as an AIN/AlGaN multi-layer) or a multi-layer interlaced structure (such as a multi-layer combination of AlN/GaN). A material of the first nitride semiconductor layer 200 comprises any one of GaN, InGaN, A1N, AlGaN, InN, AlGalnN and a combination thereof (such as a multi-layer combination of AIN/AlGaN or AlN/GaN). In a preferred embodiment, the first nitride semiconductor layer 200 is the A1N layer or the double-layer combination of AlN/GaN. A material of the mask layer 210 comprises any one of Si02, SixNi-x, Hf02, Zr02, A1203 and a photoresist.
It should be noted that, a provision of the buffer layer 110 or the mask layer 210 is optional. Alternatively, step S202 may comprise: sequentially forming a first nitride semiconductor layer 200 and a mask layer 210 on the substrate 100.
In step S203, as shown in Fig. 14, a plurality of openings are formed by etching the mask layer 210. The plurality of openings are in alignment with the plurality of etch resistant structures 1001 in a vertical direction respectively. By this means, the mask layer 210 becomes a plurality of discrete masks.
In step S204, as shown in Fig. 15, the first nitride semiconductor layer 200, the buffer layer 110 and the substrate 100 are etched from the plurality of openings to form a plurality of holes or trenches extending into the substrate 100 (that is, extending into the etch region 1002). Preferably, a depth of each hole or trench is greater than a width of each hole or trench. Alternatively, the first nitride semiconductor layer 200 and the buffer layer 110 are etched from the plurality of openings to form a plurality of holes or trenches extending to the top surface of the substrate 100.
In step S205, as shown in Fig. 16, the substrate 100 is etched through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate 100, thus forming a patterned structure, that is, the etch region 1002 becomes the porous structure. Specifically, the substrate 100 may be etched by any one of electrochemical etch, wet etch, dry etch and a combination thereof.
In step S206, as shown in Fig. 17, if the material of the substrate is Si, after step S205, under a high temperature condition or in a plasma ambiance with a relative high temperature, the substrate is processed in a nitrogenous and/or oxygenous ambience (such as any one of 02, H20, NH3, N2, O3, oxygen plasma, nitrogen plasma and a combination thereof) to enable the porous structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation layer (arrows shown in Fig. 17 represent inputting a reaction gas). In this embodiment, exposed parts of the porous structure (Si or SiGe) react with the nitrogenous and/or the oxygenous ambience to form the isolation layer (Si02 or SiN). Preferably, NH3 is input to react with porous Si or SiGe to form amorphous SiN, while the first nitride semiconductor layer (such as GaN or A1N) remaining unchanged. The porous structure thus becomes the hetero isolation layer.
It should be noted that, the step S206 is an optional step, which can be skipped when the material of the substrate 100 is not Si or SiGe. The isolation layer formed in this step is different from the substrate in material. Moreover, the amorphous isolation layer (such as amorphous SiN), in one aspect, is more favorable for a release of the thermal mismatch stress, in another aspect, may be served as a lift-off layer to separate the substrate from the first single crystal semiconductor layer, thus conveniently realizing a transfer of an epitaxial film and a recycling of the substrate.
In step S207, as shown in Figs. 18-20, a nitride semiconductor material is deposited to form a second nitride semiconductor layer 300 on the patterned structure. The nitride semiconductor material is firstly epitaxially laterally grown on a lateral surface of the first nitride semiconductor layer 200 exposed in the plurality of holes or trenches. After a while, the plurality of holes or trenches are filled with the nitride semiconductor material, and the nitride semiconductor material may be epitaxially longitudinally grown and then continuously epitaxially laterally over-grown until the second nitride semiconductor layer 300 is formed on the patterned structure. Because the second nitride semiconductor layer 300 is formed by a lateral growth, the second nitride semiconductor layer 300 has a very low dislocation density, thus improving a growth quality thereof.
A material of the second nitride semiconductor layer 300 may also comprise any one of GaN, InGaN, A1N, AlGaN, InN, AlGalnN and a combination thereof (such as a multi-layer combination of AlGaN/InGaN, AlGaN/GaN, AlGaN/GaN/InGaN or InGaN/GaN). Preferably, the second nitride semiconductor layer 300 is a GaN layer. It should be noted that, when the mask layer 210 is a photo resist layer, it needs to be removed after step S205. In step S207, alternatively, the second nitride semiconductor layer 300 may be directly formed on the first nitride semiconductor layer 300 by the ELOG process.
In this embodiment, the lateral epitaxial growth of the second nitride semiconductor layer 300 may be realized by controlling a growth condition. In Figs. 18-20, bold-faced arrows represent a flow of a gas source of the nitride semiconductor material, while light-faced arrows represent a growth direction of the nitride semiconductor material. Taking GeN as example, a growth mode of GaN mainly depends on a growth temperature and a pressure in a growth chamber. The higher the growth temperature is and the lower the pressure is, the more dominant the lateral growth is. Contrariwise, the longitudinal growth is more dominant. A preferred growth condition of GaN may be as follows: the growth temperature is 1100°C, the pressure in the growth chamber is lOOTorr, trimethylgallium is as a gallium source, and NH3 is as a nitrogen source. If GaN needs to be doped, a certain amount of SiH4 may be used as an n-type doping source, and a certain amount of Cp2Mg may be used as a p-type doping source. As shown in Fig. 18, since the lateral growth rate of GaN in the holes or trenches is greater than the longitudinal growth rate of GaN in the holes or trenches, and the depth of the holes or trenches is greater than a width of the openings, upper parts of the holes or trenches are filled with GaN by the lateral growth, while lower parts of the holes or trenches remaining unfilled or semi-filled. As shown in Fig. 19, after depositing for a while, both upper parts of the holes or trenches are filled and the openings are sealed with GaN, and then GaN is further epitaxially grown to form a lug boss on each opening. As shown in Fig. 20, GaN is continuously grown on the plurality of discrete masks by the ELOG process to form the whole second nitride semiconductor layer 300. In this embodiment, the lateral growth is favorable for a reduction of a dislocation density of GaN, thus improving a thickness and a growth quality of the film.
The method according to embodiments of the present disclosure has following advantages.
(1) For the semiconductor of wurtzite structure, the second single crystal semiconductor layer may be formed on the first single crystal semiconductor layer by the lateral growth. The dislocation density of the epitaxial film can be reduced, and the film quality is improved. More importantly, since the first single crystal semiconductor layer is not a porous structure but a single crystal, an epitaxial growth quality of the second single crystal semiconductor layer is further improved.
(2) The plurality of holes or trenches and the porous structure are advantageous for releasing the thermal mismatch stress resulted from the film growth process, thus preventing the film from cracking when the epitaxial thickness of the film is larger, and improving the epitaxial thickness and growth quality of the film. It means that it is possible to use the low cost but high thermal mismatch material (such as Si) as the substrate, and it is also favorable for an LED vertical structure. More importantly, since the plurality of holes or trenches and the porous structure are formed after a formation of the first single crystal semiconductor layer, the growth quality of the first single crystal semiconductor layer is not affected by a surface problem of the plurality of holes or trenches and the porous structure. Thus, the high quality first single crystal semiconductor layer may be obtained. Accordingly, the high quality second single crystal semiconductor layer may also be obtained.
(3) The surface of the substrate is etched into the porous structure, so that the semiconductor structure obtained is easy to be separated from the substrate. Particularly for the Si or SiGe substrate, the porous structure reacts to form the hetero isolation layer to further release stress. Moreover, the isolation layer is favorable for the separation of the substrate.
(4) The substrate is divided into a plurality of blocks by deep trench etching, which in one aspect, prevents the stress accumulation in the large scale, and in another aspect, is favorable for division of device.
(5) The low cost material (such as Si) is used as the substrate material. The process is simple and the fabrication cost is low.
Fig. 21 is a schematic cross-sectional view of the semiconductor structure according to the first embodiment of the present disclosure.
As shown in Fig. 21, the semiconductor structure comprises: a substrate 100, a first single crystal semiconductor layer 200, a porous structure, a second single crystal semiconductor layer 300 and a plurality of holes or trenches. The porous structure is formed on a top surface of the substrate 100 for reducing a thermal stress resulted from a growth process of semiconductor materials. The first single crystal semiconductor layer 200 is formed on the porous structure. The plurality of holes or trenches are buried in the first single crystal semiconductor layer 200 and extend to the porous structure. The second single crystal semiconductor layer 300 is formed on the first single crystal semiconductor layer 200, covering and extending to the plurality of holes or trenches.
The substrate 100 may have a patterned surface. For example, the substrate 100 may be a patterned Si substrate or a patterned sapphire substrate. Such patterned substrate may be favorable for a reduction of a dislocation density of an epitaxial layer formed thereon, as well as for an emission of LED light.
A material of the substrate 100 may comprise any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga203, A1203, A1N, ZnO, LiGa02 and LiA102.
The porous structure is formed by an electrochemical etch when the substrate 100 is conductive; and the porous structure is formed by a wet etch when the substrate 100 is nonconductive.
Materials of the first single crystal semiconductor layer 200 and the second single crystal semiconductor layer 300 may comprise any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga203, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof, such as a combination of a AIN/GaN layer and a GaAs/AlGaAs layer.
Optionally, a plurality of etch resistant structures (not shown in Fig. 21) are formed below the top surface of the substrate 100 by implanting different types and/or different concentrations of doping elements in the substrate 100 for introducing a lateral expansion rather than a longitudinal expansion of the electrochemical etch so as to form the porous structure on the whole surface of the substrate. Preferably, if a material of the substrate is Si or SiGe, under a high temperature condition or in a plasma ambiance with a relative high temperature, an isolation layer is formed by a reaction of the porous structure with a nitrogenous and/or oxygenous ambience (such as any one of 02, H20, NH3, N2, 03, oxygen plasma, nitrogen plasma and a combination thereof). The isolation layer is favorable for the separation of the substrate in a following process.
Preferably, the substrate 100 further comprises a plurality of deep trenches, by which the substrate 100 is divided into a plurality of blocks. Figs. 22a and 22b are a schematic cross-sectional view and a top view of the semiconductor structure respectively according to an embodiment of the present disclosure. As shown in Fig. 22a, the substrate 100 is divided into a plurality of blocks. It can be seen from Fig. 22b, besides the second single crystal semiconductor layer 300 which is exposed at a top layer, the substrate 100 is also exposed from the deep trenches. When the substrate 100 is a Si substrate and there is a hetero isolation layer on the top surface of the substrate 100, the hetero isolation layer is exposed from the deep trenches. The semiconductor structure with deep trench isolation prevents the stress accumulation in the large scale, prevents the film from cracking when the epitaxial thickness of the film is larger, and is also favorable for division of device.
Fig. 23 is a schematic cross-sectional view of the semiconductor structure according to the second embodiment of the present disclosure.
As shown in Fig. 23, the semiconductor structure comprises: a substrate 100, a buffer layer 110, a first nitride semiconductor layer 200, a mask layer 210, a porous structure, a second nitride semiconductor layer 300 and a plurality of holes or trenches. The porous structure or the porous structure with a hetero isolation layer is formed on a top surface of the substrate 100. The buffer layer 110 is formed on the substrate 100, and an interface between the substrate 100 and the buffer layer 110 is a plane or a patterned structure. The first nitride semiconductor layer 200 is formed on the buffer layer 110. The mask layer 210 is formed on the first nitride semiconductor layer 200 and has a plurality of openings, in which the mask layer 210 is divided into a plurality of discrete masks by the plurality of openings. The plurality of holes or trenches are buried in the first nitride semiconductor layer 200 and extend to the porous structure. The second nitride semiconductor layer 300 is formed on the mask layer 210, covering and extending to the plurality of holes or trenches.
The substrate 100 may have a patterned surface. For example, the substrate 100 may be a patterned Si substrate or a patterned sapphire substrate. Such patterned substrate may be favorable for a reduction of a dislocation density of an epitaxial layer formed thereon, as well as for an emission of LED light.
A material of the substrate 100 may comprise any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga203, A1203, A1N, ZnO, LiGa02 and LiA102.
Specifically, the buffer layer 110 may have a single-layer low temperature structure (such as an A1N layer), a multi-layer superlattice structure (such as an AIN/AlGaN multi-layer) or a multi-layer interlaced structure (such as a multi-layer combination of AIN/GaN). Materials of the first nitride semiconductor layer 200 and the second nitride semiconductor layer 300 may comprise any one of GaN, InGaN, A1N, AlGaN, InN, AlGalnN and a combination thereof (such as a multi-layer combination of AlGaN/InGaN, AlGaN/GaN, AlGaN/GaN/InGaN or InGaN/GaN). A material of the mask layer 210 may comprise any one of Si02, SixN1-x, Hf02, Zr02, amorphous A1203 and a photoresist.
It should be noted that, the buffer layer 110 or the mask layer 210 is optional. Alternatively, the semiconductor structure may comprise: a substrate 100, a first nitride semiconductor layer 200, a mask layer 210, a second nitride semiconductor layer 300 and a plurality of holes or trenches. Yet alternatively, the semiconductor structure may comprise: a substrate 100, a buffer layer 110, a first nitride semiconductor layer 200, a second nitride semiconductor layer 300 and a plurality of holes or trenches.
The semiconductor structure according to embodiments of the present disclosure has following advantages.
(1) For the semiconductor of wurtzite structure, the second single crystal semiconductor layer may be formed on the first single crystal semiconductor layer by the lateral growth. The dislocation density of the epitaxial film can be reduced, and the film quality is improved. More importantly, since the first single crystal semiconductor layer is not a porous structure but a single crystal, the epitaxial growth quality of the second single crystal semiconductor layer is further improved.
(2) The plurality of holes or trenches and the porous structure are advantageous for releasing the thermal mismatch stress resulted from the film growth process, thus preventing the film from cracking when the epitaxial thickness of the film is larger, and improving the epitaxial thickness and growth quality of the film. It means that it is possible to use the low cost but high thermal mismatch material (such as Si) as the substrate, and it is also favorable for an LED vertical structure. More importantly, since the plurality of holes or trenches and the porous structure are formed after a formation of the first single crystal semiconductor layer, the growth quality of the first single crystal semiconductor layer is not affected by a surface problem of the plurality of holes or trenches and the porous structure. Thus, the high quality first single crystal semiconductor layer may be obtained. Accordingly, the high quality second single crystal semiconductor layer may be obtained.
(3) The surface of the substrate is etched into the porous structure, so that the semiconductor structure obtained is easy to be separated from the substrate. Particularly for the Si or SiGe substrate, the porous structure reacts to form the hetero isolation layer to further release stress. Moreover, the isolation layer is favorable for the separation of the substrate.
(4) The substrate is divided into a plurality of blocks by deep trench etching, which in one aspect, prevents the stress accumulation in the large scale, and in another aspect, is favorable for division of device.
(5) The low cost material (such as Si) is used as the substrate material. The process is simple and the fabrication cost is low.
Reference throughout this specification to "an embodiment", "some embodiments", "one embodiment", "an example", "a specific examples", or "some examples" means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. Thus, the appearances of the phrases such as "in some embodiments", "in one embodiment", "in an embodiment", "an example", "a specific examples", or "some examples" in various places throughout this specification are not necessarily referring to the same embodiment or example of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that changes, alternatives, and modifications may be made in the embodiments without departing from spirit and principles of the disclosure. Such changes, alternatives, and modifications all fall into the scope of the claims and their equivalents.

Claims

WHAT IS CLAIMED IS:
1. A method for forming a semiconductor structure, comprising steps of:
providing a substrate;
forming a first single crystal semiconductor layer on the substrate;
etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate;
etching the substrate through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate, thus forming a patterned structure on the porous structure; and
depositing a single crystal semiconductor material to form a second single crystal semiconductor layer on the patterned structure.
2. The method for forming a semiconductor structure according to claim 1, wherein depositing a single crystal semiconductor material to form a second single crystal semiconductor layer on the patterned structure comprises:
epitaxially laterally growing a single crystal semiconductor material on a lateral surface of the first single crystal semiconductor layer exposed in the plurality of holes or trenches.
3. The method for forming a semiconductor structure according to claim 2, after epitaxially laterally growing a single crystal semiconductor material on a lateral surface of the first single crystal semiconductor layer exposed in the plurality of holes or trenches, further comprising:
epitaxially longitudinally growing and then epitaxially laterally over-growing the single crystal semiconductor material on a top surface of the first single crystal semiconductor layer to form the second single crystal semiconductor layer.
4. The method for forming a semiconductor structure according to any one of claims 1-3, wherein the substrate has a patterned surface.
5. The method for forming a semiconductor structure according to any one of claims 1-4, before forming a first single crystal semiconductor layer on the substrate, further comprising: forming a buffer layer on the substrate.
6. The method for forming a semiconductor structure according to claim 5, wherein the buffer layer has a single-layer structure, a multi-layer superlattice structure or a multi-layer interlaced structure.
7. The method for forming a semiconductor structure according to any one of claims 1-6, wherein etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate comprises: forming a mask layer on the first single crystal semiconductor layer;
etching the mask layer to form a plurality of openings; and
etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate.
8. The method for forming a semiconductor structure according to any one of claims 1-7, wherein a material of the substrate comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga203, A1203, A1N, ZnO, LiGa02 and LiA102.
9. The method for forming a semiconductor structure according to any one of claims 1-8, wherein etching the substrate through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate comprises:
etching the substrate by an electrochemical etch when the substrate is conductive; and etching the substrate by a wet etch when the substrate is nonconductive.
10. The method for forming a semiconductor structure according to any one of claims 1-9, further comprising:
implanting different types and/or different concentrations of doping elements into the substrate to form a plurality of etch resistant structures below the top surface of the substrate.
11. The method for forming a semiconductor structure according to any one of claims 1-10, wherein a material of the first single crystal semiconductor layer comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II-VI semiconductors ZnO, Ga203, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof.
12. The method for forming a semiconductor structure according to any one of claims 1-11, further comprising:
if a material of the substrate is Si, after etching the substrate through the plurality of holes or trenches to form a porous structure, processing the substrate in a nitrogenous and/or oxygenous ambience to enable the porous structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation layer.
13. The method for forming a semiconductor structure according to any one of claims 1-12, wherein the first single crystal semiconductor layer and/or the second single crystal semiconductor layer have a multi-layer compound semiconductor structure.
14. The method for forming a semiconductor structure according to any one of claims 1-13, further comprising: dividing the substrate into a plurality of blocks by deep trench etching.
15. A semiconductor structure, comprising:
a substrate;
a porous structure formed on a top surface of the substrate;
a first single crystal semiconductor layer formed on the porous structure, a plurality of holes or trenches buried in the first single crystal semiconductor layer and extending to the porous structure; and
a second single crystal semiconductor layer formed on the first single crystal semiconductor layer, covering and extending to the plurality of holes or trenches.
16. The semiconductor structure according to claim 15, wherein the substrate has a patterned surface.
17. The semiconductor structure according to claim 15 or 16, further comprising a buffer layer formed on the substrate.
18. The semiconductor structure according to claim 17, wherein the buffer layer has a single-layer structure, a multi-layer superlattice structure or a multi-layer interlaced structure.
19. The semiconductor structure according to one of claims 15-18, further comprising a mask layer formed on the first single crystal semiconductor layer, wherein the mask layer is divided into a plurality of discrete masks by the plurality of holes or trenches.
20. The semiconductor structure according to one of claims 15-19, wherein a material of the substrate comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga203, A1203, A1N, ZnO, LiGa02, and LiA102.
21. The semiconductor structure according to one of claims 15-20, wherein
the porous structure is formed by an electrochemical etch when the substrate is conductive; and
the porous structure is formed by a wet etch when the substrate is nonconductive.
22. The semiconductor structure according to one of claims 15-21, further comprising a plurality of etch resistant structures formed below the top surface of the substrate by implanting different types and/or different concentrations of doping elements in the substrate.
23. The semiconductor structure according to one of claims 15-22, wherein a material of the first single crystal semiconductor layer comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, AIN, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga203, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof.
24. The semiconductor structure according to one of claims 15-23, further comprising an isolation layer formed by a reaction of the porous structure with a nitrogenous and/or oxygenous ambience, if a material of the substrate is Si.
25. The semiconductor structure according to one of claims 15-24, wherein the first single crystal semiconductor layer and/or the second single crystal semiconductor layer have a multi-layer compound semiconductor structure.
26. The semiconductor structure according to one of claims 15-25, wherein the substrate further comprises a plurality of deep trenches, by which the substrate is divided into a plurality of blocks.
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