WO2014008160A3 - Sonos ono stack scaling - Google Patents

Sonos ono stack scaling Download PDF

Info

Publication number
WO2014008160A3
WO2014008160A3 PCT/US2013/048874 US2013048874W WO2014008160A3 WO 2014008160 A3 WO2014008160 A3 WO 2014008160A3 US 2013048874 W US2013048874 W US 2013048874W WO 2014008160 A3 WO2014008160 A3 WO 2014008160A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
scaling
oxygen
oxide film
Prior art date
Application number
PCT/US2013/048874
Other languages
French (fr)
Other versions
WO2014008160A2 (en
Inventor
Fredrick Jenne
Sagy Levy
Krishnaswamy Ramkumar
Original Assignee
Cypress Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/539,461 external-priority patent/US9299568B2/en
Application filed by Cypress Semiconductor Corporation filed Critical Cypress Semiconductor Corporation
Priority to CN201380032545.4A priority Critical patent/CN104769721A/en
Priority to KR1020147035194A priority patent/KR102159845B1/en
Publication of WO2014008160A2 publication Critical patent/WO2014008160A2/en
Publication of WO2014008160A3 publication Critical patent/WO2014008160A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane

Abstract

A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygenlean second layer.
PCT/US2013/048874 2012-07-01 2013-07-01 Sonos ono stack scaling WO2014008160A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201380032545.4A CN104769721A (en) 2012-07-01 2013-07-01 SONOS ONO stack scaling
KR1020147035194A KR102159845B1 (en) 2012-07-01 2013-07-01 Sonos ono stack scaling

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/539,461 US9299568B2 (en) 2007-05-25 2012-07-01 SONOS ONO stack scaling
US13/539,461 2012-07-01

Publications (2)

Publication Number Publication Date
WO2014008160A2 WO2014008160A2 (en) 2014-01-09
WO2014008160A3 true WO2014008160A3 (en) 2014-02-27

Family

ID=49882582

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2013/048874 WO2014008160A2 (en) 2012-07-01 2013-07-01 Sonos ono stack scaling

Country Status (4)

Country Link
KR (1) KR102159845B1 (en)
CN (1) CN104769721A (en)
TW (1) TWI604595B (en)
WO (1) WO2014008160A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6420614B2 (en) * 2014-09-30 2018-11-07 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
WO2017068859A1 (en) * 2015-10-20 2017-04-27 国立研究開発法人産業技術総合研究所 Non-volatile memory element
US10468295B2 (en) * 2016-12-05 2019-11-05 GlobalWafers Co. Ltd. High resistivity silicon-on-insulator structure and method of manufacture thereof
JP2018157035A (en) * 2017-03-16 2018-10-04 東芝メモリ株式会社 Semiconductor device and manufacturing method of the same
CN109003879B (en) * 2017-06-06 2021-03-19 中芯国际集成电路制造(上海)有限公司 Forming method of gate dielectric layer
CN110838496B (en) * 2018-08-17 2023-04-07 旺宏电子股份有限公司 Memory element and manufacturing method thereof
CN109346528B (en) * 2018-09-27 2022-03-29 上海华力微电子有限公司 Flash memory structure and corresponding programming, erasing and reading method
KR102653530B1 (en) * 2018-12-27 2024-04-02 에스케이하이닉스 주식회사 non-volatile memory device and method of fabricating the same
US20210040607A1 (en) * 2019-08-07 2021-02-11 Applied Materials, Inc. Modified stacks for 3d nand
TWI812974B (en) * 2020-09-04 2023-08-21 日商鎧俠股份有限公司 semiconductor memory device
JP2022043897A (en) 2020-09-04 2022-03-16 キオクシア株式会社 Semiconductor storage device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667217A (en) * 1985-04-19 1987-05-19 Ncr Corporation Two bit vertically/horizontally integrated memory cell
US6469343B1 (en) * 1998-04-02 2002-10-22 Nippon Steel Corporation Multi-level type nonvolatile semiconductor memory device
US20080290400A1 (en) * 2007-05-25 2008-11-27 Cypress Semiconductor Corporation SONOS ONO stack scaling
US20080290399A1 (en) * 2007-05-25 2008-11-27 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
US20110018053A1 (en) * 2007-12-07 2011-01-27 Agency For Science, Technology And Research Memory cell and methods of manufacturing thereof
US20110163371A1 (en) * 2005-09-15 2011-07-07 Song Ki-Whan Methods of fabricating nonvolatile semiconductor memory devices
US20120068159A1 (en) * 2010-09-16 2012-03-22 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US8163660B2 (en) * 2008-05-15 2012-04-24 Cypress Semiconductor Corporation SONOS type stacks for nonvolatile change trap memory devices and methods to form the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100501457B1 (en) * 2003-02-04 2005-07-18 동부아남반도체 주식회사 Semiconductor device hving a sononos structure for quantum trap device
KR100885910B1 (en) * 2003-04-30 2009-02-26 삼성전자주식회사 Nonvolatile semiconductor memory device having gate stack comprising OHAOxide-Hafnium oxide-Aluminium oxide film and method for manufacturing the same
JP6422430B2 (en) * 2012-03-27 2018-11-14 サイプレス セミコンダクター コーポレーション Non-planar memory device and method for manufacturing semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667217A (en) * 1985-04-19 1987-05-19 Ncr Corporation Two bit vertically/horizontally integrated memory cell
US6469343B1 (en) * 1998-04-02 2002-10-22 Nippon Steel Corporation Multi-level type nonvolatile semiconductor memory device
US20110163371A1 (en) * 2005-09-15 2011-07-07 Song Ki-Whan Methods of fabricating nonvolatile semiconductor memory devices
US20080290400A1 (en) * 2007-05-25 2008-11-27 Cypress Semiconductor Corporation SONOS ONO stack scaling
US20080290399A1 (en) * 2007-05-25 2008-11-27 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
US20110018053A1 (en) * 2007-12-07 2011-01-27 Agency For Science, Technology And Research Memory cell and methods of manufacturing thereof
US8163660B2 (en) * 2008-05-15 2012-04-24 Cypress Semiconductor Corporation SONOS type stacks for nonvolatile change trap memory devices and methods to form the same
US20120068159A1 (en) * 2010-09-16 2012-03-22 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device

Also Published As

Publication number Publication date
CN104769721A (en) 2015-07-08
KR102159845B1 (en) 2020-09-25
TWI604595B (en) 2017-11-01
KR20150040805A (en) 2015-04-15
TW201405717A (en) 2014-02-01
WO2014008160A2 (en) 2014-01-09

Similar Documents

Publication Publication Date Title
WO2014008160A3 (en) Sonos ono stack scaling
JP6422430B2 (en) Non-planar memory device and method for manufacturing semiconductor device
JP2012199528A5 (en)
JP2014003280A5 (en) Semiconductor device
JP2014509454A5 (en)
EP3537483A3 (en) Oxide-nitride-oxide stack having multiple oxynitride layers
JP2013168639A5 (en)
JP2011009719A5 (en)
JP2015111706A5 (en) Display device and electronic device
JP2015109433A5 (en)
JP2012216795A5 (en) Semiconductor device
JP2011151377A5 (en)
JP2010251735A5 (en) Semiconductor device
JP2011171726A5 (en) Semiconductor device
JP2010056546A5 (en) Semiconductor device
JP2012227521A5 (en)
JP2012015502A5 (en)
JP2012256875A5 (en) Semiconductor device
JP2012015491A5 (en) Semiconductor device
EP3166147A3 (en) Method of ono integration into logic cmos flow
JP2012080092A5 (en)
JP2015181158A5 (en) Semiconductor device
EP3026706A3 (en) A semiconductor device and a manufacturing method thereof
US9502513B2 (en) Non-volatile memory device and manufacture of the same
JP2014504015A5 (en)

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13812794

Country of ref document: EP

Kind code of ref document: A2

ENP Entry into the national phase

Ref document number: 20147035194

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13812794

Country of ref document: EP

Kind code of ref document: A2