WO2014053543A1

WO2014053543A1 - Mixed-signal psss receiver

Info

Publication number: WO2014053543A1
Application number: PCT/EP2013/070544
Authority: WO
Inventors: Johann-Christoph SCHEYTT; Andreas Wolf
Original assignee: Scheytt Johann-Christoph
Priority date: 2012-10-03
Filing date: 2013-10-02
Publication date: 2014-04-10
Also published as: DE102012019342A1

Abstract

The present invention relates to devices for detecting PSSS signals with mixed analogue/digital circuitry technology, and to methods for detecting PSSS signals, in order to enable an energy-efficient and hardware-efficient operation of the receiver.

Description

Mixed-signal PSSS receiver Field of the invention:

The present invention relates to devices for the detection of PSSS signals with mixed analog-digital circuit technology, as well as method detection of PSSS signals to enable energy and hardware-efficient operation of the receiver.

Description:

The Direct Sequence Spread Spectrum (DSSS) transmission method is one

Spread-band technique, is spread and sent at a transmission signal with a code sequences. In the receiver, the signal is kreukorreliert with the same code sequence and then the received symbols are detected. In US 5029181, a surround analog-digital DSSS receiver is described. Similarly, US6330274 Bl discloses an analogue correlator for spread spectrum receivers. The disadvantage of both devices is that DSSS has a low spectral efficiency. Another disadvantage is that the transmission signal is distorted by the radio channel and no channel equalization takes place in said receiver.

The Parallel Spread Spectrum Sequencing (PSSS) technique is a well-known one

telecommunications method, see e.g. DE 103 01 250.8 or optional

Transmission method in IEEE 802.15.4-2006. PSSS is a spread spectrum technique in which N orthogonal spreading codes are loaded with transmit data and added to the transmitter. The N orthogonal spreading sequences are typically formed from the cyclic shifting of a fundamental code. Frequently, the N codes obtained in this way are extended by cyclical additions. The process of forming the N spreading sequences from N code sequences with cyclic additions, loading of the transmission data on the N spreading sequences and subsequent Summation to a signal is referred to as PSSS coding. PSSS can achieve a higher spectral efficiency than DSSS.

The principle of PSSS coding is exemplified in FIG. 1 (N = 31). The transmission data d1 to d31 are respectively linked in parallel with the spreading sequences B1 to B31 and then added to form a signal. The clock frequency of the spreading sequences (chip rate) is significantly higher than the frequency of the uncoded transmission data d1 to d31 (symbol rate). In the receiver, the PSSS signal is decoded by cross-correlating the input signal with the N spreading sequences used in the PSSS coding to then detect the transmitted data word.

In PSSS based receivers of the prior art, PSSS decoding is done in a digital signal processor. For this, the received analog signal must first be converted to a digital signal with an analog-to-digital converter. Then the PSSS decoding takes place. For very broadband signals in the range of z. B. more than one GHz bandwidth, are therefore very fast AD converter and a very powerful digital

Signal processing needed. Disadvantages are the high power loss, as well as the high circuit complexity (transistor number, chip area, etc.). Another disadvantage is that in extremely broadband signals u. U. the AD converter with the

technically not required combination of resolution and bandwidth

is feasible. Another disadvantage is that no channel equalization takes place.

By A. Wolf and JC Scheytt, in a "15 Gbps Communication on USB3.0 Cable and Even More" (9th Interantional Multi-Converence on Systems, Signals, and Devices, March 20-23 Chemnitz, Germany) is a variant of a PSSS receiver described that uses instead of the original spreading sequences modified spreading sequences in which the individual chips are weighted with coefficients so that at the same time the influence of the transmission channel in the cross-correlation

is compensated (channel unfolding or channel equalization). A similar procedure for compensation of the transmission channel is disclosed in EP 1359679. A2. Here, an orthogonal spreading sequence in the receiver is modified to increase the influence of the transmission channel leading to non-orthogonal spreading sequences

compensate. The advantage of using weighted spreading sequences for channel equalization is that decoding and channel deconvolution can be performed simultaneously with the cross-correlation of the input signal with weighted chips. A disadvantage is that in the prior art methods the signal processing takes place in the digital processor and again, e.g. for very broadband signals in the range of z. B. more than one GHz bandwidth, very fast AD converter and a very powerful digital signal processing with the disadvantages already mentioned above is needed.

An object of the invention is to reduce the required hardware expense of PSSS receivers and to reduce their power dissipation. Another task is also to enable energy and hardware-efficient channel equalization.

The previously derived and indicated object is achieved by the features of the independent claims.

In particular, the previously derived and indicated object according to a first teaching of the invention is achieved by a device having a parallel PSSS receiver 200 with a parallel integrating and resetting unit for correlation 230 with an input signal 232, a synchronization input 299 and

Output signals 237, digitizing units 235, wherein each of the output signals 237 is connected to one input of the digitizing units 235 and the

Digitizing units 235 each have a digitized at their outputs

Output a correlation result 268, the parallel integration and reset unit for correlation 230 consisting of integration and reset units for correlation 236, wherein an integrating and resetting unit for correlation 236 consists of one spreading sequence generator 231, one linking element 233 and one each Correlation filter 234 consists, with a linking element 233 at its

Inputs to the output of a spreading sequence generator 231 and the

common input signal 232 is connected, and at its output to the input of a correlation filter 234 is connected, each of which generates an output signal 237 of an integrating and resetting unit for correlation 236, wherein the

Correlation filter 234 are configured to be reset with the common signal 299, wherein the spreading sequence generators 231 are configured so that their clock frequency is equal to the chip rate, the digitizing units 235 having a sampling rate below the chip rate, wherein the repetition frequency of the common reset signal 299 is equal to the sampling rate of the digitizing units 235.

Moreover, according to a second teaching of the invention, the previously derived and indicated object is achieved by a method for decoding PSSS signals, in particular using a device with a parallel PSSS signal.

Receiver 200 with a parallel integrating and resetting unit for correlation 230 with an input signal 232, a synchronization input 299 and

Digitizing units 235 each have a digitized at their outputs

Output a correlation result 268, the parallel integration and reset unit for correlation 230 consisting of integration and reset units for correlation 236, wherein an integration and reset unit for correlation 236 each consist of a spreading sequence generator 231, one coupling element 233 and one each Correlation filter 234 consists, with a linking element 233 at its

Inputs to the output of a spreading sequence generator 231 and the

common input signal 232, and connected at its output to the input of a correlation filter 234, each of which generates an output signal 237 of an integration and reset unit for correlation 236, the correlation filters 234 being configured to be resettable with the common signal 299 where the spreading sequence generators 231 are configured to their clock frequency is equal to the chip rate, the digitizer units 235 having a sampling rate below the chip rate, the repetition frequency of the common reset signal 299 being equal to the sampling rate of the digitizing units 235, the analogue PSSS input signal being linked to N spreading sequences 201 and N linking elements 233 and the output signals of the N

Link elements with N correlation filters 234, e.g. integrated analog integrators that the correlation filter 234 (eg integrator) respectively at the beginning of the received spreading sequences are reset simultaneously with the signal SYNC 299 that the correlation filter 234 (eg integrator) over the duration of a code sequence, the input signal 232 integrates that after the integration at the outputs of the correlation filter 234 (eg integrators) in each case the decoded data signal 237 is applied, that the output signals of the correlation filter 237 (eg integrator) with N parallel digitizers 235 (eg AD converters) are digitized.

Embodiment of the device and the method are the subject of

Subclaims and are described below.

The invention relates to a mixed signal PSSS decoder circuit, which is composed of analog and digital elements and u.a. avoids fast AD converter in the PSSS receiver. The circuit principle is shown by way of example in FIG. 2 (N = 31).

The analogue PSSS input signal is combined with N spreading sequences (e.g., with an analogue multiplier) and integrated with N analogue integrators. The integrators become the beginning of the received spreading sequences, respectively

reset simultaneously with the signal SYNC. The optimum phase angle of the SYNC signal depends on the phase of the PSSS input signal and must be suitably set by means of a synchronization process. If the integrator has integrated the input signal over the duration of a code sequence, the decoded data signal is present at the output of the integrator after the last chip of the spreading sequence, ie a cross-correlation is carried out. In such a receiver, N cross-correlations are typically performed in parallel to decode all transmitted data. But you can also only part of the data through Recover cross correlation. The result of the cross-correlation can now be digitized with N parallel AD-converters.

FIG. 2 shows by way of example the inventive PSSS decoding circuit for real-valued input signals. In the case of complex-valued signals, each of the I and Q input signals must be linked to the respective spreading sequences and integrated in a common integrator and converted with a common AD converter. The advantage of the invention is on the one hand that instead of a very fast AD converter, which must have sufficiently high sampling rate and bandwidth in order to process the fast spreading sequences, now only AD converter are required, the data with the slow symbol rate. Furthermore, the resolution requirements of the A / D converters are also reduced because the integrator outputs have a lower dynamic range than the received coded PSSS signal. The disadvantage is that N are needed instead of just one AD converter. However, this is typically still more energy efficient and also requires less complex hardware (eg, chip area). According to a third teaching, the above-identified object is achieved by a device having a parallel PSSS receiver 300 having a parallel integrating and resetting unit 330 for correlation an input signal 332, a synchronization input 399 and output signals 337, digitizing units 335, each of the output signals 337 having one input each of the digitizing units

335 is connected and the digitizing units 335 output at their outputs each a digitized correlation result 368, wherein the parallel integrating and

Resetting unit for correlation 330 consists of integrating and resetting units for correlation 336, one integrating and resetting unit for correlation

336 consists of a respective spreading sequence generator with weighted chips 331, one linking element 333 and one correlation filter 334 each, wherein a linking element 333 at its inputs to the output of a

Spreading sequence generator with weighted chips 331 and the common Input signal 332 is connected, and is connected at its output to the input of a correlation filter 334, each of which generates an output signal 337 of an integration and reset unit for correlation 336, wherein the

Correlation filter 334 are configured to be reset with the common signal 399, wherein the weighted chip spreading sequence generators 331 are configured so that their clock frequency is equal to the chip rate, the linking element 333 being a multiplier, the digitizing units 335 having a sampling rate below the chip rate, wherein the repetition frequency of the common reset signal 399 is equal to the sampling rate of

Digitizing units 335 is.

According to a fourth teaching, the above-derived object is achieved by a method for decoding PSSS signals, in particular using a device having a parallel PSSS receiver 300 with a parallel integrating and resetting unit for correlation 330 with an input signal 332, a

Synchronization input 399 and output signals 337, digitizing units 335, each of the output signals 337 having one input each of the digitizing units

335 and the digitizing units 335 output at their outputs a digitized correlation result 368, respectively, the parallel integrating and resetting unit 330 for integrating and resetting units for correlation 330

Correlation 336, with an integrating and resetting unit for correlation

Spreading sequence generator with weighted chips 331 and the common

Input signal 332 is connected, and is connected at its output to the input of a correlation filter 334, each of which generates an output signal 337 of an integration and reset unit for correlation 336, wherein the

Correlation filter 334 are configured to be reset with the common signal 399, wherein the weighted chip spreading sequence generators 331 are configured so that their clock frequency is equal to the chip rate, the Logic element 333 is a multiplier, wherein the digitizing units 335 have a sampling rate below the chip rate, wherein the repetition frequency of the common reset signal 399 is equal to the sampling rate of the

Digitizing units 335, with the analog PSSS input signal N

Spreading sequences with weighted chips 301 and N logic elements 333 is linked and the output signals of the N logic elements with N

Correlation filtering 334, e.g. integrated with analog integrators, that the correlation filters 334 (eg integrator) are each reset at the beginning of the received spreading sequences simultaneously with the signal SYNC 399, that the correlation filter 334 (eg integrator) integrates the input signal 332 over the duration of a code sequence integrating at the outputs of the correlation filters 334 (eg, integrators) the decoded data signal 337, respectively, so that the output signals of the correlation filters 337 (eg, integrators) are digitized with N parallel digitizers 335 (eg AD converters).

Embodiment of the device and the method are the subject of

Subclaims and are described below.

A variant of the invention is shown by way of example in FIG. Here, instead of the original spreading sequences, modified spreading sequences are used in which the individual chips are weighted with coefficients. In this case, the weights of the chips of the spreading sequences are determined in such a way that the influence of the transmission channel is simultaneously compensated in the cross-correlation (channel development or channel equalization).

The advantage of the circuit is that now the PSSS decoding and the

Channel equalization can be performed in one step. This will not

Channel equalization filter needed more. Another advantage is that the channel equalization further reduces the dynamic range of the output of the integrator and simplifies the recovery of the data signal due to the smaller distortions. According to a further embodiment of the device according to the invention for decoding PSSS signals, the weighted chip spreading sequence generator 331 comprises an analog multiplexer 403, a state machine 402, weighted chip controllable sources 420, and a clock input 405 for the

State machine 402, wherein the analog multiplexer 403 by the

Control signal 409 is controllable by state machine 402 and that of the

Controlled sources 420 produced weighted chips 411 in response to the control signal 409 sequentially to an output signal 410 of the analog multiplexer 403, wherein the weighted chips 411 are set so that the influence of the transmission channel is compensated by the cross-correlation.

One way to make this correlation advantageous with weighted chips too

implement is shown in FIG.

A state machine 402 (SEL) clocked at the chip rate 405 generates a control signal 409 for an analog multiplexer 403. This sequentially switches the weighted chips 411.1 (b'll) to 411.m (b'lm) to a first one Input 410 of a multiplier 401. The weighted chips 411.1 (b'll) to 411.m (b'lm) can be realized for example by controlled voltage sources. The second input of the multiplier 401 is driven by the encoded PSSS signal 407. The output of the multiplier is sent to the correlation filter 404, e.g. an integrator, fed. The integrator is reset via the SYNC signal 1 406 at the beginning of the spreading sequence.

The advantage of the implementation in FIG. 4 is the very low hardware outlay and the low power loss.

According to a further embodiment of the device according to the invention for the decoding of PSSS signals, the device has a state machine 402, which has a plurality of analog multiplexers 403 of different integrators and integrators

Reset units for correlation 336 controls together. Referring to Figure 4, each correlator circuit 400 includes a state machine 402 (SEL). In an advantageous embodiment of the invention, the N of different integration and reset units for correlation 336 in FIGS. 2 and 3 can use a common state machine 402 (SEL), so that only 1

State machine 402 (SEL) is needed instead of N state machine 402 (SEL) for the receiver in FIGS. 2 and 3, respectively. This has the advantage that the power loss and the complexity of the overall circuit is reduced.

According to a further embodiment of the device according to the invention for decoding PSSS signals, the correlation filters 234, 334 are designed as resettable integrators.

According to a further embodiment of the device according to the invention for decoding PSSS signals, the correlation filters 234, 334 are designed as resettable low-pass filters.

The fact that simple low-pass filters are used instead of the integrators in FIGS. 2 or 3 results in the advantage that the hardware complexity and power loss are reduced. According to a further embodiment of the invention

Apparatus for decoding PSSS signals, the digitizing units 235, 335 are designed as analog-to-digital converters.

According to a further embodiment of the device according to the invention for decoding PSSS signals, the digitizing units 235, 335 are as

Comparators with a settable at a threshold voltage input

Threshold carried out and have a clock input, the am

Clock input applied clock frequency of the symbol rate corresponds.

In this embodiment of the invention, instead of the ADCs in FIG. 2 or 3 N, clocked comparators with adjustable threshold voltage VTH are used. The

Clock frequency of the comparators corresponds to the clock frequency of the slow ADCs in Figure 2 or 3, ie the symbol rate. The use of comparators has the advantage of lower circuit complexity and power dissipation compared to the use of ADCs. According to a further embodiment of the device according to the invention for

Decoding of PSSS signals, the device comprises an analog-to-digital converter, at least one digital-to-analog converter whose output is connected to a

Threshold voltage input of a comparator is connected, and a unit for digital calculation of the correlation reference, wherein the analog-to-digital converter is connected at its input to the result of the cross-correlation 337, at its output to the input of the unit for digital computation

Correlation reference is connected, whose output is connected to the input of the digital-to-analog converter so that the threshold voltages of the comparators are determined.

In this embodiment of the invention, the threshold voltage of the comparators is adjusted by means of a slow DA converter. The optimum threshold voltage is determined by estimating noise and signal components in the received signal. This is done with a slow ADC and the digital computation of the correlation reference. The ADC samples the correlation results. The sampling period corresponds to the total length of a spreading sequence (e.g., an m-sequence). From the sampled values, the received noise and the signal amplitude are calculated. From this, the optimal decision threshold is calculated and the input word of the slow DAC is set accordingly. According to a further embodiment of the device according to the invention for

To decode PSSS signals, state machine 402 is formed by a ring of flip-flops.

According to a further embodiment of the device according to the invention for decoding PSSS signals, individual integrating and resetting units for correlation 336.31 can be switched off. An advantage of this embodiment is that the power loss of the receiver can be adapted adaptively to the desired data rate by temporarily switching off a portion of the correlators. This can also be used advantageously, for example in point-to-multi-point communication scenarios. A further advantageous embodiment of the invention is that the analog multiplexer of N buffer amplifiers and N transmission gates is formed.

literature

DE 103 01 250.8

[2] IEEE 802.15.4-2006 Standard for Information technology, part 15.4 "Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs)", Sep. 8th, 2006

[3] A. Wolf, J. C. Scheytt, "15 Gbps Communication on USB3.0 Cable and Even More", 9th Interantional Multi-Converence on Systems, Signals, and Devices, March 20-23, 2012 Chemnitz, Germany

[4] EP 1359679. A2

[5] US 5029181

[6] US6330274 B1

Description of the figures

Figure 1 describes a PSSS transmission circuit for N = 31, wherein 151 denote the uncoded input data dl to d31 and 101 spreading sequences Bl to B31. Figure 2 describes a mixed-signal PSSS receiver circuit for N = 31, where 201 the spreading sequences B'l to B'31, 299 the reset signal SYNC for resetting the correlation filter 234, eg integrator, and 237 the decoded data signals, d'l bis d'31 designate. FIG. 3 describes a mixed-signal PSSS receiver circuit for N = 31, 301 weighted chip spreading sequences B'1 to B'31, 399 a reset signal SYNC for resetting the correlation filter 334, eg integrator, and 337 denote decoded data signals d'l to d'31.

FIG. 4 describes an implementation possibility of a weighted-chip correlation circuit 400, wherein weighted chips 411 (b'11 to b'lm) of a

Spreading sequence 410, 406 a reset signal SYNC for resetting a

Correlation filter 404, e.g. an integrator,, 402 a state machine 402 (SEL) for controlling the analog multiplexer 403 (AMUX), 401 a multiplier, and 405 the chip rate fchip. Figure 4 shows an exemplary

Implementation for m = 4.

Reference numerals:

101.1 to 101.31 Spreading sequences B1 to B31 with data rate equal to the chip rate 140 Linking element for linking spreading sequence and symbol (e.g., multiplier)

141 totalizers

142 multi-level PSSS signal

151.1 to 151.31 uncoded transmission data dl to d31 with data rate equal to

Symbol rate

200 Parallel PSSS receiver

201.1 to 201.31 spreading sequences B'l to B'31

230 Parallel integration and reset unit for correlation

231.1 to 231.31 spreading sequence generators for generating the signals 201.1 to

201.31

232 multi-level input signal, e.g. PSSS encoded

233 linking element for linking spreading sequences 201.1 to 201.31 and multi-level input signal 232 (e.g., multiplier)

234 correlation filters, e.g. Integration element or low-pass filter

235 digitizing unit, e.g. AD converter or comparator

236.31 Integrating and resetting unit for correlation with a

Spread sequence generator 231.31 for a spreading sequence 201.31, a

Link element 233 and a correlation filter 234

237.1 to 237.31 Result of the cross correlation d'l to d'31, analogue representation of the decoded data signal

268.1 to 268.31 Decoded data, digital representation of the decoded

data signal

299 SYNC signal for resetting the correlation filter 234

300 Parallel PSSS receiver with channel equalization capability

301.1 to 301.31 Spreading sequences B'l to B'31 with weighted chips

330 Parallel integration and reset unit for correlation

331.1 to 331.31 spreading sequence generators for generating the signals 301.1 to 301.31 332 multi-level input signal, eg PSSS coded

333 linking element for linking spreading sequences 301.1 to 301.31 and multi-level input signal 332 (e.g., multiplier)

334 correlation filters, e.g. Integration element or low-pass filter

335 digitizing unit, e.g. AD converter or comparator

336.31 Integrating and resetting unit for correlation with a

Spread sequence generator 331.31 for a spreading sequence 301.31, a

Link element 333 and a correlation filter 334

337.1 to 337.31 Result of the cross correlation d'l to d'31, analog representation of the decoded data signal

368.1 to 368.31 Decoded data, digital representation of the decoded

data signal

399 SYNC signal for resetting the correlation filters 334

400 Exemplary Implementation of an Integrate and Reset Unit for

correlation

401 linking element for combining the weighted spreading sequence 410 and multi-level input signal 407 (e.g., multiplier)

402 state machine for controlling the analog multiplexer 403

403 Analog Multiplexer

404 correlation filters, e.g. Integration element or low-pass filter

405 clock signal for state machine 402

406 SYNC signal for resetting the correlation filter 404

407 multi-level input signal, e.g. PSSS encoded

408 result of cross-correlation, analog representation of the decoded

Data signal, e.g. 337.31

409 control signal of the analog multiplexer 403

410 output of the analog multiplexer providing a weighted chip spreading sequence, e.g. 301.31

411.1 to 411.m m weighted chips b'll to b'lm

420.1 to 420. m m units for generating the weighted chips, e.g. controlled voltage sources

Claims

P a n t a n s p r e c h e

Apparatus comprising a parallel PSSS receiver 200 having a parallel integrating and resetting unit for correlating 230 with an input signal 232, a synchronization input 299 and output signals 237,

Digitizing units 235, each of the output signals 237 each having an input of the

Digitizing units 235 and the digitizing units 235 output a digitized correlation result 268 at their outputs, the parallel integrating and resetting unit for correlation 230 consisting of integrating and resetting units for correlation 236, one integrating and resetting unit for correlation 236 each one spreading sequence generator 231, one linking element 233 and one correlation filter 234 each, wherein a linking element 233 is connected at its inputs to the output of a spreading sequence generator 231 and the common input signal 232, and connected at its output to the input of a correlation filter 234 is, one each

Output signal 237 of an integrating and resetting unit for correlation 236 is generated, wherein the correlation filters 234 are configured so that they can be reset with the common signal 299, wherein the

Spreading sequence generators 231 are configured such that their clock frequency is equal to the chip rate, the digitizing units 235 having a sampling rate below the chip rate, wherein the repetition frequency of the common reset signal 299 is equal to the sampling rate of the digitizing units 235.

Apparatus comprising a parallel PSSS receiver 300 having a parallel integrating and resetting unit for correlating 330 with an input signal 332, a synchronization input 399, and output signals 337,

Digitizing units 335, each of the output signals 337 having one input each

Digitizing units 335 and the digitizing units 335 output a digitized correlation result 368 at their outputs, the parallel integrating and resetting unit for correlation 330 consisting of integrating and resetting units for correlation 336, and an integrating and resetting unit for correlation 336 each a spreading sequence generator with weighted chips 331, one each

Link element 333 and a respective correlation filter 334, wherein a linking element 333 at its inputs to the output of a

Spreading sequence generator is connected to weighted chips 331 and the common input signal 332, and connected at its output to the input of a correlation filter 334, which generates an output signal 337 of an integration and reset unit for correlation 336, wherein the correlation filter 334 are configured so that they are resettable with the common signal 399, the weighted chip spreading sequence generators 331 being configured so that their clock frequency is equal to the chip rate, the linking element 333 being a multiplier, wherein the digitizing units 335 have a sampling rate below the chip rate, wherein the repetition frequency of the common reset signal 399 is equal to the sampling rate of the digitizing units 335.

Apparatus according to claim 2, characterized in that the

Weighted chip spreading sequence generator 331 comprises an analog multiplexer 403, a state machine 402, weighted chip controllable sources 420 411, and a state machine 402 clock input 405, the analog multiplexer 403 being controlled by the control signal 409 of FIG

State machine 402 is controllable and the weighted chips 411 generated by the controllable sources 420 in response to the control signal 409 sequentially lead to an output signal 410 of the analog multiplexer 403, the weighted chips 411 are set so that the influence of the transmission channel by the cross-correlation compensated is.

Apparatus according to claim 3, characterized in that a

State machine 402 controls a plurality of analog multiplexers 403 of different integration and reset units to correlate 336 together.

Device according to one of the preceding claims, characterized

characterized in that the correlation filters 234, 334 are implemented as resettable integrators.

Device according to one of claims 1 to 4, characterized in that the correlation filter 234, 334 are designed as resettable low-pass filter. Device according to one of the preceding claims, characterized

characterized in that the digitizing units 235, 335 are designed as analog-to-digital converters.

Device according to one of claims 1 to 6, characterized in that the digitizing units 235, 335 as comparators with a on a

Threshold voltage adjustable threshold voltage are executed and have a clock input, wherein the clock frequency applied to the clock input corresponds to the symbol rate.

Apparatus according to claim 8, comprising an analog-to-digital converter, at least one digital-to-analog converter whose output is connected to a

Threshold voltage input of a comparator, and a unit for digitally calculating the correlation reference, the analogue to digital converter being connected at its input to the result of the cross correlation 337, connected at its output to the input of the digital unit for calculating the correlation reference, whose output is connected to the input of the digital-to-analog converter so that the

Threshold voltages of the comparators are determined.

Device according to the preceding claims, characterized in that the state machine 402 is formed by a ring of flip-flops.

Device according to the preceding claims, characterized in that individual integration and reset units for correlation 336.31 are switched off.