WO2014098557A1

WO2014098557A1 - A system and method for determining frequency of a signal

Info

Publication number: WO2014098557A1
Application number: PCT/MY2013/000238
Authority: WO
Inventors: Kien Seng LAM
Original assignee: Mimos Bhd.
Priority date: 2012-12-17
Filing date: 2013-12-06
Publication date: 2014-06-26
Also published as: MY187705A

Abstract

The present invention relates to a system (100) for determining frequency of a signal, comprising: an input (10) for receiving a signal; a delaying means (20) comprising a plurality of first delay cells (21), connected to the input (10) for receiving the signal, and delaying the signal by a first predetermined period to produce delayed signals; and an evaluating means (30) comprising a plurality of capturing means (32) connected to the delaying means (20) for capturing the delay signals and determining frequency of the signal; characterized in that the evaluating means (30) further comprises: a second delay cell (31) connected to the input (10) and at least a corresponding capturing means (32) for delaying the signal by a second predetermined period; a detector (33) connected to the plurality of capturing means (32) for receiving the captured delayed signals and detecting a predetermined pattern; and a processor (34) operating with the detector (33) for determining frequency of the signal, wherein the signal is a clock signal.

Description

A SYSTEM AND METHOD FOR DETERMINING FREQUENCY OF A SIGNAL

Field of the invention The present invention relates to the field of electronics, and more particularly the present invention relates to a system and method for determining frequency of a signal in an electronic circuit.

Background of the invention

Most integrated circuit requires a clock signal to synchronize different part of the circuit for an organized operation. A processor performs an instruction, reads, transmits, and receives data on the basis of one clock cycle. Typically, internal clock source is employed in an electronic circuit for providing the clock signal to the circuit operation.

However, there are several occasions for using an external clock source in a circuit, with one of the reasons being the need to support a higher range of frequency and higher accuracy which cannot be fulfilled by the internal clock source. Yet, the frequency of the external clock source needs to be identified to the respective integrated circuit to ensure proper behaviour of the circuit. Conventionally, the clock frequency of the external clock source is determined by using control input, either to encode the frequency value, or to use it as a fixed reference clock.

United States Patent No. 8089318 discloses a method for determining frequency of a reference clock on an integrated circuit. The method comprises the steps of counting a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count. The frequency of the reference clock is then estimated based on the reference clock cycle count and the sleep clock frequency. The sleep clock has a known frequency which can be used to estimate the reference clock frequency. In this prior art, the sleep clock is an additional input used as the reference clock for determination of the clock frequency. The additional input requires a larger board space and increases the cost involved. United States Patent No. 8175213 discloses a system and method for configuring threshold values of counters used in a system on a chip (SoC). The system comprises a plurality of memory cells and a frequency range sampler connected to a multiplexer which in turn connects to a counter. The counter receives a reference clock signal for generation of a system clock signal to the system on a chip.

The frequency range sampler receives frequency sub-range control which indicates the frequency sub-range of the reference clock signal which will then transmitted to the multiplexer for receiving a corresponding threshold value to send to the counter. Likewise, the prior art requires an additional input to the system which also adds to the costs involved.

United States Patent No. 7009439 discloses a method for generating an internal clock signal in a semiconductor memory device for synchronizing the operation by using an externally inputted clock signal. The external clock signal is determined whether it is high frequency or low frequency. A delayed unit is used to delay the external clock signal by time corresponding to a desired pulse-width. The delayed signal is logically combined with the external clock signal to generate an internal clock signal. The prior art requires generating a new internal clock signal based on external clock signal and thus the efficiency of the method may be reduced.

Accordingly, it can be seen in the prior arts that there exists a need to provide a self-sufficient system and method for determining clock frequency from an external clock source which does not require additional input to the system. Summary of Invention

It is an object of the present invention to provide a system and method for determining frequency of a signal without additional input to the circuit.

It is also an object of the present invention to provide a system and method for determining frequency of a signal which relies on internally generated reference signals. It is a further objective of the present invention to provide a system and method for determining frequency of a signal which captures delayed signals from the plurality of delay cells.

It is yet another object of the present invention to provide a system for determining frequency of a signal which has a detector for automatically detecting a pattern which can be used for estimating frequency.

Accordingly, these objectives may be achieved by following the teachings of the present invention. The present invention relates to a system for determining frequency of a signal, comprising: an input for receiving the signal; a delaying means comprising a plurality of first delay cells, connected to the input for receiving the signal, and delaying the signal by a first predetermined period to produce delayed signals; and an evaluating means comprising a plurality of capturing means connected to the delaying means for capturing the delay signals and determining frequency of the signal; characterized in that the evaluating means further comprises: a second delay cell connected to the input and at least a corresponding capturing means for delaying the signal by a second predetermined period; a detector connected to the plurality of capturing means for receiving the captured delayed signals and detecting a predetermined pattern; and a processor operating with the detector for determining frequency of the signal, wherein the signal is a clock signal. Brief descriptions of drawings

Figure 1 is a diagram showing a system for determining frequency of signal according to the present invention.

Figure 2 is flow chart showing a method for determining frequency of the signal according to the present invention.

Figure 3 is a timing diagram showing the pattern of the captured signals of an exemplary embodiment whereby the period of the signal is 2 nanoseconds according to the present invention.

Figure 4 is a timing diagram showing the pattern of the captured signals of yet another exemplary embodiment whereby the period of the signal is 3 nanoseconds according to the present invention.

Detailed description of the preferred embodiments

The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

The present invention is a system (100) for determining signal frequency in the field of electronics. The system comprises an input (10) for receiving a signal, a delaying means (20) and an evaluating means (30), whereby the delaying means (20) produce an array of delayed signals which are captured and detected by the evaluating means (30). A predetermined pattern is detected from which the signal frequency can be deducted. In a preferred embodiment, the signal is a clock signal provided to the system (100) for coordination of the instructions execution. The clock signal is received from an external source such that determination of the frequency is required. The clock signal is effectively a signal oscillating between a high and a low state, mostly in the form of a square wave, and thus having a frequency therewith. Therefore, the clock signal has a rising edge which is the transition of the signal from a low state to a high state and a falling edge which is the transition of the signal from a high state to a low state. Meanwhile, the clock period is referred to as the time required for the clock signal to repeat.

Figure 1 illustrates the overall connection of components in the system (1 00) of the present invention. The input (10) receives the signal from an external source. The delaying means (20) is connected to the input (10) for receiving and delaying the signal to produce delayed signals. The delaying means (20) preferably comprises a plurality of first delay cells (21 ) such that each of the plurality of the first delay cells (21 ) delays the signal by a first predetermined period. In a preferred embodiment, the plurality of the first delay cells (21 ) is connected in series and delays the signal cumulatively. In this way, a list of delayed signals is produced by the plurality of first delay cells (21 ).

The evaluating means (30) further comprises a plurality of capturing means (32) which is connected to the delaying means (20). In a preferred embodiment, the capturing means (32) is a flip-flop which is able to capture signals from the plurality of first delay cells (21 ). More particularly, the flip-flop is a delay flip-flop which is able to capture value upon triggered by the signal. Preferably, each of the plurality of first delay cells (21 ) is connected to a corresponding capturing means (32) such that the delayed signal from each of the plurality of first delay cells (21 ) can be captured. A second delay cell (31 ) is connected to the input (10) and the plurality of capturing means (32) for delaying the signal by a second predetermined period. The signal delayed by the second delay cell (31 ) is then transmitted to the plurality of capturing means (32). The signal delayed by the second delay cell (31 ) acts as a trigger for the plurality of the capturing means (32) to capture the delayed signals from the plurality of first delay cells (21 ). In a preferred embodiment, the second predetermined period is half the first predetermined period, such that the rising edge of the signal delayed by the second delay cell (31 ) triggers the action of the plurality of flip-flops (32) to capture delayed signals produced by the plurality of first delay cell (21 ).

Still referring to Figure 1 , a detector (33) in the evaluating means (30) is connected to each of the plurality of capturing means (32) for receiving the captured delayed signals and detecting a predetermined pattern. In a preferred embodiment, the predetermined pattern is the first occurrence of "01 " signal. A processor (34) operates with the detector (33) for determining frequency of the signal.

Further, the present invention relates to a method for determining the frequency of a signal. Initially, the system (100) receives the signal. The signal is then simultaneously transmitted to two paths for delaying of the signal. At the first path, the signal is delayed using a delaying means (20), whereas at the second path, the signal is delayed using a second delay cells (31 ). The signal delayed from the delaying means (20) in the first path is captured using at least a capturing means (32), and the pattern of which is subsequently detected. The frequency of the signal is then determined according to the pattern. Figure 2 illustrates an exemplary method of the present invention to determine the signal frequency. The incoming clock signal from an external clock source is received. The clock signal is then delayed by the plurality of the delay cells (21 ), whereby each of the plurality of delay cells (21 ) causes delay of the clock signal by the first predetermined period. The delayed signals from each of the plurality of first delay cells (21 ) are then captured by the corresponding connected flip- flops (32). The capture of the delayed signals is triggered by the signal delayed by the second delay cell (31 ) at the rising edge thereof. The pattern of the captured delayed signals is then detected. In a preferred embodiment, the pattern of the captured delayed signal is provided in n-bit binary vector to the detector (33) for further processing. In a specific embodiment, the pattern of the captured delayed signals in n-bit binary vector is then searched through starting from the least significant bit to locate the first occurrence of the "01 " pattern. Based on the result, the frequency of the signal is then determined. The calculation involved for determining the clock frequency will be described herein. The first occurrence of "01 " pattern, denoted as n_detect, together with the first predetermined period, tdeiay, can be used to obtain the clock period of the clock signal, with a condition that the second predetermined period is half of the first predetermined period. The inverse of the incoming clock period value gives the frequency value of the incoming clock signal. The formula of which is given by: i

Frequency of signal = Hz

ndetect ^x tdeiay Example 1

With reference to Figure 3 which is a timing diagram showing the delayed clock signals in an example, the delay of the first predetermined period is by 1 nanosecond and the second predetermined period is 0.5 nanoseconds, while the incoming clock period is 2 nanoseconds. A list of the delayed signals is produced with each subsequent delayed signal having an increasing period of delay than the previous. The detector (33) will search through the n-bit binary vector and the first occurrence of "01 " pattern will be detected at bit 2. Hence, the determined frequency of the clock signal would be 1 /(2x1 ns) Hz. Example 2

Figure 4 shows another example for determining the frequency of the clock signal. With the first predetermined period of 1 ns, the second predetermined period of 0.5 nanoseconds, and an incoming clock period of 3 ns, a list of delayed signals as shown in the Figure 4 will be captured and the captured delayed signals pattern would be "01 10". Thus, the first occurrence of "01" pattern is detected from the least significant bit, thus at bit 3 in this case. With this information, it can be verified that the frequency of the signal would be 1 /(3x1 ns) Hz.

Although the present invention has been described in a specific embodiment as in the above description, it is understood that the above description does not limit the invention to the above given details. It will be apparent to those skilled in the art that various changes and modification may be made therein without departing from the principle of the invention or from the scope of the appended claims.

Claims

1 . A system (100) for determining frequency of a signal, comprising:

an input (10) for receiving a signal;

a delaying means (20) comprising a plurality of first delay cells (21 ), connected to the input (1 0) for receiving the signal, and delaying the signal by a first predetermined period to produce delayed signals; and an evaluating means (30) comprising a plurality of capturing means (32) connected to the delaying means (20) for capturing the delay signals and determining frequency of the signal;

characterized in that the evaluating means (30) further comprises: a second delay cell (31 ) connected to the input (10) and at least a corresponding capturing means (32) for delaying the signal by a second predetermined period;

a detector (33) connected to the plurality of capturing means (32) for receiving the captured delayed signals and detecting a predetermined pattern; and

a processor (34) operating with the detector (33) for determining frequency of the signal.

2. A system (100) for determining frequency of a signal according to Claim 1 , wherein the plurality of first delay cells (21 ) is connected in series and delays the signal cumulatively.

3. A system (100) for determining frequency of a signal according to Claim 1 , wherein each of the plurality of first delay cells (21 ) is connected to a corresponding capturing means (32).

4. A system (100) for determining frequency of a signal according to Claim 1 , wherein the plurality of capturing means (32) is flip-flops.

5. A system (100) for determining frequency of a signal according to Claim 1 , wherein the second predetermined period is half of the first predetermined period.

6. A method for determining frequency of a signal, in accordance to the system as claimed in Claim 1 , characterized by the steps of:

receiving a signal by an input (10);

delaying the signal using a delaying means (20);

delaying the signal using a second delay cell (31 );

capturing the delayed signals from the delaying means (20) using at least a capturing means (32), wherein the capturing means (32) is trigerred by the second delay cell (31 );

detecting a pattern from the captured delayed signals using a detector (33);

determining frequency of the signal by using a processor (34).

7. A method for determining frequency of a signal according to Claim 6, wherein the pattern of the captured delayed signals is in the form of n-bit binary vector.