WO2014172957A1

WO2014172957A1 - Circuit board, preparation method therefor, and display apparatus

Info

Publication number: WO2014172957A1
Application number: PCT/CN2013/076593
Authority: WO
Inventors: 孙冰
Original assignee: 京东方科技集团股份有限公司
Priority date: 2013-04-25
Filing date: 2013-05-31
Publication date: 2014-10-30
Also published as: CN103280447A; CN103280447B

Abstract

A circuit board, a manufacturing method therefor, and a display apparatus. The circuit comprises a wiring. The wiring comprises a first metal layer (2), a stress adjustment layer (3), and a second metal layer (4). The stress adjustment layer (3) is located between the first metal layer (2) and the second metal layer (4). The first metal layer (2) and the stress adjustment layer (3) are arranged into a step shape. An end portion of the second metal layer (4) contacts the first metal layer (2).

Description

Circuit board, manufacturing method thereof and display device

Embodiments of the present invention relate to a circuit board, a method of fabricating the same, and a display device. Background technique

In recent years, with the development of technology, liquid crystal display technology has also been continuously improved. TFT-LCD (Thin Film Transistor-Liquid Crystal Display) occupies an important position in the display field with its image display quality, low energy consumption and environmental protection.

The aperture ratio is an important indicator of the performance of TFT-LCD products. In order to achieve a large aperture ratio, a low-resistance laminated structure film is generally used as the metal electrode. The multi-layer structure inevitably causes the thickness of the structure to increase. However, the greater the thickness of the metal wire, the higher the probability of metal wire failure, which in turn limits the resistance of the metal. Moreover, the step difference caused by the high-thickness film after etching causes the subsequent electrode disconnection phenomenon to be greatly increased, which seriously affects the performance of the TFT product and reduces the yield of the TFT product. Summary of the invention

Embodiments of the present invention provide a circuit board, a method of fabricating the same, and a display device, which can overcome the defects such as a decrease in yield with a thickening of a metal thin film layer in an existing array substrate.

An aspect of the invention provides a circuit board including a wiring, the wiring comprising: a first metal layer, a stress adjustment layer, and a second metal layer, the stress adjustment layer being located between the first metal layer and the second metal layer, The first metal layer and the stress adjustment layer are disposed in a stepped shape, and an end of the second metal layer is in contact with the first metal layer.

In the circuit board, for example, the thicknesses of the first metal layer and the second metal layer are respectively

1000-5000 angstroms.

In the circuit board, for example, the stress adjustment layer is one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a composite structure of at least two of the above films.

In the circuit board, for example, the first metal layer is a laminate including a first metal sublayer and a first buffer layer, and the second metal layer includes a laminate of a second metal sublayer and a second buffer layer. . In the circuit board, for example, the first metal sublayer and the second metal sublayer are low resistance metals. In the circuit board, for example, the first buffer layer and the second buffer layer are each one of Mo, Ti, Cr or an alloy of at least two of the above.

In the circuit board, for example, the first buffer layer is located below the first metal sublayer, the first metal sublayer is adjacent to the stress adjustment layer; and the second buffer layer is located on the second metal sublayer Above, the second metal sublayer is adjacent to the stress adjustment layer.

In the circuit board, for example, the first metal layer and the second metal layer structure are stepped. The circuit board, for example, further includes a thin film transistor, wherein the wiring includes a portion corresponding to an electrode of the thin film transistor.

In the circuit board, for example, a portion of an electrode of the thin film transistor is a gate, a source or a drain.

The circuit board, for example, further includes a thin film transistor including a gate line or a data line connected to the thin film transistor.

Another aspect of the present invention provides a display device including an array substrate, wherein the array substrate is formed of any of the above-described circuit boards.

According to still another aspect of the present invention, a method of fabricating a wiring or an electrode, comprising: forming a pattern of a first metal layer on a substrate; forming a pattern of a stress adjustment layer on a pattern of the first metal layer; A pattern of the second metal layer is formed on the pattern of the stress adjustment layer. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, rather than to the present invention. limit.

1 is a schematic view of a first metal layer and a stress adjustment layer in an array substrate according to an embodiment of the present invention; and FIG. 2 is a schematic structural view of a first metal layer, a stress adjustment layer, and a second metal layer in an array substrate according to an embodiment of the present invention. detailed description

The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. Obviously, The described embodiments are a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

Unless otherwise defined, technical terms or scientific terms used herein shall be of the ordinary meaning understood by those of ordinary skill in the art to which the invention pertains. The terms "first", "second" and similar terms used in the specification and claims of the invention are not intended to indicate any order, quantity or importance, but are merely used to distinguish different components. Similarly, the words "a", "an" or "the" do not mean a quantity limitation, but rather mean that there is at least one. The words "including" or "comprising", etc., are intended to mean that "a" or "comprising" or "an" Component or object. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "Down", "Left", "Right", etc. are only used to indicate the relative positional relationship. When the absolute position of the object to be described is changed, the relative positional relationship may also change accordingly.

It should be noted that the array substrate in the display device is one of the circuit boards. Hereinafter, the present embodiment will be described by taking an array substrate as an example. Although the following description is made by taking an array substrate in a display device as an example, those skilled in the art should understand that the design of the wiring and electrodes disclosed in the present invention can also be applied to various types of thin film transistors including wiring and/or electrodes. Circuit board. The wiring is not limited to being wired for a gate line, a data line, or a common electrode line, and may be any wiring that can be fabricated on a circuit board.

The array substrate provided by the embodiment of the invention includes a gate, a gate line, a data line, and a source and a drain. Alternatively, the gate can be considered part of the gate line, and the source or drain connected to the data line can also be considered part of the data line. At least one of the above structures includes the structure described in the following embodiments. In the present embodiment, a gate (gate line) is taken as an example for illustrative purposes.

As shown in the cross-sectional views of FIGS. 1 and 2, the array substrate includes a glass substrate 1 on which a first metal layer 2, a stress adjustment layer 3, and a second metal layer 4 are disposed, the stress adjustment layer 3 Located between the first metal layer 2 and the second metal layer 4, the first metal layer 2 and the stress adjustment layer 3 are arranged in a stepped shape, and the edge S of the first metal layer 2 and the stress adjustment layer 3 is opposite to The layer has a certain height difference (or step difference). Moreover, the end of the second metal layer 4 is in contact with the end of the first metal layer 2. The first metal layer 2 is a laminate including a first metal sub-layer and a first buffer layer, and the second metal layer 4 is a laminate including a second metal sub-layer and a second buffer layer.

Since stress concentration is easily generated between the two metal layers, stress concentration will cause a hillock, and the room for stress adjustment between the metal layers is very small. However, in the embodiment of the present invention, the stress adjustment layer 3 is provided between the two metal layers, and the stress adjustment layer 3 is one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or at least two kinds of the above films. The composite structure, therefore, can effectively reduce the stress between the two metal layers, correspondingly greatly improve the wiring performance of the metal layer, and improve product yield.

In addition, in the embodiment of the present invention, the first metal layer 2 and the stress adjustment layer 3 are arranged in a stepped shape, and the end of the second metal layer 4 is in contact with the first metal layer 2, and the first metal layer 2 and the second layer are ensured. Under the premise that the two metal layers 4 are electrically conductive, there is a buffer step difference between the first metal layer 2 and the stress adjustment layer 3, so that the probability of disconnection of the subsequent structural layer can be effectively avoided.

For example, the thicknesses of the first metal layer 2 and the second metal layer 4 are respectively 1000 to 5000 angstroms. The first metal sublayer and the second metal sublayer are generally made of a low resistance metal, and preferably a low resistance wiring metal such as Cu or Al.

The first buffer layer and the second buffer layer may be one of Mo, Ti, Cr, or an alloy of at least two of the foregoing, the first buffer layer and the second buffer layer respectively facing the first metal sublayer and the second The metal sublayer acts as a good buffer and protection. In addition to the above preferred materials, other materials having the same physical properties as the above materials may be used.

The materials of the common two-layer metal laminate are preferably: Cu/Ti and Al/Mo, Cu/Mo and Al/Ti,

Cu/Ni and Al/Cr, Cu/Cr and Al/Ti, and the like. In addition to the above preferred materials, other materials having the same physical properties as the above materials may be used.

In order to maximize the conductivity of the metal, it is generally set that the first buffer layer is located below the first metal sublayer, such that the first metal sublayer is adjacent to the stress adjustment layer; and the second buffer layer is located at the second metal layer. Above the sub-layer; bringing the second metal sub-layer close to the stress adjustment layer.

For example, when the laminate material of the first metal layer is Cu/Ti and the laminate material of the second metal layer is Al/Mo, the Ti layer may be disposed on the Cu layer to promote the Ti layer to be compared with the glass substrate. Good fusion; the Mo layer is placed on the A1 layer to further protect the performance of the softer A1 layer. It should be noted that, in practical applications, including but not limited to the above settings, the positional relationship between the metal layer and the buffer layer can be reasonably set according to the properties of the selected metal. For example, in order to further avoid the problem of disconnection of the subsequent electrodes, the first metal layer can also be provided.

2 and the second metal layer 4 has a stepped structure.

It should be noted that, in this embodiment, only the gate is exemplified, and the above-mentioned structure may also be adopted for the gate line, the data line, and the electrodes and wirings of the source and drain electrodes on the array substrate.

Further, an embodiment of the present invention also provides a display device including the above array substrate. The display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and the like, or any product or component having a display function.

Embodiments of the present invention also provide a method of processing an array substrate, and an example of the method includes the following steps S301 to S304:

Step S301, forming a pattern of the gate on the glass substrate.

For example, a first metal layer having a thickness of about 1000 to 5000 A is deposited by sputtering or thermal evaporation on a glass substrate or a transparent quartz substrate as a base substrate.

For example, a stress adjustment layer such as SiO ₂ , 81 Ω is continuously deposited on the substrate on which the above steps are completed, and a pattern of the first metal layer and a pattern of the stress adjustment layer are formed by photolithography by a first halftone or gray tone mask exposure process. The pattern of the first metal layer includes a stacked pattern of the first metal sub-layer pattern and the first buffer layer pattern. The first metal layer and the stress adjustment layer pattern are arranged in a step shape.

For example, a second metal layer having a thickness of about 1000 to 500 θ is deposited by sputtering or thermal evaporation on the substrate on which the above steps are performed, and a pattern of the second metal layer is formed by a second photolithography process. The pattern of the second metal layer includes a stacked pattern of the second metal sublayer pattern and the second buffer layer pattern.

Step S302, continuously depositing a semiconductor layer having a thickness of 1000-3000 A and a 500-1000 A ohm contact layer by a PECVD (plasma enhanced chemical vapor deposition) method on the glass substrate completing the above steps, and the reaction gas corresponding to the semiconductor layer may be Si , H ₂ or SiH ₂ Cl ₂ , H ₂ . The reaction gas corresponding to the ohmic contact layer may be SiH ₄ , PH ₃ , _3⁄4 or 8 _3⁄4 ( 1 ₂ , PH ₃ , H ₂ . The relief layer Mo, Ta, Ti, Ni having a thickness of 500 ~ 1000θΑ is formed by sputtering or thermal evaporation. A metal or alloy such as MoTi or MoNb is exposed and developed by a halftone or gray tone mask, and after a plurality of etching steps, a semiconductor layer pattern, a TFT channel, a source electrode drain electrode, and a data line are formed.

Step S303, depositing a passivation layer having a thickness of about 700 to 5000 A by a PECVD method on the completed glass, and forming a via hole in the passivation layer. The passivation layer may be an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , N ₂ .

Step S304, depositing a layer by sputtering or thermal evaporation on the substrate on which the above steps are completed. The transparent conductive layer has a thickness of about 300 ~ 600 A, and the transparent conductive layer is generally ITO or IZO, and may be other metals and metal oxides; the transparent pixel electrode is formed by one photolithography.

It should be noted that the method for forming the above array substrate includes, but is not limited to, the above-mentioned process method. Except for the fabrication process of the gate electrode, other structures are obtained, for example, by a known or open technology. In addition, in this embodiment, the method of forming the stress adjustment layer is added to the fabrication process of the gate and the gate line as an example, and those skilled in the art should understand that the data line and the source and drain electrodes and the like are arranged. The above method can also be employed in the formation process.

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

claims

1. A circuit board, including wiring, and the wiring includes:

a first metal layer, a stress adjustment layer and a second metal layer, the stress adjustment layer is located between the first metal layer and the second metal layer, the first metal layer and the stress adjustment layer are arranged in a ladder shape, and the second An end of the metal layer is in contact with the first metal layer.

2. The circuit board of claim 1, wherein the thicknesses of the first metal layer and the second metal layer are 1000~5000 angstroms respectively.

3. The circuit board according to claim 1 or 2, wherein the stress adjustment layer is one of a silicon oxide film, a silicon nitride film and a silicon oxynitride film, or a composite structure of at least two of the above films. .

4. The circuit board according to any one of claims 1 to 3, wherein the first metal layer is a stack including a first metal sub-layer and a first buffer layer, and the second metal layer includes a second metal layer. A stack of sublayers and a second buffer layer.

5. The circuit board of claim 4, wherein the first metal sub-layer and the second metal sub-layer are low-resistance metal.

6. The circuit board according to claim 4, wherein the first buffer layer and the second buffer layer are respectively one of Mo, Ti, Cr or an alloy composed of at least two of the above.

7. The circuit board of claim 4, wherein the first buffer layer is located below the first metal sub-layer, and the first metal sub-layer is close to the stress adjustment layer; and the second buffer layer is located under the first metal sub-layer. Above the second metal sub-layer, the second metal sub-layer is close to the stress adjustment layer.

8. The circuit board according to any one of claims 1 to 7, wherein the first metal layer and the second metal layer have a stepped structure.

9. The circuit board according to any one of claims 1 to 8, further comprising a thin film transistor, wherein the wiring includes a portion corresponding to an electrode of the thin film transistor.

10. The circuit board according to claim 9, wherein part of the electrode of the thin film transistor is a gate electrode, a source electrode or a drain electrode.

11. The circuit board according to any one of claims 1 to 8, further comprising a thin film transistor, and the wiring includes a gate line or a data line connected to the thin film transistor.

12. A display device including an array substrate, wherein the array substrate according to claims 1-11 The circuit board of any one is formed.

13. A method of manufacturing wiring or electrodes, including: forming a pattern of a first metal layer on a substrate;

forming a pattern of a stress adjustment layer on the pattern of the first metal layer;