WO2015008870A2 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2015008870A2
WO2015008870A2 PCT/JP2014/069265 JP2014069265W WO2015008870A2 WO 2015008870 A2 WO2015008870 A2 WO 2015008870A2 JP 2014069265 W JP2014069265 W JP 2014069265W WO 2015008870 A2 WO2015008870 A2 WO 2015008870A2
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WO
WIPO (PCT)
Prior art keywords
intermediate structural
electrode
semiconductor device
structural bodies
semiconductor member
Prior art date
Application number
PCT/JP2014/069265
Other languages
French (fr)
Other versions
WO2015008870A4 (en
WO2015008870A3 (en
Inventor
Yoshiaki Sugizaki
Akihiro Kojima
Original Assignee
Kabushiki Kaisha Toshiba
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Publication date
Application filed by Kabushiki Kaisha Toshiba filed Critical Kabushiki Kaisha Toshiba
Publication of WO2015008870A2 publication Critical patent/WO2015008870A2/en
Publication of WO2015008870A3 publication Critical patent/WO2015008870A3/en
Publication of WO2015008870A4 publication Critical patent/WO2015008870A4/en

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    • H—ELECTRICITY
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    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Definitions

  • Embodiments of the invention relates to a semiconductor device and a method for manufacturing the same.
  • FIG. 1A is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment.
  • FIG. IB is a cross-sectional view along line A-A' shown in FIG. 1A.
  • FIG. 2A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 2B is a cross-sectional view along line A-A' shown in FIG. 2A.
  • FIG. 3A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 3B is a cross-sectional view along line A-A' shown in FIG. 3A.
  • FIG. 4A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 4B is a cross-sectional view along line A-A' shown in FIG. 4A.
  • FIG. 5A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 5B is a cross-sectional view along line A-A' shown in FIG. 5A.
  • FIG. 6A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 6B is a cross-sectional view along line A-A' shown in FIG. 6A.
  • FIG. 7 is a cross-sectional view showing an arranging machine used in the first embodiment.
  • FIGS. 8A and 8B are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 9A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 9B is a cross-sectional view along line A-A' shown in FIG. 9A.
  • FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 11 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIGS. 12A and 12B are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIGS. 13A and 13B are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 14A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and
  • FIG. 14B is a cross-sectional view along line A-A' shown in FIG. 14A.
  • FIG. 15A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 15B is a cross-sectional view along line A-A' shown in FIG. 15A.
  • FIG. 16A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 16B is a cross-sectional view along line A-A' shown in FIG. 16A.
  • FIG. 17A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 17B is a cross-sectional view along line A-A' shown in FIG. 17A.
  • FIG. 18A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 18B is a cross-sectional view along line A-A' shown in FIG. 18A.
  • FIGS. 19A and 19B are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIGS. 20A and 20B are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 21A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 21B is a cross-sectional view along line A-A' shown in FIG. 21A.
  • FIG. 22A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 22B is a cross-sectional view along line A-A' shown in FIG. 22A.
  • FIG. 23 is a plan view showing an intermediate structural body of a first modification of the first embodiment.
  • FIG. 24 is a plan view showing an intermediate structural body of a second modification of the first embodiment.
  • FIG. 25 is a plan view showing an intermediate structural body of a third modification of the first embodiment.
  • FIG. 26A is a plan view showing an intermediate structural body of a fourth modification of the first embodiment
  • FIG. 26B is a cross-sectional view along line A-A' shown in FIG. 26A
  • FIG. 26C is a perspective view as viewed from the lower side.
  • FIG. 27A is a cross-sectional view showing an intermediate structural body of a fifth modification of the first embodiment
  • FIG. 27B is a perspective view showing the intermediate structural body and the recess
  • FIG. 27C is a perspective view showing the state in which the intermediate structural body engages with the recess.
  • FIGS. 28A to 28D are cross-sectional views showing a method for manufacturing a semiconductor device according to the sixth modification of the first embodiment.
  • FIGS. 29A and 29B are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh modification of the first embodiment.
  • FIGS. 30A and 30B are cross-sectional views showing a method for manufacturing a semiconductor device according to an eighth modification of the first embodiment.
  • FIG . 31A is a plan view showing a method for manufacturing a semiconductor device according to a second embodiment; and FIG. 31 B is a cross-sectional view along line
  • FIG . 32A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG . 32B is a cross-sectional view along line A-A' shown in FIG. 32A.
  • FIG. 33A is a plan view showing the method for manufacturing the semiconductor device according to the second em bodiment; and FIG . 33B is a cross-sectional view along line A-A' shown in FIG. 33A.
  • FIG. 34A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 34B is a cross-sectional view along line A-A' shown in FIG. 34A.
  • FIGS. 35A and 35B and FIG. 36 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.
  • FIG. 37A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 37B is a cross-sectional view along line A-A' shown in FIG. 37A.
  • FIGS. 38A and 38B are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.
  • FIG. 39A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 39B is a cross-sectional view along line A-A' shown in FIG. 39A.
  • FIG. 40A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 40B is a cross-sectional view along line A-A' shown in FIG. 40A.
  • FIG. 41A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 41B is a cross-sectional view along line A-A' shown in FIG. 41A.
  • FIG. 42A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 42B is a cross-sectional view along line A-A' shown in FIG. 42A.
  • FIG. 43A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 43B is a cross-sectional view along line A-A' shown in FIG. 43A.
  • FIG. 44A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 44B is a cross-sectional view along line A-A' shown in FIG. 44A.
  • FIG. 45 is a plan view showing a method for manufacturing a semiconductor device according to a third embodiment.
  • FIG. 46 is a plan view showing a method for manufacturing a semiconductor device according to a modification of the third embodiment.
  • FIG. 47 and FIG. 48 are perspective views showing a method for manufacturing a semiconductor device according to a fourth embodiment.
  • FIG. 49A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 49B is a cross-sectional view along line A-A' shown in FIG. 49A.
  • FIG. 50A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 50B is a cross-sectional view along line A-A' shown in FIG. 50A.
  • FIG. 51 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment.
  • FIG. 52A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 52B is a cross-sectional view along line A-A' shown in FIG. 52A.
  • FIG. 53A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 53B is a cross-sectional view along line A-A' shown in FIG. 53A.
  • FIG. 54A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 54B is a cross-sectional view along line A-A' shown in FIG. 54A.
  • FIG. 55A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 55B is a cross-sectional view along line A-A' shown in FIG. 55A.
  • FIG. 56A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 56B is a cross-sectional view along line A-A' shown in FIG. 56A.
  • FIGS. 57A and 57B and FIG. 58 are cross-sectional views showing the method for manufacturing the semiconductor device according to the fourth embodiment.
  • FIG. 59 is a drawing comparing the configurations of an
  • FIG. 60A is a plan view showing a method for manufacturing a semiconductor device according to a fifth embodiment
  • FIG. 60B is a plan view showing the semiconductor device
  • FIG. 60C is a drawing showing a relationship between configurations of semiconductor members.
  • FIGS. 61A to 61D are drawings comparing configurations of intermediate structural bodies of a modification of the fifth embodiment.
  • FIG. 62A is a plan view showing a method for manufacturing a semiconductor device according to a sixth embodiment; and FIG. 62B is a cross-sectional view along line A-A' shown in FIG. 62A.
  • FIG. 63A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 63B is a cross-sectional view along line A-A' shown in FIG. 63A.
  • FIG. 64A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 64B is a cross-sectional view along line A-A' shown in FIG. 64A.
  • FIG. 65A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 65B is a cross-sectional view along line A-A' shown in FIG. 65A.
  • FIG. 66A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 66B is a cross-sectional view along line A-A' shown in FIG. 66A.
  • FIG. 67A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 67B is a cross-sectional view along line A-A' shown in FIG. 67A.
  • FIG. 68A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 68B is a cross-sectional view along line A-A' shown in FIG. 68A.
  • FIGS. 69A to 69C are drawings showing the method for manufacturing the semiconductor device according to the sixth embodiment.
  • FIG. 69A is a plan view of an intermediate structural body as viewed from a crystal growth substrate side
  • FIG. 69B is a plan view as viewed from an LED layer side
  • FIG. 69C is a cross-sectional view along line A-A' shown in FIG. 69B.
  • FIG. 70 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the sixth embodiment.
  • FIG. 71A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 71B is a cross-sectional view along line A-A' shown in FIG. 71A.
  • FIGS. 72 to 75 are cross-sectional views showing the method for manufacturing the semiconductor device according to the sixth embodiment.
  • FIG. 76A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 76B is a cross-sectional view along line A-A' shown in FIG. 76A.
  • FIG. 77A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 77B is a cross-sectional view along line A-A' shown in FIG. 77A.
  • FIG. 78A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 78B is a cross-sectional view along line A-A' shown in FIG. 78A.
  • FIG. 79A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 79B is a cross-sectional view along line A-A' shown in FIG. 79A.
  • FIG. 80A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 80B is a cross-sectional view along line A-A' shown in FIG. 80A.
  • FIG. 81A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 81B is a cross-sectional view along line A-A' shown in FIG. 81A.
  • FIG. 82A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 82B is a cross-sectional view along line A-A' shown in FIG. 82A.
  • FIG. 83A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 83B is a cross-sectional view along line A-A' shown in FIG. 83A.
  • FIG. 84A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 84B is a cross-sectional view along line A-A' shown in FIG. 84A.
  • FIG. 85A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 85B is a cross-sectional view along line A-A' shown in FIG. 85A.
  • FIG. 86A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 86B is a cross-sectional view along line A-A' shown in FIG. 86A.
  • FIG. 87A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 87B is a cross-sectional view along line A-A' shown in FIG. 87A.
  • FIG. 88A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 88B is a cross-sectional view along line A-A' shown in FIG. 88A.
  • FIG. 89A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 89B is a cross-sectional view along line A-A' shown in FIG. 89A.
  • FIG. 90A is a plan view showing a method for manufacturing a semiconductor device according to a modification of the sixth embodiment; and FIG. 90B is a cross-sectional view along line A-A' shown in FIG. 90A.
  • FIG. 91A is a plan view showing the method for manufacturing the semiconductor device according to the modification of the sixth embodiment; and FIG. 91B is a cross-sectional view along line A-A' shown in FIG. 91A.
  • FIG. 92A is a plan view showing the method for manufacturing the semiconductor device according to the modification of the sixth embodiment; and FIG. 92B is a cross-sectional view along line A-A' shown in FIG. 92A.
  • FIG. 93A is a plan view showing a method for manufacturing a semiconductor device according to a seventh embodiment; and FIG. 93B is a cross-sectional view along line A-A' shown in FIG. 93A.
  • FIG. 94A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 94B is a cross-sectional view along line A-A' shown in FIG. 94A.
  • FIG. 95A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 95B is a cross-sectional view along line A-A' shown in FIG. 95A.
  • FIG. 96A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 96B is a cross-sectional view along line A-A' shown in FIG. 96A.
  • FIG. 97A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 97B is a cross-sectional view along line A-A' shown in FIG. 97A.
  • FIG. 98A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 98B is a cross-sectional view along line A-A' shown in FIG. 98A.
  • FIG. 99A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 99B is a cross-sectional view along line A-A' shown in FIG. 99A.
  • FIGS. 100A to 100H are drawings showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 100A is a plan view of the LED chip as viewed from the crystal growth substrate side
  • FIG. 100B is a cross-sectional view along line A-A' shown in FIG. 100A
  • FIG. lOOC is a plan view as viewed from the LED layer side
  • FIG. 100D is a plan view of the Zener diode chip as viewed from the upper surface side
  • FIG. 100E is a cross-sectional view
  • FIG. 100F is a plan view as viewed from the lower surface side
  • FIG. 100G is a top view showing the conduction dummy chip
  • FIG. 100H is a side view.
  • FIG. 101 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the seventh embodiment.
  • FIG. 102A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 102B is a cross-sectional view along line A-A' shown in FIG. 102A.
  • FIG. 103 and FIG. 104 are cross-sectional views showing the method for manufacturing the semiconductor device according to the seventh embodiment.
  • FIGS. 105A and 105B and FIGS. 106A and 106B are cross-sectional views showing the method for manufacturing the semiconductor device according to the seventh embodiment.
  • FIG. 107A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 107B is a cross-sectional view along line A-A' shown in FIG. 107A
  • FIG. 107C is a cross-sectional view along line B-B' shown in FIG 107A.
  • FIG. 108A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 108B is a cross-sectional view along line A-A' shown in FIG. 108A
  • FIG. 108C is a cross-sectional view along line B-B' shown in FIG 108A.
  • FIG. 109A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 109B is a cross-sectional view along line A-A' shown in FIG. 109A
  • FIG. 109C is a cross-sectional view along line B-B' shown in FIG 109A.
  • FIG. 110A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. HOB is a cross-sectional view along line A-A' shown in FIG. 110A
  • FIG. HOC is a cross-sectional view along line B-B' shown in FIG 110A.
  • FIG. 111A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 111B is a cross-sectional view along line A-A' shown in FIG. 111A
  • FIG. 111C is a cross-sectional view along line B-B' shown in FIG 111A.
  • FIG. 112A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 112B is a cross-sectional view along line A-A' shown in FIG. 112A
  • FIG. 112C is a cross-sectional view along line B-B' shown in FIG 112A.
  • FIG. 113A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 113B is a cross-sectional view along line A-A' shown in FIG. 113A
  • FIG. 113C is a cross-sectional view along line B-B' shown in FIG 113A.
  • FIG. 114A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 114B is a cross-sectional view along line A-A' shown in FIG. 114A
  • FIG. 114C is a cross-sectional view along line B-B' shown in FIG 114A.
  • FIG. 115A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 115B is a cross-sectional view along line A-A' shown in FIG. 115A
  • FIG. 115C is a cross-sectional view along line B-B' shown in FIG 115A.
  • FIG. 116A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 116B is a cross-sectional view along line A-A' shown in FIG. 116A
  • FIG. 116C is a cross-sectional view along line B-B' shown in FIG 116A.
  • FIG. 117A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 117B is a cross-sectional view along line A-A' shown in FIG. 117A
  • FIG. 117C is a cross-sectional view along line B-B' shown in FIG 117A.
  • FIG. 118A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 118B is a cross-sectional view along line A-A' shown in FIG. 118A
  • FIG. 118C is a cross-sectional view along line B-B' shown in FIG 118A.
  • FIG. 119A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 119B is a cross-sectional view along line A-A' shown in FIG. 119A
  • FIG. 119C is a cross-sectional view along line B-B' shown in FIG 119A.
  • FIG. 120A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 120B is a cross-sectional view along line A-A' shown in FIG. 120A
  • FIG. 120C is a cross-sectional view along line B-B' shown in FIG 120A.
  • FIG. 121A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 121B is a cross-sectional view along line A-A' shown in FIG. 121A
  • FIG. 121C is a cross-sectional view along line B-B' shown in FIG 121A.
  • FIG. 122A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 122B is a cross-sectional view along line A-A' shown in FIG. 122A
  • FIG. 122C is a cross-sectional view along line B-B' shown in FIG 122A.
  • FIG. 123A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 123B is a cross-sectional view along line A-A' shown in FIG. 123A
  • FIG. 123C is a cross-sectional view along line B-B' shown in FIG 123A.
  • FIG. 124A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment
  • FIG. 124B is a cross-sectional view along line A-A' shown in FIG. 124A
  • FIG. 124C is a cross-sectional view along line B-B' shown in FIG 124A.
  • FIG. 125 is a circuit diagram showing a configuration of the semiconductor device according to the seventh embodiment.
  • FIG. 126A is a plan view showing a method for manufacturing a semiconductor device according to a first modification of the seventh embodiment; and FIG. 126B is a cross-sectional view along line A-A' shown in FIG 126A.
  • FIG. 127A is a plan view showing the method for manufacturing the semiconductor device according to the first modification of the seventh embodiment; and FIG. 127B is a cross-sectional view along line A-A' shown in FIG 127A.
  • FIG. 128A is a plan view showing the method for manufacturing the semiconductor device according to the first modification of the seventh embodiment; and FIG. 128B is a cross-sectional view along line A-A' shown in FIG 128A.
  • FIGS. 129A to 129C are drawings showing a method for manufacturing a semiconductor device according to a second modification of the seventh embodiment
  • FIG. 129A is a plan view of a Zener diode chip as viewed from an upper surface side
  • FIG. 129B is a cross-sectional view
  • FIG. 129C is a plan view as viewed from a lower surface side.
  • FIGS. 130 to 139 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second modification of the seventh embodiment.
  • FIG. 140A is a plan view showing the method for manufacturing the semiconductor device according to the second modification of the seventh embodiment; and FIG. 140B is a cross-sectional view along line A-A' shown in FIG 140A.
  • FIG. 141A is a plan view showing a method for manufacturing a semiconductor device according to an eighth embodiment; and FIG. 141B is a cross-sectional view along line A-A' shown in FIG 141A.
  • FIG. 142A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 142B is a cross-sectional view along line A-A' shown in FIG 142A.
  • FIG. 143A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 143B is a cross-sectional view along line A-A' shown in FIG 143A.
  • FIG. 144A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 144B is a cross-sectional view along line A-A' shown in FIG 144A.
  • FIG. 145A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 145B is a cross-sectional view along line A-A' shown in FIG 145A.
  • FIG. 146A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 146B is a cross-sectional view along line A-A' shown in FIG 146A.
  • FIG. 147A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 147B is a cross-sectional view along line A-A' shown in FIG 147A.
  • FIG. 148A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 148B is a cross-sectional view along line A-A' shown in FIG 148A.
  • FIGS. 149A to 149C are drawings showing the method for manufacturing the semiconductor device according to the eighth embodiment.
  • FIG. 149A is a plan view of an LED chip as viewed from a crystal growth substrate side
  • FIG. 149B is a cross-sectional view along line A-A' shown in FIG. 149A
  • FIG. 149C is a plan view as viewed from an LED layer side.
  • FIG. 150 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment.
  • FIG. 151A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 151B is a cross-sectional view along line A-A' shown in FIG 151A.
  • FIGS. 152 to 155 are cross-sectional views showing the method for manufacturing the semiconductor device according to the eighth embodiment.
  • FIG. 156A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 156B is a cross-sectional view along line A-A' shown in FIG 156A.
  • FIG. 157A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 157B is a cross-sectional view along line A-A' shown in FIG 157A.
  • FIG. 158A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 158B is a cross-sectional view along line A-A' shown in FIG. 158A
  • FIG. 158C is a cross-sectional view along line B-B' shown in FIG 158A.
  • FIG. 159A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 159B is a cross-sectional view along line A-A' shown in FIG. 159A
  • FIG. 159C is a cross-sectional view along line B-B' shown in FIG 159A.
  • FIG. 160A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 160B is a cross-sectional view along line A-A' shown in FIG. 160A
  • FIG. 160C is a cross-sectional view along line B-B' shown in FIG 160A.
  • FIG. 161A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 161B is a cross-sectional view along line A-A' shown in FIG. 161A
  • FIG. 161C is a cross-sectional view along line B-B' shown in FIG 161A.
  • FIG. 162A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 162B is a cross-sectional view along line A-A' shown in FIG. 162A
  • FIG. 162C is a cross-sectional view along line B-B' shown in FIG 162A.
  • FIG. 163A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 163B is a cross-sectional view along line A-A' shown in FIG. 163A
  • FIG. 163C is a cross-sectional view along line B-B' shown in FIG 163A.
  • FIG. 164A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 164B is a cross-sectional view along line A-A' shown in FIG. 164A
  • FIG. 164C is a cross-sectional view along line B-B' shown in FIG 164A.
  • FIG. 165A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 165B is a cross-sectional view along line A-A' shown in FIG. 165A
  • FIG. 165C is a cross-sectional view along line B-B' shown in FIG 165A.
  • FIG. 166A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 166B is a cross-sectional view along line A-A' shown in FIG. 166A
  • FIG. 166C is a cross-sectional view along line B-B' shown in FIG 166A.
  • FIG. 167A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 167B is a cross-sectional view along line A-A' shown in FIG. 167A
  • FIG. 167C is a cross-sectional view along line B-B' shown in FIG 167A.
  • FIG. 168A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 168B is a cross-sectional view along line A-A' shown in FIG. 168A
  • FIG. 168C is a cross-sectional view along line B-B' shown in FIG 168A.
  • FIG. 169A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 169B is a cross-sectional view along line A-A' shown in FIG. 169A
  • FIG. 169C is a cross-sectional view along line B-B' shown in FIG 169A.
  • FIG. 170A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 170B is a cross-sectional view along line A-A' shown in FIG. 170A
  • FIG. 170C is a cross-sectional view along line B-B' shown in FIG 170A.
  • FIG. 171A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 171B is a cross-sectional view along line A-A' shown in FIG. 171A
  • FIG. 171C is a cross-sectional view along line B-B' shown in FIG 171A.
  • FIG. 172A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 172B is a cross-sectional view along line A-A' shown in FIG. 172A
  • FIG. 172C is a cross-sectional view along line B-B' shown in FIG 172A.
  • FIG. 173A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment
  • FIG. 173B is a cross-sectional view along line A-A' shown in FIG. 173A
  • FIG. 173C is a cross-sectional view along line B-B' shown in FIG 173A.
  • FIG. 174 is a circuit diagram showing the semiconductor device according to the eighth embodiment.
  • a method for manufacturing a semiconductor device includes making a plurality of intermediate structural bodies.
  • Each of the plurality of intermediate structural bodies includes an electrode and a semiconductor member.
  • the electrode is formed on the semiconductor member.
  • a configuration of an upper portion and a configuration of a lower portion are different from each other as viewed from above for each of the plurality of intermediate structural bodies.
  • the method includes arranging the plurality of intermediate structural bodies to be separated from each other by causing one portion selected from the upper portion and the lower portion for each of the intermediate structural bodies to engage with a recess multiply made in an upper surface of a tray by causing the plurality of intermediate structural bodies to tumble on the tray.
  • the one portion is configured to engage with the recess.
  • the other portion selected from the upper portion and the lower portion is configured not to engage with the recess.
  • the method includes forming an external electrode connected to the electrode. A portion of the external electrode extends outside the intermediate structural body as viewed from above.
  • a semiconductor device includes a semiconductor member having a configuration having ?-fold rotational symmetry (/? being an integer not less than 2), an electrode provided on the semiconductor member and disposed with n-fold rotational symmetry, and an external electrode connected to the electrode with a portion of the external electrode extending outside the semiconductor member as viewed from above.
  • multiple intermediate structural bodies are made by dividing a substrate after forming electrodes, etc., on the substrate.
  • Semiconductor members are included in the intermediate structural bodies.
  • these intermediate structural bodies are fed onto a tray having an upper surface in which multiple recesses are made; and these intermediate structural bodies are caused to engage with the recesses by causing the intermediate structural bodies to tumble by causing the tray to vibrate.
  • the multiple intermediate structural bodies are arranged on the tray to be separated from each other.
  • an external electrode is formed collectively on the intermediate structural bodies in the arranged state; and multiple semiconductor devices are manufactured by performing singulation.
  • combinations of the configurations of the recesses and the configurations of the intermediate structural bodies are contrived to fix the intermediate structural bodies in appropriate orientations when arranging the multiple intermediate structural bodies on the tray.
  • inversion of front and back is prevented by making the front and back of the intermediate structural body asymmetric; and discrepancies are prevented from occurring even when the intermediate structural body rotates by making the configuration of the intermediate structural body rotationally symmetric and by making the dispositions of the electrodes rotationally symmetric.
  • the semiconductor device according to the embodiment is, for example, an LED (light emitting diode) chip.
  • the semiconductor member is an LED layer.
  • FIG. 1A to FIG. 22 are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
  • a crystal growth substrate 10 (hereinbelow, also called simply the "substrate 10") is prepared as shown in FIGS. 1A and IB.
  • the substrate 10 is, for example, a silicon wafer, a sapphire wafer, or a silicon carbide (a SiC) wafer, and favorably, a silicon wafer.
  • FIGS. 1A and IB show a portion of a wafer having a disc configuration as the substrate 10. This is similar also for the other drawings described below.
  • MO-CVD Metal Organic Chemical Vapor Deposition
  • the LED layer 11 is divided into multiple portions by, for example, selectively removing the LED layer 11 by RIE (Reactive Ion Etching). In other words, high-mesa patterning of the LED layer 11 is performed.
  • RIE Reactive Ion Etching
  • the p-type GaN layer l i b is removed from the corners of the divided LED layer 11 by, for example, p-mesa patterning by RIE. Thereby, the n-type GaN layer 11a is exposed at the upper surface at the corners of the LED layer 11. On the other hand, the p-type GaN layer l i b is exposed at the upper surface at the cross-shaped portion other than the corners of the LED layer 11. Then, as shown in FIGS.
  • n-electrodes 12a are formed on the n-type GaN layer 11a; and a p-electrode 12b is formed on the p-type GaN layer l ib.
  • the dispositions of the n-electrodes 12a and the p-electrode 12b have 4-fold rotational symmetry because the n-electrodes 12a are disposed at the corners of four locations of the square LED layer 11 and the p-electrode 12b is disposed in the region of the cross-shape other than the corners. Then, by forming a passivation film 13 in the region between the p-electrode 12b and the n-electrodes 12a on each of the LED layers 11, the active layer that is exposed at the side surface in the p-mesa patterning is covered.
  • the passivation film 13 is formed to cover the end portions of the n-electrodes 12a and the end portion of the p-electrode 12b.
  • the manufacturing of the example is performed in the order of high mesa, and then subsequently p-mesa, electrode formation, and passivation film, the order may be modified as necessary.
  • the high mesa may be last; and the passivation film may be formed prior to the electrode.
  • the p-mesa and/or passivation film formation may be performed between the p-electrode formation and the n-electrode formation. Further, annealing may be performed as necessary after the electrode formation.
  • a trench 14a is made in the upper portion of the substrate 10 from above using, for example, a diamond blade.
  • the trench 14a is made in a lattice configuration between the LED layers 11 to partition the substrate 10 every LED layer 11.
  • the trench 14a is made not to pierce the substrate 10.
  • the trench 14a may be made by RIE or laser patterning.
  • a trench 14b is made in the lower portion of the substrate 10 from below using, for example, a diamond blade.
  • the trench 14b may be made by wet processing, RIE, or laser patterning.
  • the trench 14b is made in a region including the region directly under the trench 14a to be wider than the trench 14a and to communicate with the trench 14a.
  • the substrate 10 is cut every LED layer 11 by the trench 14a and the trench 14b; and the multiple intermediate structural bodies 16 are made.
  • a lower portion 16b of the intermediate structural body 16 cut by the trench 14b is finer than an upper portion 16a of the intermediate structural body 16 cut by the trench 14a.
  • the outer edge of the lower portion 16b is positioned inside the outer edge of the upper portion 16a as viewed from above.
  • an arranging machine 100 is prepared as shown in FIG. 7.
  • a tray 102 that has an upper surface in which multiple recesses 101 are made, and a vibration unit 103 that vibrates the tray 102 are provided in the arranging machine 100.
  • the configuration of the tray 102 is a configuration corresponding to the exterior form of a wafer, the exterior form of a printed circuit board, or the exterior form of a liquid crystal panel.
  • the recess 101 is arranged in, for example, a matrix configuration.
  • the configuration of each of the recesses 101 is a rectangular parallelepiped configuration; and the size is such that the lower portion 16b of the intermediate structural body 16 engages but the upper portion 16a does not engage.
  • the multiple intermediate structural bodies 16 are fed onto the tray 102.
  • the vibration unit 103 causes the tray 102 to vibrate.
  • the intermediate structural bodies 16 tumble randomly on the tray 102.
  • the intermediate structural bodies 16 of which the lower portion 16b has engaged with the recess 101 do not tumble anymore and are stabilized in that position.
  • FIGS. 9A and 9B ultimately, all of the intermediate structural bodies 16 engage respectively with the recesses 101 ; and the positions are fixed.
  • the multiple intermediate structural bodies 16 are arranged periodically in a matrix configuration and separated from each other.
  • a porous chuck 105 is brought to a position above the tray 102 and lowered from that position. Thereby, the lower surface of the porous chuck 105 contacts the upper surfaces of the intermediate structural bodies 16. Then, the porous chuck 105 is lifted in the state in which the intermediate structural bodies 16 are held by suction. Thereby, the multiple intermediate structural bodies 16 are lifted collectively and removed from the tray 102.
  • An adhesive film may be used instead of the porous chuck 105.
  • the porous chuck 105 is moved to a position above an adhesive film 20 and lowered. Thereby, the lower surfaces of the intermediate structural bodies 16 contact and are bonded to the adhesive film 20. Subsequently, the porous chuck 105 releases the intermediate structural bodies 16; and the porous chuck 105 is lifted. Thereby, the multiple intermediate structural bodies 16 are transferred collectively from the porous chuck 105 to the adhesive film 20. At this time, the relative positional relationship of the multiple intermediate structural bodies 16 remains in the state of the arrangement on the tray 102.
  • the configuration of the adhesive film 20 is favorable for the configuration of the adhesive film 20 to be, for example, a configuration corresponding to the exterior form of a wafer having a large diameter, the exterior form of a printed circuit board, or the exterior form of a liquid crystal panel. Thereby, the subsequent processes can be implemented using existing equipment. Further, a support substrate such as a silicon wafer, etc., may be used instead of the adhesive film 20.
  • a resin film 21 is formed by coating a resin material on the adhesive film 20 by a method such as spin coating, printing, etc., to bury the intermediate structural bodies 16.
  • planarization of the upper surface of the resin film 21 is performed as necessary.
  • the upper portions of the upper portions 16a of the intermediate structural bodies 16 are exposed by etching the resin film 21 by wet processing, dry processing, etc.
  • an insulating film 22 is formed by, for example, CVD, sputtering, etc.
  • openings 22a and 22b are made by removing the portions of the insulating film 22 corresponding to the regions directly above the n-electrodes 12a and the portion of the insulating film 22 corresponding to the region directly above the p-electrode 12b.
  • a thin seed layer (not shown) is formed by depositing a metal on the entire surface by, for example, sputtering.
  • a resist pattern 23 is formed by forming a resist film on the entire surface and by patterning.
  • the resist pattern 23 has openings in the regions where plating is to be performed in a subsequent process.
  • the resist pattern 23 is formed to partition the region of each of the intermediate structural bodies 16 including the four n-electrodes 12a as one continuous region 23a and partition the region of each of the intermediate structural bodies 16 including the one p-electrode 12b as one continuous region 23b. More specifically, the region 23a is set to be substantially C-shaped; and the region 23b is set to be substantially T-shaped.
  • the insulating film 22 is not shown in FIG. 14A.
  • a seed layer of a metal such as, for example, copper (Cu), etc.
  • a metal such as, for example, copper (Cu), etc.
  • Cu copper
  • a copper film 24 is formed in the regions 23a and 23b where the resist pattern 23 is not provided.
  • a resist pattern 25 is formed by forming a resist film on the entire surface and by patterning.
  • the resist pattern 25 is formed to partition one I-shaped region 25a in a portion of the region 23a and partition one T-shaped region 25b in a portion of the region 23b.
  • a metal such as copper, etc., is electroplated. Thereby, copper is plated and a copper film 26 is formed in the regions 25a and 25b where the resist pattern 25 is not provided.
  • the resist patterns 25 and 23 are removed by wet processing, ashing, etc.
  • the seed layer (not shown) is removed by performing wet processing.
  • an n-pillar 27a and a p-pillar 27b are formed of the stacked body of the copper films 24 and 26.
  • the n-pillar 27a is connected to the n-electrodes 12a; and the p-pillar 27b is connected to the p-electrode 12b.
  • a portion of the n-pillar 27a and a portion of the p-pillar 27b extend outside the intermediate structural body 16 as viewed from above.
  • a sealing resin film 28 is formed to cover the n-pillars 27a and the p-pillars 27b by coating a resin material such as, for example, an epoxy resin, etc., on the entire surface by, for example, printing or molding.
  • the removal method an appropriate method can be selected to match the material properties of the adhesive film 20.
  • the peeling from the resin film 21 may be performed by heating or by using a solvent to dissolve a portion of the adhesive film 20.
  • the adhesive film 20 may be removed by wet processing or dry processing. Further, mechanical polishing may be performed in the case where a hard support substrate is used instead of the adhesive film 20. The lower surfaces of the substrates 10 of the intermediate structural bodies 16 are exposed by removing the adhesive film 20.
  • the resin film 21 is removed as shown in FIG. 19B.
  • an appropriate method such as a method using a solvent, wet processing, dry processing, etc., can be selected.
  • the insulating film 22, the entire lower portions 16b of the intermediate structural bodies 16, and the lower portions of the upper portions 16a of the intermediate structural bodies 16 are exposed.
  • the crystal growth substrate 10 is removed from the intermediate structural bodies 16. Thereby, the LED layers 11 are exposed.
  • the substrate 10 can be removed by wet processing or dry processing.
  • the substrate 10 is formed of sapphire or SiC, removal is not always necessary because of the transparent properties.
  • a micro unevenness (not shown) is formed in the exposed surfaces of the LED layers 11 by, for example, performing surface roughening using a chemical liquid.
  • a fluorescer film 29 is formed to cover the exposed surfaces of the LED layers 11 by, for example, printing.
  • a fluorescer (not shown) is dispersed in a transparent or semi-transparent resin material.
  • the upper surfaces of the n-pillars 27a and the upper surfaces of the p-pillars 27b are exposed by, for example, polishing the upper surface of the sealing resin film 28 by a mechanical unit.
  • FIGS. 22A and 22B dicing of the fluorescer film 29, the insulating film 22, and the sealing resin film 28 is performed using, for example, a diamond blade. Thereby, the multiple semiconductor devices 1 are manufactured.
  • the fluorescer film 29 is provided; and the LED layer 11 is provided as a semiconductor member on the fluorescer film 29.
  • the n-type GaN layer 11a, the active layer (not shown), and the p-type GaN layer lib are stacked in this order in the LED layer 11.
  • the configuration of the LED layer 11 is a square as viewed from above. At the corners of the LED layer 11, the p-type GaN layer l ib is removed; and the n-type GaN layer 11a is exposed at the upper surface.
  • n-electrodes 12a that are connected to the n-type GaN layer 11a and one cross-shaped p-electrode 12b that is connected to the p-type GaN layer l ib are provided on the LED layer 11.
  • the dispositions of the n-electrodes 12a and the p-electrode 12b have 4-fold rotational symmetry as viewed from above.
  • the passivation film 13 is provided between the p-electrode 12b and the n-electrodes 12a.
  • the insulating film 22 is provided to cover the fluorescer film 29, the LED layer 11, the n-electrodes 12a, the p-electrode 12b, and the passivation film 13.
  • the n-pillar 27a and the p-pillar 27b are provided on the insulating film 22.
  • the n-pillar 27a is connected to the n-electrodes 12a via the opening 22a of the insulating film 22; and the p-pillar 27b is connected to the p-electrode 12b via the opening 22b of the insulating film 22.
  • a portion of the n-pillar 27a and a portion of the p-pillar 27b extend outside the LED layer 11 as viewed from above.
  • the sealing resin film 28 is provided on the insulating film 22 to fill around the n-pillar 27a and the p-pillar 27b.
  • the upper surface of the n-pillar 27a and the upper surface of the p-pillar 27b are exposed at the upper surface of the sealing resin film 28.
  • the n-pillar 27a and the p-pillar 27b function as external electrodes.
  • the intermediate structural bodies 16 are fed onto the tray 102 of the arranging machine 100; and the intermediate structural bodies 16 are caused to tumble on the tray 102 and engage with the recesses 101 by the vibration unit 103 causing the tray 102 to vibrate.
  • the multiple intermediate structural bodies 16 can be aligned with high precision and arranged in a matrix configuration in a mutually-separated state.
  • fine structural bodies can be formed collectively on the multiple intermediate structural bodies 16.
  • the n-pillar 27a and the p-pillar 27b that extend outside the LED layer 11 are formed; and the multiple semiconductor devices 1 having exterior forms larger than the exterior forms of the LED layers 11 can be manufactured collectively.
  • the heat that is generated can be dissipated efficiently from the LED layer 11.
  • the heat dissipation also can be increased when the multiple semiconductor devices 1 are mounted on a mounting substrate because the spacing between the LED layers 11 increases. Further, by forming the semiconductor device 1 to be larger than the LED layer 11, even in the case where the LED layer 11 is downscaled, good handling can be maintained without the handling of the semiconductor device 1 becoming difficult. Further, because the fluorescer film 29 can be provided in a region wider than the LED layer 11, it is easy to, for example, adjust the light distribution properties using a lens, etc. Thus, according to the embodiment, a semiconductor device 1 having high heat dissipation, easy handling, and high extensibility can be manufactured inexpensively.
  • the intermediate structural body 16 in the intermediate structural body 16, the configuration of the upper portion 16a and the configuration of the lower portion 16b are different from each other; and the lower portion 16b is finer than the upper portion 16a.
  • the recess 101 that is made in the tray 102 of the arranging machine 100 has a configuration with which the lower portion 16b of the intermediate structural body 16 engages but with which the upper portion 16a of the intermediate structural body 16 does not engage.
  • the lower portions 16b always engage with the recesses 101 ; and the intermediate structural bodies 16 are fixed in an orientation in which the LED layers 11 face upward.
  • the intermediate structural bodies 16 can be prevented from flipping; and all of the intermediate structural bodies 16 can be arranged in a state in which the LED layers 11 face upward.
  • the configuration of the intermediate structural body 16 has 4-fold rotational symmetry (90-degree symmetry) as viewed from above. Therefore, when the lower portion 16b of the intermediate structural body 16 engages with the recess 101, the intermediate structural body 16 can have four orientations in the plane.
  • the dispositions of the n-electrodes 12a and the p-electrode 12b also have 4-fold rotational symmetry. Therefore, the positional relationships of the n-electrodes 12a and the p-electrode 12b are equivalent no matter which orientation of the four orientations the intermediate structural body 16 has. Accordingly, it is unnecessary to consider the orientation of the intermediate structural body 16 in the plane.
  • the multiple intermediate structural bodies 16 can be arranged in the appropriate orientation on the tray 102. Thereby, repair work to rearrange intermediate structural bodies 16 disposed at inappropriate orientations becomes unnecessary; and after the arrangement, the transition to the next process can be performed immediately. As a result, the manufacturing cost of the semiconductor device 1 can be reduced even further.
  • the configuration of the adhesive film 20 can be any configuration because the arrangement and processing of the multiple intermediate structural bodies 16 can be performed inside any region.
  • the exterior form of the adhesive film 20 is made to match the exterior form of a wafer, the exterior form of a printed circuit board, or the exterior form of a liquid crystal panel, subsequent processes can be implemented using the existing manufacturing line of a semiconductor device, manufacturing line of a printed circuit board, or manufacturing line of a liquid crystal panel. Therefore, the semiconductor device 1 can be manufactured inexpensively and efficiently. Modifications of the first embodiment will now be described.
  • both the configuration of the intermediate structural body 16 and the dispositions of the n-electrodes 12a and the p-electrode 12b are made to have 4-fold rotational symmetry.
  • the dispositions of the electrodes are equivalent; and the external electrodes, i.e., the n-piilar 27a and the p-pillar 27b, can be formed collectively.
  • the configuration of the intermediate structural body 16 and the electrode dispositions are not limited to 4-fold rotational symmetry; and it is sufficient to have /7-fold rotational symmetry, where n is an integer not less than 2.
  • the types of the electrodes are not limited to the two types.
  • first to fourth modifications of the first embodiment described below examples are described in which the symmetry and number of types of the electrodes are different. Also, although an example is illustrated in the first embodiment in which the configuration of the intermediate structural body 16 is made to be front-and-back asymmetric by forming the two types of trenches 14a and 14b in the substrate 10, the method for making the front-and-back asymmetry is not limited thereto. An example is described in a fifth modification of the first embodiment in which the intermediate structural bodies are front-and-back asymmetric by using a bump. Further, examples are described in sixth to eighth modifications of the first embodiment in which a conductive film for electrostatic countermeasures is formed in the outer surface of the intermediate structural body.
  • the semiconductor device according to the modification is, for example, a low pin count IC (Integrated Circuit) chip.
  • FIG. 23 is a plan view showing the intermediate structural body of the modification.
  • the configuration of an intermediate structural body 36a of the modification is a square as viewed from above and accordingly has 4-fold rotational symmetry (90-degree symmetry).
  • four sets of a set made of three types of electrodes 32a, 32b, and 32c are provided in the intermediate structural body 36a.
  • One of each of the electrodes 32a, 32b, and 32c belonging to each set are arranged in one column along each side of the intermediate structural body 36a. Thereby, the electrodes 32a to 32c are disposed with 4-fold rotational symmetry.
  • the intermediate structural body 36a may have four orientations when engaging with the recess of the tray, the positional relationships between the electrodes are equivalent for any orientation. Therefore, the external electrodes, etc., can be formed collectively for multiple intermediate structural bodies 36a. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above.
  • the semiconductor device according to the modification also is, for example, a low pin count IC chip.
  • FIG. 24 is a plan view showing the intermediate structural body of the modification.
  • the configuration of the intermediate structural body 36b of the modification is a rectangle as viewed from above and accordingly has 2-fold rotational symmetry (180-degree symmetry).
  • two sets of a set made of five types of electrodes 32a to 32e are provided in the intermediate structural body 36b.
  • One of each of the electrodes 32a to 32e belonging to each set are arranged in an L-shaped configuration along two mutually-adjacent sides of the intermediate structural body 36b. Thereby, the electrodes 32a to 32e are disposed with 2-fold rotational symmetry. Therefore, although the intermediate structural body 36b may have two orientations when engaging with the recess of the tray, the positional relationships between the electrodes are equivalent regardless of the orientation of the fixation. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above.
  • the semiconductor device according to the modification also is, for example, a low pin count IC chip.
  • FIG. 25 is a plan view showing the intermediate structural body of the modification.
  • the configuration of the intermediate structural body 36c of the modification is a rectangle as viewed from above and accordingly has 2-fold rotational symmetry (180-degree symmetry).
  • two sets of a set made of six types of electrodes 32a to 32f are provided in the intermediate structural body 36c.
  • One of each of the electrodes 32a to 32f belonging to each set are arranged on two sides of the center line of the intermediate structural body 36c extending in the longitudinal direction in one column each along the center line.
  • the arrangement direction of the electrodes inside each set is reversed between the two sets.
  • the electrodes 32a to 32f are disposed with 2-fold rotational symmetry. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above.
  • FIG. 26A is a plan view showing the intermediate structural body of the modification
  • FIG. 26B is a cross-sectional view along line A-A' shown in FIG. 26A
  • FIG. 26C is a perspective view as viewed from the lower side.
  • the configuration of the intermediate structural body 36d of the modification is an equilateral triangle as viewed from above.
  • the lower portion of the intermediate structural body 36d is smaller than the upper portion of the intermediate structural body 36d. Therefore, the configuration of the intermediate structural body 36d is front-and-back asymmetric and has 3-fold rotational symmetry.
  • the configuration of the recess (not shown) made in the upper surface of the tray of the arranging machine is an equilateral triangular prism having a size such that the lower portion of the intermediate structural body 36d engages but the upper portion of the intermediate structural body 36d does not engage. As shown in FIG.
  • the widths of the p-type GaN layer lib and the p-electrodes 12b are narrower than the width of the other portion, these can be ignored regarding the engagement with the recess because the thicknesses of the p-type GaN layer l ib and the p-electrodes 12b are exceedingly thin compared to the thickness of the crystal growth substrate 10.
  • the n-electrodes 12a are provided on the upper surface of the intermediate structural body 36d at each of the three equilateral triangle corners. Also, one hexagonal p-electrode 12b is provided in the region of the upper surface of the intermediate structural body 36d where the n-electrodes 12a are not provided. Therefore, in the intermediate structural body 36d, the dispositions of the n-electrodes 12a and the p-electrode 12b have 3-fold rotational symmetry.
  • the intermediate structural body 36d does not flip when being fixed due to the engagement with the recess of the tray because the configuration of the intermediate structural body 36d is front-and-back asymmetric.
  • the positional relationships of the electrodes are equivalent for any orientation of the three orientations in which the intermediate structural body 36d may engage with the recess because the configuration of the intermediate structural body 36d and the dispositions of the electrodes both have 3-fold rotational symmetry. Therefore, the external electrodes, etc., are formed collectively in the state in which the multiple intermediate structural bodies 36d are arranged periodically and separated from each other. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above.
  • FIG. 27A is a cross-sectional view showing the intermediate structural body of the modification
  • FIG. 27B is a perspective view showing the intermediate structural body and the recess
  • FIG. 27C is a perspective view showing the state in which the intermediate structural body engages with the recess.
  • the semiconductor device according to the modification is a Zener diode chip.
  • an electrode 32 is formed on a semiconductor substrate 30; and a bump 33 is bonded onto the upper surface of the electrode 32.
  • a Zener diode is formed in the semiconductor substrate 30 as the semiconductor member; and electrodes are connected to the upper surface and lower surface of the Zener diode.
  • the configuration of the intermediate structural body 36e is a square as viewed from above. Also, the electrodes can be disposed with point symmetry because it is sufficient to provide one on each of the front and back surfaces of the semiconductor substrate 30.
  • multiple recesses 111 are made in the upper surface of a tray 112 of the arranging machine. The configurations of the recesses 111 are rectangular parallelepipeds.
  • the intermediate structural body 36e is engageable with the recess 111 when the orientation of the intermediate structural body 36e is such that the bump 33 is positioned on the upper side.
  • the bump 33 becomes an obstruction; and the intermediate structural body 36e cannot engage with the recess il l. Therefore, the intermediate structural body 36e always is fixed by engaging with the recess 111 in the orientation in which the bump 33 faces upward and is not fixed when flipped.
  • the intermediate structural body 36e may have four orientations because the configuration of the intermediate structural body 36e has 4-fold rotational symmetry, the positional relationships of the electrodes are equivalent regardless of the orientation because the dispositions of the electrodes are point-symmetric. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above. (Sixth modification of first embodiment)
  • FIGS. 28A to 28D are cross-sectional views showing the method for manufacturing the semiconductor device according to the modification.
  • the trench 14b is made by performing wide dicing from the backside, i.e., the crystal growth substrate 10 side.
  • the trench 14a is made in the bottom surface of the trench 14b by performing narrow dicing in the interior of the trench 14b.
  • the trench 14a is finer than the trench 14b and pierces the substrate 10. Thereby, the substrate 10 is cut apart by the trench 14b and the trench 14a every LED layer 11 ; and the multiple intermediate structural bodies 16 are made.
  • a conductive film 38 is formed on the lower surfaces of the intermediate structural bodies 16 and on the side surfaces of the intermediate structural bodies 16 from the substrate 10 side. It is favorable for the conductive film 38 to be a continuous film having good coverage. Also, it is favorable for the substrate 10 itself to be conductive and for the contact resistance between the substrate 10 and the conductive film 38 to be low.
  • the conductive film 38 may be formed by, for example, coating a conductive polymer or may be formed by sputtering a metal. Subsequently, the dicing tape 37 is removed.
  • the subsequent processes are similar to the processes shown in FIGS. 7 to FIG. 22.
  • the greater part of the conductive film 38 is removed with the crystal growth substrate 10 when removing the crystal growth substrate 10 in the process shown in FIG. 20A.
  • the conductive film 38 is formed on the lower surfaces of the intermediate structural bodies 16 and on the side surfaces of the intermediate structural bodies 16 in the process shown in FIG. 28D. Therefore, the intermediate structural bodies 16 can be prevented from scattering due to static electricity when the multiple intermediate structural bodies 16 are fed onto the arranging machine 100 in the process shown in FIG. 7.
  • the conductive film 38 is formed in the process shown in FIG. 28D, the side surfaces of each of the intermediate structural bodies 16 are exposed in the state in which all of the intermediate structural bodies 16 are arranged inside a wafer-shaped region using the dicing tape 37. Therefore, the formation of the conductive film 38 is easy; and the conductive film 38 can be formed in a wide region on the side surfaces of each of the intermediate structural bodies 16.
  • the conductive film 38 may be formed after making the trench 14b by the wide dicing and prior to making the trench 14a.
  • FIGS. 29A and 29B are cross-sectional views showing a method for manufacturing the semiconductor device according to the modification.
  • laser light 150 is irradiated into the interior of the trench 14b so that the focal point fits the bottom surface of the trench 14b.
  • a crystal alteration portion 39 is formed by the crystal of the silicon of which the substrate 10 is formed being altered by the energy of the laser light 150 at a portion of the crystal growth substrate 10 corresponding to the region directly under the trench 14b.
  • the dicing tape 37 is caused to expand (expand).
  • the substrate 10 is cleaved at the crystal alteration portion 39; and the substrate 10 is singulated into the multiple intermediate structural bodies 16.
  • the conductive film 38 (referring to FIG. 28C) is formed on the lower surfaces of the intermediate structural bodies 16 and on the side surfaces of the intermediate structural bodies 16.
  • the number of chips per production unit can be increased because the width of the laser light 150 can be finer. This effect is particularly large for an extremely small chip such as an LED chip.
  • FIGS. 30A and 30B are cross-sectional views showing a method for manufacturing the semiconductor device according to the modification.
  • the conductive film 38 is formed from the substrate 10 side. At this time, the conductive film 38 is formed on the lower surface of the substrate 10 and on the inner surface of the trench 14b.
  • the dicing tape 37 is caused to expand. Thereby, the substrate 10 is cleaved at the crystal alteration portion 39; and the multiple intermediate structural bodies 16 are singulated.
  • the formation of the conductive film 38 is easier compared to the seventh modification described above because the conductive film 38 is formed prior to singulating the substrate 10.
  • the conductive film 38 is formed after the substrate 10 is singulated, the conductive film 38 can be formed in a wider region of the side surfaces of the intermediate structural bodies 16.
  • the embodiment is an example in which inversion of front and back is prevented by making the front and back of the intermediate structural body asymmetric.
  • the upper portion of the intermediate structural body is made to be smaller than the lower portion of the intermediate structural body so that the upper portion engages with the recess of the tray.
  • the intermediate structural body is fixed with respect to the tray by engaging with the recess in a designated orientation by making the dispositions of the electrodes rotationally asymmetric and making the configuration of the intermediate structural body rotationally asymmetric.
  • FIG. 31A to FIG. 44B are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
  • FIGS. 31A and 31B multiple semiconductor circuits 41 are formed on a semiconductor substrate 40.
  • the semiconductor substrate 40 is, for example, a silicon wafer; and the semiconductor circuit 41 includes an interconnect layer formed on a semiconductor element such as a transistor, etc.
  • the semiconductor circuits 41 are arranged in a matrix configuration; and the configuration of each of the semiconductor circuits 41 is a rectangle. In the specification, squares also are included in " rectangle.”
  • electrodes 42 are formed on each of the semiconductor circuits 41.
  • ten electrodes 42 are formed and arranged in an annular configuration along the outer edge of the semiconductor circuit 41.
  • the roles of the ten electrodes that are formed on one semiconductor circuit 41 are different from each other. Accordingly, the dispositions of the electrodes 42 are rotationally asymmetric.
  • a bump 43 made of, for example, gold (Au) is formed on one of the electrodes 42 formed on each of the semiconductor circuits 41 using, for example, a stud bump bonder (not shown).
  • the bump 43 is provided on the electrode 42 that is formed at the same position on each of the semiconductor circuits 41.
  • the electrodes 42 are disposed at a position distal to the central axis C of the semiconductor circuit 41
  • the bump 43 is disposed at a position distal to the central axis C of the semiconductor circuit 41.
  • a trench 44a is made in the upper surface of the semiconductor substrate 40 using a relatively wide blade; and then, a trench 44b is made in the bottom surface of the trench 44a using a relatively fine blade.
  • the trench 44b is deeper and finer than the trench 44a.
  • the upper portion of the semiconductor substrate 40 is partitioned every semiconductor circuit 41 by the trenches 44a and 44b.
  • the back surface of the semiconductor substrate 40 is polished until the trench 44b is reached. Thereby, the semiconductor substrate 40 is singulated every semiconductor circuit 41 to become multiple intermediate structural bodies 46.
  • the order of the processes of making the trenches 44a and 44b shown in FIGS. 33A and 33B and the process of polishing the back surface shown in FIGS. 34A and 34B may be reversed.
  • the integrated circuit as the semiconductor member includes the semiconductor substrate 40 and the semiconductor circuit 41.
  • An upper portion 46a of the intermediate structural body 46 i.e., the portion on the side where the electrodes 42 are formed, is subdivided by the relatively wide trench 44a and therefore is relatively fine.
  • a lower portion 46b of the intermediate structural body 46 i.e., the portion on the semiconductor substrate 40 side, is subdivided by the relatively fine trench 44b and therefore is relatively wide. Accordingly, the configuration of the intermediate structural body 46 is front-and-back asymmetric. Also, the configuration of the intermediate structural body 46 is rotationally asymmetric because the bump 43 is provided at a position distal to the central axis C of the intermediate structural body 46.
  • each of the recesses 121 is a two-step configuration; and a lower portion 121b that has a rectangular parallelepiped configuration smaller than an upper portion 121a is made at one location at the bottom surface of the upper portion 121a having a rectangular parallelepiped configuration.
  • the upper portion 121a of the recess 121 has a configuration with which the portion of the upper portion 46a of the intermediate structural body 46 other than the bump 43 engages; and the lower portion 121b has a configuration in which the bump 43 is contained.
  • the lower portion 46b of the intermediate structural body 46 does not engage with the recess 121 because the lower portion 46b of the intermediate structural body 46 is larger than the upper portion 46a of the intermediate structural body 46.
  • the upper portion 46a of the intermediate structural body 46 engages with the recess 121.
  • the orientation of the intermediate structural body 46 is constrained to one orientation because it is necessary for the bump 43 to fit in the lower portion 121b.
  • an adhesive film 51 that is provided on the lower surface of a support substrate 50 is adhered over the intermediate structural bodies 46 from above and subsequently lifted. Thereby, the intermediate structural bodies 46 are removed from the recesses 121. Then, as shown in FIGS. 37A and 37B, up and down are inverted. Thereby, the multiple intermediate structural bodies 46 are transferred onto the support substrate 50 with the adhesive film 51 interposed while maintaining the positional relationship between the multiple intermediate structural bodies 46.
  • a resin film 52 is formed on the entire surface of the adhesive film 51 by, for example, coating.
  • the resin film 52 covers the intermediate structural body 46.
  • an insulating film 53 is formed by, for example, coating. Then, openings 53a are made by removing portions of the insulating film 53 corresponding to the regions directly above the electrodes 42. The electrodes 42 are exposed inside the openings 53a of the insulating film 53. Also, the bump 43 protrudes from the upper surface of the insulating film 53 via the opening 53a.
  • a thin seed layer 54 is formed by, for example, depositing a metal onto the entire surface by sputtering. Then, a resist film is formed on the entire surface; and a resist pattern (not shown) is formed by patterning.
  • the resist pattern has openings in regions where plating is to be performed in a subsequent process.
  • the seed layer 54 of a metal such as, for example, copper (Cu), etc., is electroplated as a plating contact line. At this time, copper is plated in the regions where the resist pattern is not provided.
  • the resist pattern is removed by wet processing, ashing, etc. Then, the portion of the seed layer 54 exposed at the no-copper-plating portion is removed by performing wet processing.
  • re-interconnect layers 55 made of, for example, copper are formed on the insulating film 53.
  • An interconnect portion 55a having an arm-like configuration and a pad portion 55b having a disc configuration are provided in each of the re-interconnect layers 55.
  • One end of each of the interconnect portions 55a is connected to each of the electrodes 42 via each of the openings 53a.
  • the electrode 42 to which the bump 43 is bonded is connected to the interconnect portion 55a via the bump 43.
  • the interconnect portion 55a and the electrode 42 are directly connected in a form in which the bump 43 is enveloped in the interior of the interconnect portion 55a.
  • at least a portion of the other end of the interconnect portion 55a and the entire pad portion 55b extend outside the intermediate structural body 46.
  • a solder resist 56 is formed by depositing an insulating material. Then, openings 56a are made by removing the regions of the solder resist 56 directly above the pad portions 55b by exposing and developing the solder resist 56.
  • the back surface of the support substrate 50 is made thin as necessary by polishing.
  • the support substrate 50 may be peeled.
  • BGA All Grid
  • Array balls 57 are formed on the pad portions 55b of the re-interconnect layers 55.
  • the BGA balls 57 protrude from the upper surface of the solder resist 56 via the openings 56a.
  • singulation is performed every semiconductor substrate 40 by dicing the support substrate 50, the adhesive film 51, the resin film 52, the insulating film 53, and the solder resist 56. Thereby, the multiple semiconductor devices 2 are manufactured.
  • the configuration of the intermediate structural body 46 is a rectangle; and the upper portion 46a is smaller than the lower portion 46b.
  • the semiconductor circuit 41 is provided on the semiconductor substrate 40; a plurality, e.g., ten, electrodes 42 are provided on the semiconductor circuit 41; and the bump 43 made of, for example, gold is provided on one of the electrodes 42.
  • the resin film 52 is provided around the intermediate structural body 46; and the insulating film 53 is provided on the resin film 52 and on the intermediate structural body 46.
  • the number of re-interconnect layers 55 provided on the insulating film 53 substantially corresponds to the electrodes 42.
  • Each of the re-interconnect layers 55 is made of, for example, copper; and the interconnect portion 55a and the pad portion 55b are formed as one body. When viewed from above, a portion of the interconnect portion 55a and the entire pad portion 55b extend outside the semiconductor substrate 40 and the semiconductor circuit 41.
  • the interconnect portions 55a are connected to the electrodes 42 via the openings 53a of the insulating film 53; and the pad portions 55b are connected to the BGA balls 57 provided on the pad portions 55b.
  • the solder resist 56 that is insulative is provided on the insulating film 53 to cover the entire re-interconnect layers 55 and the lower portions of the BGA balls 57.
  • the semiconductor device 2 has high heat dissipation and easy handling because the re-interconnect layers 55 extend outside the region directly above the semiconductor substrate 40, and the BGA balls 57 can be disposed outside the region directly above the semiconductor substrate 40. Also, in the case where the semiconductor device 2 is a versatile device, the package size can be standardized. Further, even in the case where the number of electrodes 42 and the number of BGA balls 57 corresponding to the electrodes 42 are high, the size and pitch necessary for the substrate mounting can be ensured because the BGA balls 57 can be disposed in a region greater than the size of the semiconductor device 2.
  • the multiple intermediate structural bodies 46 can be arranged easily in a matrix configuration and separated from each other in one orientation by making the configuration of the intermediate structural body 46 front-and-back asymmetric and rotationally asymmetric and making the configuration of the recess 121 of the tray 122 to be a configuration with which the upper portion 46a of the intermediate structural body 46 engages and the lower portion 46b of the intermediate structural body 46 does not engage.
  • the multiple semiconductor devices 2 can be manufactured collectively; and the manufacturing cost can be reduced. Otherwise, the effects of the embodiment are similar to those of the first embodiment described above.
  • the embodiment is an example in which the configuration of the intermediate structural body is rotationally asymmetric and mirror-image asymmetric. Further, the configuration of the recess of the tray also is a configuration that fits the intermediate structural body. Thereby, when the intermediate structural body engages with the recess of the tray, the orientation of the intermediate structural body is constrained to one orientation. In other words, the intermediate structural body is not flipped and is oriented in a designated direction.
  • FIG. 45 is a plan view showing the method for manufacturing the semiconductor device according to the embodiment.
  • FIG. 45 shows a process in which multiple intermediate structural bodies 61 are singulated.
  • the configuration of the intermediate structural body 61 is a trapezoid that is not an isosceles trapezoid. Therefore, the configuration of the intermediate structural body 61 is rotationally asymmetric and mirror-image asymmetric. It is difficult to singulate the intermediate structural body 61 by only blade dicing, but it is sufficient to use, for example, laser patterning or RIE. Otherwise, the configuration, the manufacturing method, and the effects of the embodiment are similar to those of the first embodiment described above.
  • FIG. 46 is a plan view showing the method for manufacturing the semiconductor device according to the modification.
  • the configuration of an intermediate structural body 62 is made to be a pentagonal prism configuration formed of a rectangular parallelepiped having a so-called chamfer. This also makes the configuration of the intermediate structural body 62 rotationally asymmetric and mirror-image asymmetric. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the third embodiment described above. (Fourth embodiment)
  • the embodiment is an example in which two intermediate structural bodies selected from the intermediate structural bodies described in the first to third embodiments or modifications of the first to third embodiments described above are provided together in one package.
  • two types of recesses are made in the tray of the arranging machine; only a first intermediate structural body engages with a first recess; a second intermediate structural body is made not to engage with the first recess; only the second intermediate structural body engages with a second recess; and the first intermediate structural body is made not to engage with the second recess.
  • FIG. 47 to FIG. 58 are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
  • the embodiment is an example in which the intermediate structural body 36d (referring to FIGS. 26A to 26C) shown in the fourth modification of the first embodiment and the intermediate structural body 36e (referring to FIGS. 27A to 27C) shown in the fifth modification of the first embodiment described above are provided together in one package.
  • the intermediate structural body 36d includes an LED layer as the semiconductor member; and the intermediate structural body 36e includes a Zener diode as the semiconductor member. Therefore, the semiconductor device 4 (referring to FIG. 58) that is manufactured in the embodiment is an LED package including a Zener diode.
  • the configuration of the intermediate structural body 36d and the dispositions of the electrodes have 3-fold rotational symmetry; and the configuration of the intermediate structural body 36e and the dispositions of the electrodes have 4-fold rotational symmetry.
  • an arranging machine is prepared in which a tray 132 is provided. Multiple regions corresponding to the semiconductor devices 4 to be manufactured are arranged in the tray 132 in a matrix configuration; and each of two types of recesses 131d and 131e are formed in each region. The positions of the recesses 131d and 131e inside each region are the same between the regions.
  • the configuration of the recess 131d is a triangular prism configuration and is a configuration with which the lower portion of the intermediate structural body 36d engages but the upper portion of the intermediate structural body 36d and the intermediate structural body 36e do not engage.
  • the configuration of the recess 131e is a rectangular parallelepiped configuration and is a configuration with which the lower portion of the intermediate structural body 36e, i.e., the portion on the side where the bump 33 is not provided, engages but the upper portion of the intermediate structural body 36e, i.e., the portion on the side where the bump 33 is provided, and the intermediate structural body 36d do not engage.
  • the multiple intermediate structural bodies 36d and the multiple intermediate structural bodies 36e are fed onto the tray 132. Then, the intermediate structural bodies 36d and 36e are caused to tumble on the tray 132 by the vibration unit (not shown) causing the tray 132 to vibrate.
  • the intermediate structural body 36d engages with the recess 131d of the tray 132; and the lower portion of the intermediate structural body 36e engages with the recess 131e.
  • the intermediate structural bodies 36d and 36e are fixed in a constant positional relationship to form a pair; and the pair is arranged in a matrix configuration.
  • the intermediate structural body 36d can have three orientations; but the positional relationships of the electrodes are equivalent for any of the orientations.
  • the configuration of the intermediate structural body 36e has 4-fold rotational symmetry, the intermediate structural body 36e can have four orientations; but the positional relationships of the electrodes are equivalent for any of the orientations.
  • FIGS. 49A and 49B the intermediate structural bodies 36d and 36e that are arranged on the tray 132 are picked up using, for example, a porous chuck (not shown), etc., and are transferred onto the support substrate 50.
  • the adhesive film 51 is adhered to the support substrate 50.
  • FIG. 49A the frames illustrated by the double dot-dash lines show the regions that become the semiconductor devices 4. This is similar for subsequent drawings as well.
  • the resin film 52 is formed on the entire surface of the adhesive film 51 to bury the intermediate structural bodies 36d and 36e. Then, the upper portions of the intermediate structural bodies 36d and the upper portions of the intermediate structural bodies 36e are exposed by etching the resin film 52. Then, the openings 53a are made in the regions directly above the n-electrodes 12a, the p-electrodes 12b, and the electrodes 32 by forming and patterning the insulating film 53.
  • a seed layer 64 made of, for example, copper is formed on the entire surface; a resist pattern (not shown) is formed on the seed layer 64; and copper is electroplated.
  • re-interconnect layers 65a and 65b are formed.
  • the re-interconnect layers 65a are connected to the n-electrodes 12a of the intermediate structural bodies 36d via the seed layer 64.
  • the re-interconnect layers 65b are connected to the p-electrodes 12b of the intermediate structural bodies 36d via the seed layer 64 and are connected to the electrodes 32 of the intermediate structural bodies 36e via the seed layer 64 and the bumps 33.
  • n-pillars 67a and p-pillars 67b are formed.
  • the n-pillars 67a are connected to the re-interconnect layers 65a.
  • the p-pillars 67b are connected to the re-interconnect layers 65b.
  • a sealing resin film 68 is formed on the entire surface to bury the n-pillars 67a and the p-pillars 67b.
  • FIGS. 52A and 52B front and back are inverted; and the support substrate 50 (referring to FIG. 51) and the adhesive film 51 (referring to FIG. 51) are removed. Then, the resin film 52 (referring to FIG. 51) is removed. Thereby, the crystal growth substrates 10 and the semiconductor substrates 30 are exposed from the insulating film 53.
  • a protective film 69 is formed to cover the exposed portions of the semiconductor substrates 30.
  • the LED layers 11 are exposed by removing the crystal growth substrates 10 (referring to FIG. 52B).
  • FIGS. 54A and 54B a fine unevenness is formed in the exposed surfaces of the LED layers 11 by performing frosting.
  • a transparent insulating film 71 is formed on the entire surface as shown in FIGS. 55A and 55B. Then, a photoresist (not shown) is formed; and after exposing and developing the photoresist, the transparent insulating film 71 is patterned by RIE; and anisotropic etching such as RIE, etc., is performed using the transparent insulating film 71 as a hard mask. Thereby, via holes 72a are made in portions of the portions of the transparent insulating film 71 and the insulating film 53 corresponding to regions directly above the re-interconnect layers 65a; and via holes 72b are made in portions of the portions of the transparent insulating film 71 and the protective film 69 corresponding to regions directly above the semiconductor substrates 30.
  • ESD Electrostatic Discharge protection interconnects 73 are formed in a region to link the interiors of the via holes 72a and 72b and the regions on the transparent insulating film 71 directly above the via holes 72a and 72b.
  • a fluorescer film 74 is formed on the entire surface of the transparent insulating film 71 to cover the ESD protection interconnects 73.
  • FIG. 59 is a drawing comparing the configurations of the LED layer and the semiconductor substrate of the embodiment.
  • the configuration of the semiconductor device 4 is a rectangular parallelepiped configuration.
  • the sealing resin film 68, the insulating film 53, the transparent insulating film 71, and the fluorescer film 74 are stacked in this order from the bottom upward in the semiconductor device 4.
  • the n-pillar 67a, the p-pillar 67b, the re-interconnect layer 65a, and the re-interconnect layer 65b are provided inside the sealing resin film 68.
  • the n-pillar 67a and the re-interconnect layer 65a are connected to each other and pierce the sealing resin film 68.
  • the p-pillar 67b and the re-interconnect layer 65b are connected to each other and pierce the sealing resin film 68.
  • the lower surface of the n-pillar 67a and the lower surface of the p-pillar 67b are exposed at the lower surface of the semiconductor device 4.
  • the seed layer 64 is provided on the upper surfaces of the re-interconnect layers 65a and 65b.
  • the LED layer 11 is provided inside the insulating film 53.
  • the p-type GaN layer l ib, the active layer (not shown), and the n-type GaN layer 11a are stacked in this order from the bottom upward in the LED layer 11; and frosting of the upper surface of the LED layer 11 is performed.
  • the n-type GaN layer 11a is connected to the re-interconnect layer 65a via the n-electrodes 12a; and the p-type GaN layer l ib is connected to the re-interconnect layer 65b via the p-electrode 12b.
  • the configuration of the LED layer 11 is an equilateral triangle; and the n-electrodes 12a are disposed at the corners of the equilateral triangle.
  • the bump 33 is provided inside the insulating film 53 and is connected to the re-interconnect layer 65b.
  • the semiconductor substrate 30 that is included in the Zener diode is provided inside the fluorescer film 74.
  • the lower surface of the semiconductor substrate 30 is connected to the re-interconnect layer 65b via the electrode 32 and the bump 33.
  • the configuration of the semiconductor substrate 30 is a square; and the dispositions of the electrode 32 are point-symmetric.
  • the end portions of the side surfaces and upper surface of the semiconductor substrate 30 are covered with the protective film 69.
  • the transparent insulating film 71 covers the upper surfaces of the insulating film 53, the LED layer 11, and the protective film 69.
  • the ESD protection interconnect 73 is provided between the transparent insulating film 71 and the fluorescer film 74.
  • One end of the ESD protection interconnect 73 is connected to the re-interconnect layer 65a through the via hole 72a made in the insulating film 53; and the other end of the ESD interconnect 73 is connected to the upper surface of the semiconductor substrate 30 through the via hole 72b made in the protective film 69.
  • an LED package including a Zener diode is realized in which the LED layer 11 and the semiconductor substrate 30 are connected in parallel between the n-pillar 67a and the p-pillar 67b.
  • LED layer 11 used as the first semiconductor member as viewed from above and the outer edge of the semiconductor substrate 30 used as the second semiconductor member as viewed from above are overlaid virtually, the outer edge of the LED layer 11 and the outer edge of the semiconductor substrate 30 always intersect. Further, as viewed from below, a portion of the n-pillar 67a extends outside the LED layer 11 ; and a portion of the p-pillar 67b extends outside the LED layer 11 and the semiconductor substrate 30.
  • the electrode dispositions and configuration of the intermediate structural body 36d including the LED layer 11 are made to have 3-fold rotational symmetry; and the electrode dispositions and configuration of the intermediate structural body 36e including the Zener diode are made to have 4-fold rotational symmetry.
  • the recess 131d of the tray 132 is made to have a configuration with which only the lower portion of the intermediate structural body 36d is engageable; and the recess 131e is made to have a configuration with which only the lower portion of the intermediate structural body 36e is engageable.
  • the intermediate structural bodies 36d and 36e can be arranged periodically in a state in which the intermediate structural bodies 64d and 64e are held with a mutually-separated constant positional relationship and equivalent electrode dispositions are realized.
  • the re-interconnect layers 65a and 65b, the n-pillars 67a, the p-pillars 67b, the ESD protection interconnects 73, etc. can be formed collectively; and the manufacturing cost can be reduced. Otherwise, the manufacturing method, the configuration, and the effects of the embodiment are similar to those of the first or second embodiments described above.
  • the embodiment is an example in which two intermediate structural bodies are provided together in one package similarly to the fourth embodiment described above but differs in that the configurations of the intermediate structural bodies as viewed from above both are rectangles. In this case, selective engagement with the recesses of the tray is possible by providing the lengths of each side of the rectangle with a prescribed relationship.
  • FIG. 60A is a plan view showing the method for manufacturing the semiconductor device according to the embodiment
  • FIG. 60B is a plan view showing the semiconductor device
  • FIG. 60C is a drawing showing the relationship between the configurations of the semiconductor members.
  • the two types of intermediate structural bodies 81a and 81b are fed onto a tray 142 of an arranging machine.
  • a semiconductor member 82a is provided in the entire upper surface of the intermediate structural body 81a; and a semiconductor member 82b is provided in the entire upper surface of the intermediate structural body 81b.
  • the configurations of the intermediate structural bodies 81a and 81b are front-and-back asymmetric.
  • the configurations of the intermediate structural bodies 81a and 81b both are rectangles; but the dimensions of the configurations are different from each other.
  • a long side La of the intermediate structural body 81a is longer than a long side Lb of the intermediate structural body 81b
  • a short side Wb of the intermediate structural body 81b is longer than a short side Wa of the intermediate structural body 81a, where the length of the long side of the intermediate structural body 81a is La, the length of the short side is Wa, the length of the long side of the intermediate structural body 81b is Lb, and the length of the short side is Wb.
  • the lengths La, Wa, Lb, and Wb satisfy the relationships of Formulas ( 1) and (2) recited below.
  • squares are included in "rectangle," in the case where the configuration of the intermediate structural body is a square, the length of the short side and the length of the long side of the square are equal to each other.
  • the intermediate structural bodies 81a and 81b can be arranged regularly. Then, the multiple semiconductor devices 5 are manufactured by forming external electrodes 83a and 83b collectively by a method similar to that of the fourth embodiment described above.
  • the semiconductor members 82a and 82b are provided to be separated from each other.
  • the semiconductor member 82a includes, for example, an integrated circuit; and the semiconductor member 82b includes, for example, a passive element.
  • the external electrodes 83a that are connected to the semiconductor member 82a are multiply provided; and the external electrodes 83b that are connected to the semiconductor member 82b are multiply provided.
  • a portion of each of the external electrodes 83a extends outside the semiconductor member 82a; and a portion of each of the external electrodes 83b extends outside the semiconductor member 82b.
  • the external electrodes 83a and 83b are exposed at the outer surface of the semiconductor device 5.
  • an electrode may be formed to provide a direct electrical connection between the semiconductor member 82a and the semiconductor member 82b.
  • a portion of the electrical connection unit may be provided to be exposed at the outer surface of the semiconductor device 5.
  • each of the recesses of the tray can have a designated intermediate structural body that is caused to selectively engage with the recess; and the arrangement can be performed in a state in which a prescribed positional relationship is realized for the multiple types of intermediate structural bodies.
  • FIGS. 61A to 61D are drawings comparing configurations of the intermediate structural bodies of the modification .
  • the number of types of intermediate structural bodies is m (m being an integer not less than 2) ; and all of the configurations of the intermediate structural bodies are rectangles as viewed from above. Also, Formulas (3) and (4) recited below are satisfied, where the length of the long side of the /th (/ being an integer not less than 1 and not more than (m-l)) intermediate structural body 86/ is L shadow- and the length of the short side of the intermediate structural body 86, is W,.
  • the embodiment is an example in which a reflective film is formed at the side of the LED layer.
  • FIG. 62A to FIG. 89B are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
  • the n-type GaN layer 11a, an active layer 11c, and the p-type GaN layer lib are epitaxially grown in this order on the crystal growth substrate 10 by, for example, MO-CVD. Thereby, the LED layer 11 is formed.
  • high-mesa patterning of the LED layer 11 is performed by, for example, RIE.
  • the LED layer 11 is divided into multiple portions arranged in a matrix configuration.
  • the configuration of each of the portions is a rectangle as viewed from above.
  • p-mesa patterning of the LED layers 11 is performed.
  • the n-type GaN layer 11a is exposed at the upper surface by removing the p-type GaN layer lib and the active layer; and the p-type GaN layer lib is exposed at the upper surface of the remaining cross-shaped portion.
  • the n-electrodes 12a are formed on the n-type GaN layer 11a; and the p-electrode 12b is formed on the p-type GaN layer l ib.
  • the passivation film 13 is formed on the entire surface by, for example, CVD. Then, the passivation film 13 is patterned by, for example, RIE to have openings on the n-electrodes 12a and on the p-electrode 12b.
  • a reflective metal layer 161 is formed on the entire surface by, for example, depositing a metal material having a high optical reflectance such as aluminum (Al), silver (Ag), platinum (Pt), etc., by PVD.
  • the reflective metal layer 161 is formed on the upper surfaces of the LED layers 11 and is connected to the n-electrodes 12a and the p-electrodes 12b via the openings of the passivation film 13. Also, the reflective metal layer 161 is formed on the side surfaces of the LED layers 11. Then, the reflective metal layer 161 is patterned to be divided into portions connected to the n-electrodes 12a and portions connected to the p-electrodes 12b.
  • the structural bodies that include the LED layers 11, etc., formed on the substrate 10 are adhered to the dicing tape 37.
  • the upper surfaces of the structural bodies, i.e., the reflective metal layer 161 are bonded to the dicing tape 37.
  • the dicing tape 37 and the structural bodies are inverted; and the trench 14b is made in a lattice configuration in the lower surface of the substrate 10, i.e., the surface on the side where the LED layers 11 are not formed, by using, for example, a diamond blade (not shown).
  • laser light e.g., YAG laser light
  • the focal point of the laser light is set to be positioned in the interior of the substrate 10.
  • a portion of the substrate 10 is modified to form a modified portion 162.
  • the crystal of the substrate 10 of the modified portion 162 degrades and becomes brittle.
  • an antistatic film 163 is formed on the entire surface.
  • a conductive film having good adhesion with the substrate 10 and a surface that does not oxidize easily is favorable; and, for example, a titanium (Ti)/titanium nitride (TiN) stacked film, a metal film such as a gold (Au) film or a platinum (Pt) film, or a conductive resin film can be used.
  • the metal film can be formed by, for example, PVD or plating; and the conductive resin film can be formed by, for example, spraying, etc.
  • the modified portion 162 may be formed by irradiating laser light after forming the antistatic film 163.
  • the dicing tape 37 is caused to expand (expand).
  • the modified portion 162 which is more brittle than the surroundings, fractures; and the substrate 10 is singulated every LED layer 11.
  • an intermediate structural body 164 is made every LED layer 11.
  • the LED layer 11 is provided on the substrate 10.
  • the n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer l ib are stacked in this order in the LED layer 11.
  • the upper surface is formed of the n-type GaN layer 11a at the corners of the LED layer 11 and is formed of the p-type GaN layer lib at the other portions.
  • the n-electrodes 12a are provided on the upper surface of the n-type GaN layer 11a; and the p-electrode 12b is provided on the upper surface Of the p-type GaN layer l ib.
  • the passivation film 13 is provided to cover the side surfaces and upper surface of the LED layer 11; and the reflective metal layer 161 is provided on the outer side of the passivation film 13.
  • the portion of the reflective metal layer 161 positioned in the region directly above the p-type GaN layer l ib is connected to the p-electrode 12b via the opening of the passivation film 13; and the portion of the reflective metal layer 161 positioned in the region directly above the n-type GaN layer 11a and at the sides of the LED layer 11 is connected to the n-electrodes 12a via the openings of the passivation film 13.
  • a rectangular parallelepiped protrusion is formed in the lower surface of the substrate 10.
  • the antistatic film 163 is provided on the lower surface of the substrate 10.
  • the protrusion of the substrate 10 and the antistatic film 163 provided on the lower surface of the protrusion and on the side surface of the protrusion are called a lower portion 164a of the intermediate structural body 164; and the other portions are called an upper portion 164b of the intermediate structural body 164.
  • the lower portion 164a is finer than the upper portion 164b.
  • a tray 166 of the arranging machine 100 (referring to FIG. 7) is prepared.
  • a recess 167 is made in the upper surface of the tray 166.
  • the recess 167 is arranged in a matrix configuration as viewed from above.
  • the recess 167 has a two-step configuration; and a lower portion 167b is formed in the lower surface central portion of an upper portion 167a.
  • the configurations of the upper portion 167a and the lower portion 167b are rectangular parallelepipeds.
  • the lower portion 167b of the recess 167 has a configuration with which the lower portion 164a of the intermediate structural body 164 engages but with which the upper portion 164b does not engage.
  • the size of the upper portion 167a of the recess 167 is such that the upper portion 164b of the intermediate structural body 164 engages. Then, the intermediate structural bodies 164 are fed onto the tray 166; and the tray 166 is caused to vibrate. Thereby, the intermediate structural bodies 164 tumble randomly on the tray 166.
  • the intermediate structural bodies 164 are fixed inside the recesses 167 and no longer tumble due to the lower portions 164a of the intermediate structural bodies 164 engaging with the lower portions 167b of the recesses 167 and the lower portions of the upper portions 164b of the intermediate structural bodies 164 engaging with the upper portions 167a of the recesses 167.
  • the multiple intermediate structural bodies 164 are arranged periodically in a matrix configuration and separated from each other. At this time, the vertical orientation of the intermediate structural bodies 164 is fixed.
  • the planar configuration of the intermediate structural body 164 has 2-fold rotational symmetry and can have two mutually-opposite orientations because the planar configuration is a rectangle; but problems do not occur because the electrode dispositions of the intermediate structural body 164 also have 2-fold rotational symmetry.
  • the intermediate structural bodies 164 are extracted from the recesses 167 of the tray 166 by moving the heat-resistant tape 169 in a direction away from the tray 166.
  • the p-mesa portions are buried inside the heat-resistant tape 169 because the stepped portions of the p-mesa portions of the intermediate structural bodies 164 are about several microns and the thickness of the heat-resistant tape 169 is about several millimeters.
  • a wafer support system in which an adhesive layer is formed on a support substrate may be used instead of the heat-resistant tape 169.
  • the intermediate structural bodies 164 are disposed on the heat-resistant tape 169 by inverting up and down.
  • a reinforcing insulating resin film 170 is formed on the heat-resistant tape 169 to bury the intermediate structural bodies 164 by, for example, coating or molding.
  • the reinforcing insulating resin film 170 favorably is a resin film that reflects light and can be, for example, a resin film into which titanium oxide is mixed.
  • the reinforcing insulating resin film 170 may be transparent.
  • the resin material favorably is a material that is transparent and has excellent lightfastness such as, for example, a silicone resin, an acrylic resin, etc., but may be an epoxy resin.
  • the heat-resistant tape 169 is peeled from the reinforcing insulating resin film 170.
  • the intermediate structural bodies 164 remain inside the reinforcing insulating resin film 170; and the p-mesa portions are exposed.
  • an insulating film 171 is formed on the entire surface of the reinforcing insulating resin film 170 to cover the exposed portions of the intermediate structural bodies 164; and openings are made to expose portions of the reflective metal layers 161.
  • the insulating film 171 may be an inorganic film or may be an organic film. In the case where the inorganic film is used as the insulating film 171, for example, the film formation is performed by PVD or CVD; and the patterning is performed by photolithography and RIE.
  • the film formation is performed by spin coating; if photosensitive, the patterning is performed by exposing and developing; and if non-photosensitive, the patterning is performed by developing by wet processing after photolithography or by forming a hard mask and performing RIE after photolithography.
  • a seed layer 172 is formed on the entire surface by, for example, PVD.
  • PVD a titanium (Ti)/copper (Cu) stacked film or an aluminum (AI)/copper (Cu) stacked film is formed by sputtering.
  • a thick film resist 173 is formed and patterned.
  • the thick film resist 173 is patterned into a lattice configuration and partitioned into regions where the n-electrodes 12a are exposed and regions where the p-electrodes 12b are exposed.
  • copper (Cu) is formed on the entire surface by electroplating.
  • a copper interconnect layer 174 is formed in the regions where the thick film resist 173 is not formed.
  • the copper interconnect layer 174 is partitioned by the thick film resist 173 because the upper portion of the thick film resist 173 protrudes from the upper surface of the copper interconnect layer 174.
  • each of the portions of the partitioned copper interconnect layer 174 is connected to the n-electrodes 12a or the p-electrode 12b via the seed layer 172.
  • a thick film resist 175 is formed on the copper interconnect layer 174 to cover the thick film resist 173; and patterning is performed.
  • copper pillars 176 are formed in the regions where the thick film resist 175 is not formed by forming copper (Cu) on the entire surface by electroplating.
  • the copper pillars 176 are connected to the copper interconnect layer 174.
  • the thick film resist 175 and the thick film resist 173 are removed by performing wet processing or ashing processing.
  • the seed layer 172 is removed by etching using the copper pillars 176 and the copper interconnect layer 174 as a mask.
  • the copper interconnect layer 174 and the copper pillar 176 that are connected to the n-electrodes 12a and the copper interconnect layer 174 and the copper pillar 176 that are connected to the p-electrode 12b are electrically isolated from each other.
  • a reinforcing insulating resin film 178 is formed on the reinforcing insulating resin film 170 to cover the copper interconnect layer 174 and the copper pillars 176 by, for example, coating an epoxy resin, a polyimide resin, or a silicone resin by screen printing or compression molding.
  • the reinforcing insulating resin film 170 is thinned by polishing from the lower surface side by, for example, a method of a back side grinder, etc. Thereby, the lower portions 164a of the intermediate structural bodies 164 also are removed; and the substrate 10 is exposed.
  • the crystal growth substrate 10 is removed as shown in FIGS. 85A and 85B.
  • the removal is performed by wet etching or dry etching.
  • an excimer laser is irradiated and lift-off is performed; or the substrate 10 is polished until the substrate 10 vanishes in the process shown in FIGS. 84A and 84B described above. Thereby, the LED layers 11 are exposed.
  • an unevenness may be formed by performing wet etching using a strongly alkaline aqueous solution and utilizing the crystal anisotropy of the n-type GaN layer 11a; or the unevenness may be formed by performing etching such as RIE, etc., using a patterned mask.
  • a fluorescer film 179 is formed on the reinforcing insulating resin film 170 by, for example, screen printing, etc.
  • the reinforcing insulating resin film 178 is thinned by polishing from the lower surface side by, for example, a method of a back side grinder, etc. Thereby, the copper pillars 176 are exposed.
  • singulation is performed every LED layer 11 by cutting the reinforcing insulating resin film 178, the insulating film 171, the reinforcing insulating resin film 170, and the fluorescer film 179 by a method such as, for example, blade dicing, laser dicing, etc.
  • a method such as, for example, blade dicing, laser dicing, etc.
  • the reflective metal layers 161 are provided below and at the side of the LED layers 11. Therefore, the light extraction efficiency of the semiconductor device 6 is high.
  • FIG. 90A to FIG. 92B are drawings showing the method for manufacturing the semiconductor device according to the modification.
  • transparent members 181 having dome configurations are formed to cover the LED layers 11.
  • a transparent resin material or transparent glass material having a semi-liquid state is formed in a dome configuration by dropping by a dispenser or by imprinting.
  • the fluorescer film 179 is formed on the reinforcing insulating resin film 170 to cover the transparent members 181.
  • the copper pillars 176 are exposed by backgrinding the reinforcing insulating resin film 178. Then, singulation is performed every LED layer 11. Thereby, the semiconductor device 6a according to the modification is manufactured.
  • the light that is emitted from the LED layer 11 is incident substantially perpendicularly to the interface between the transparent member 181 and the fluorescer film 179. Therefore, little of the light undergoes a total internal reflection at the interface; and the light extraction efficiency is high.
  • a Zener diode may be mounted in the sixth embodiment and the modification of the sixth embodiment described above.
  • an LED chip and a Zener diode chip are mounted inside one semiconductor device and connected to each other using a dummy chip.
  • FIG. 93A to FIG. 124C are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
  • the n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer lib are epitaxially grown in this order on the crystal growth substrate 10 by, for example, MO-CVD. Thereby, the LED layer 11 is formed.
  • p-mesa patterning and high-mesa patterning of the LED layer 11 are performed by, for example, RIE.
  • the n-type GaN layer 11a is exposed at the upper surface at the corners of four locations of the LED layer 11 ; and the p-type GaN layer lib is exposed at the upper surface of the remaining cross-shaped portion.
  • the p-electrode 12b is formed on the p-type GaN layer lib. At this stage, the n-electrodes 12a are not formed.
  • the passivation film 13 is formed; and openings are made on the exposed surface of the n-type GaN layer 11a by, for example, RIE.
  • the passivation film 13 covers the p-electrode 12b, the p-type GaN layer lib, the side surface of the n-type GaN layer 11a, and the upper surface of the substrate 10 and leaves a portion of the n-type GaN layer 11a exposed.
  • the n-electrodes 12a are formed on the passivation film 13.
  • the n-electrodes 12a are formed in the regions other than the region directly above the central portion of the p-electrode 12b and are connected to the n-type GaN layer 11a via openings of the passivation film 13.
  • the end portions of the n-electrodes 12a are made to overlap the end portions of the p-electrode 12b.
  • the n-electrodes 12a are separated from the p-electrode 12b by the passivation film 13.
  • the structural bodies in which the LED layers 11 , etc., are formed on the substrate 10 are adhered to the dicing tape 37.
  • the upper surfaces of the structural bodies, i.e., the n-electrodes 12a, are bonded to the dicing tape 37.
  • the dicing tape 37 and the structural bodies are inverted ; and the trench 14b is made in a lattice configuration in the lower surface of the substrate 10, i.e., the surface on the side where the LED layers 11 are not formed, by using, for example, a diamond blade (not shown) .
  • the modified portion 162 is formed by irradiating laser light toward the interior of the trench 14b so that the focal point of the laser light is positioned in the interior of the substrate 10. Then, the antistatic film 163 is formed on the entire surface. The order of the laser modification and the formation of the antistatic film 163 may be reversed .
  • the dicing tape 37 is caused to expand (expand) .
  • the relatively brittle the modified portion 162 fractures; and the substrate 10 is singulated every LED layer 11.
  • the intermediate structural body that includes the LED layer 11 hereinbelow, called the "LED chip 184" is made.
  • the LED layer 11 is provided on the substrate 10.
  • the n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer l i b are stacked in this order in the LED layer 11.
  • the configuration of the LED layer 11 is a rectangle as viewed from above.
  • the p-type GaN layer l ib and the active layer 11c are removed at the four corners of the LED layer 11 to expose the n-type GaN layer 11a at the upper surface.
  • the p-type GaN layer lib is exposed at the upper surface in the cross-shaped region other than the four corners of the LED layer 11.
  • the p-electrode 12b is provided on the upper surface of the p-type GaN layer l ib.
  • the passivation film 13 is provided to cover the p-electrode 12b and the side surfaces and upper surface of the LED layer 11 and leave the exposed surfaces of the n-type GaN layer 11a exposed.
  • the n-electrodes 12a are provided on the passivation film 13.
  • the n-electrodes 12a are disposed to cover the upper surface of the end portion and side surface of the stacked body made of the LED layer 11 and the p-electrode 12b and are connected to the n-type GaN layer 11a via openings of the passivation film 13.
  • the end portions of the p-electrode 12b and the end portions of the n-electrodes 12a overlap with the passivation film 13 interposed.
  • a rectangular parallelepiped protrusion is formed at the lower surface of the substrate 10.
  • the antistatic film 163 is provided on the lower surface of the substrate 10 and on the side surface of the substrate 10.
  • the protrusion of the substrate 10 and the antistatic film 163 provided on the lower surface of the protrusion and on the side surface of the protrusion are called a lower portion 184a of the LED chip 184; and the other portions are called an upper portion 184b of the LED chip 184.
  • the lower portion 184a is finer than the upper portion 184b.
  • a Zener diode chip 186 (hereinbelow, also called the "ZD chip 186") and a conduction dummy chip 196 are prepared.
  • the configuration of the ZD chip 186 is a substantially rectangular parallelepiped and is a square as viewed from above.
  • the conduction dummy chip 196 is a rectangular parallelepiped block made of a high electrical conductivity material such as copper (Cu), etc.
  • an n-type semiconductor layer 189 is provided on a back surface electrode 188.
  • the n-type semiconductor layer 189 is connected to the back surface electrode 188.
  • a recess is made in the central portion of the upper surface of the n-type semiconductor layer 189; a p-type semiconductor layer 190 is provided on the inner surface of the recess; and an n-type semiconductor layer 191 is provided on the p-type semiconductor layer 190.
  • n-type semiconductor layer 189 and the n-type semiconductor layer 191 are separated from each other with the p-type semiconductor layer 190 interposed.
  • a semiconductor block 192 is formed of the n-type semiconductor layer 189, the p-type semiconductor layer 190, and the n-type semiconductor layer 191.
  • An insulative passivation film 193 is provided on the end portion of the semiconductor block 192; and a front surface electrode 194 is provided on the central portion of the semiconductor block 192.
  • the front surface electrode 194 is connected to the n-type semiconductor layer 191. Accordingly, the back surface electrode 188, the n-type semiconductor layer 189, the p-type semiconductor layer 190, the n-type semiconductor layer 191, and the front surface electrode 194 are connected in series in this order in the ZD chip 186.
  • a tray 200 of the arranging machine 100 (referring to FIG. 7) is prepared.
  • a recess 201 with which the LED chip 184 engages, a recess 202 with which the ZD chip 186 engages, and a recess 203 with which the conduction dummy chip 196 engages are made in the upper surface of the tray 200.
  • the recess 201 is arranged in a matrix configuration as viewed from above.
  • the recess 202 is disposed on one longitudinal-direction side of the recess 201 as viewed from the recess 201; and the recess 203 is disposed on one lateral-direction side of the recess 201 as viewed from the recess 201.
  • One unit includes one recess 201, one recess 202, and one recess 203.
  • the recess 201 has a two-step configuration; and a lower portion 201b is formed in the lower surface central portion of an upper portion 201a.
  • the configurations of the upper portion 201a and the lower portion 201b are rectangular parallelepipeds.
  • the lower portion 201b of the recess 201 has a configuration with which the lower portion 184a of the LED chip 184 engages but the upper portion 184b does not engage; and the size of the upper portion 201a of the recess 201 is such that the upper portion 184b of the LED chip 184 engages.
  • the configurations of the recess 202 and the recess 203 are rectangular parallelepipeds.
  • the depths of the recesses 201 to 203 are set so that the upper surface of the LED chip 184 engaging with the recess 201, the upper surface of the ZD chip 186 engaging with the recess 202, and the upper surface of the conduction dummy chip 196 engaging with the recess 203 are at the same height.
  • the LED chip 184, the ZD chip 186, and the conduction dummy chip 196 are simultaneously fed onto the tray 200; and the tray 200 is caused to vibrate. Thereby, after the chips are caused to tumble on the tray 200, the LED chip 184 engages with the recess 201; the ZD chip 186 engages with the recess 202; and the conduction dummy chip 196 engages with the recess 203.
  • the vertical orientation of the LED chip 184 is restricted; and the upper portion 184b is disposed higher than the lower portion 184a.
  • the vertical orientation of the ZD chip 186 is not restricted, the ZD chip 186 may have the two orientations of the orientation in which the front surface electrode 194 is positioned on the upper side and the orientation in which the back surface electrode 188 is positioned on the upper side.
  • the vertical orientation of the conduction dummy chip 196 also is not restricted.
  • problems do not occur because the functions of the ZD chip 186 are vertically symmetric and the conduction dummy chip 196 is a single block. Then, as shown in FIG.
  • the upper surfaces of the chips are bonded to the heat-resistant tape 169; and these chips are extracted from the tray 200 by moving the heat-resistant tape 169 in a direction away from the tray 200.
  • a wafer support system in which an adhesive layer is formed on a support substrate may be used instead of the heat-resistant tape 169.
  • the chips are disposed on the heat-resistant tape 169.
  • the upper surface of the ZD chip 186 is positioned lower than the stepped surface of the boundary between the lower portion 184a and the upper portion 184b of the LED chip 184 and positioned lower than the upper surface of the conduction dummy chip 196.
  • a bump 205 e.g., a gold stud bump, is adhered to the electrode on the upper surface side of the ZD chip 186, i.e., the back surface electrode 188 or the front surface electrode 194.
  • the upper end of the bump 205 is positioned higher than the interface between the substrate 10 and the LED layer 11 of the LED chip 184 and positioned higher than the upper surface of the conduction dummy chip 196.
  • the reinforcing insulating resin film 170 is formed on the heat-resistant tape 169 to bury the chips by, for example, coating or molding. Subsequently, the heat-resistant tape 169 is peeled from the reinforcing insulating resin film 170.
  • the insulating film 171 is formed on the entire surface on the reinforcing insulating resin film 170 to cover each of the exposed portions of the chips and is provided with openings so that portions of the electrodes of each of the chips are exposed.
  • a p-side via 171a, a ZD via 171b, and an n-interconnect via 171c are made in the insulating film 171; the central portion of the p-electrode 12b of the LED chip 184 is exposed at the p-side via 171a; the central portion of the back surface electrode 188 or front surface electrode 194 of the ZD chip 186 is exposed at the ZD via 171b; and the central portion of the conduction dummy chip 196 is exposed at the n-interconnect via 171c.
  • the thick film resist 173 is formed and patterned. At this time, the thick film resist 173 is patterned into a lattice configuration so that the LED chip 184 and the ZD chip 186 are partitioned in one block and the conduction dummy chip 196 is partitioned in one block.
  • the copper interconnect layer 174 is formed in the regions where the thick film resist 173 is not formed. At this time, the copper interconnect layer 174 is divided into multiple portions because the upper portion of the thick film resist 173 protrudes from the upper surface of the copper interconnect layer 174. Also, the copper interconnect layer 174 is connected to the p-electrode 12b of the LED chip 184, the back surface electrode 188 or front surface electrode 194 of the ZD chip 186, and the conduction dummy chip 196 via the seed layer 172. On the other hand, the n-electrodes 12a of the LED chip 184 are not connected to the copper interconnect layer 174 because the n-electrodes 12a are covered with the insulating film 171.
  • the thick film resist 175 is formed on the copper interconnect layer 174 to cover the thick film resist 173; and the thick film resist 175 is patterned.
  • the thick film resist 175 is formed in a lattice configuration to cover the region where the LED chip 184 and the ZD chip 186 are disposed and leave exposed the region where the conduction dummy chip 196 is disposed and the region positioned on the side opposite to the region where the conduction dummy chip 196 is disposed as viewed from the region where the LED chip 184 and the ZD chip 186 are disposed.
  • copper (Cu) on the entire surface by electroplating, the copper pillars 176 are formed in the regions where the thick film resist 175 is not formed.
  • the copper pillars 176 are connected to the copper interconnect layer 174.
  • the seed layer 172 is selectively removed by etching using the copper pillars 176 and the copper interconnect layer 174 as a mask.
  • the copper interconnect layer 174 and the copper pillar 176 that are connected to the p-electrode 12b of the LED chip 184 and the back surface electrode 188 or front surface electrode 194 of the ZD chip 186 and the copper interconnect layer 174 and the copper pillar 176 that are connected to the conduction dummy chip 196 are electrically isolated from each other.
  • the reinforcing insulating resin film 178 is formed on the entire surface.
  • the reinforcing insulating resin film 170 is thinned by polishing from the lower surface side by, for example, a back side grinder. Thereby, the lower portion 184a of the LED chip 184 is removed; and the substrates 10 is exposed. Also, the bump 205 that is bonded to the ZD chip 186 is exposed. Further, the surface of the conduction dummy chip 196 opposite to the surface connected to the copper interconnect layer 174 is exposed.
  • the crystal growth substrate 10 of the LED chip 184 is removed as shown in FIGS. 115A to 115C. Thereby, the n-type GaN layer 11a of the LED layer 11 is exposed.
  • an n-side interconnect film 207 is formed by depositing a conductive material on the entire surface. It is favorable for the upper surface of the n-side interconnect film 207 to be formed of a material having a high optical reflectance, e.g., silver (Ag), aluminum (Al), etc.
  • the hard mask film 208 is formed on the entire surface.
  • the hard mask film 208 covers and protects the n-side interconnect film 207 and is an inorganic film having high light-shielding properties, e.g., by being formed by depositing silicon oxide (SiO 2 ) by CVD. Then, the hard mask film 208 is patterned into a matrix configuration and removed from the region where dicing is to be performed in a subsequent process.
  • the n-side interconnect film 207 is patterned by etching the n-side interconnect film 207 using the hard mask film 208 as a mask. Thereby, the n-side interconnect film 207 is partitioned at every portion connected to one LED chip 184, one ZD chip 186, and one conduction dummy chip 196 and is removed from on top of the LED layer 11.
  • the passivation film 209 favorably is an inorganic film having high light-shielding properties and can be formed by, for example, depositing silicon oxide (Si0 2 ) by CVD. Then, the LED layer 11 is exposed by patterning the passivation film 209.
  • FIGS. 121A to 121C surface roughening of the LED layer 11 is performed.
  • an unevenness is formed by utilizing the crystal anisotropy of the n-type GaN layer 11a by performing wet etching using a strongly alkaline aqueous solution, or an unevenness is formed by etching such as RIE, etc., using a patterned mask.
  • the fluorescer film 179 is formed on the reinforcing insulating resin film 170 by, for example, screen printing, etc.
  • the copper pillars 176 are exposed by polishing the reinforcing insulating resin film 178 from the lower surface side by, for example, a back side grinder.
  • singulation is performed every LED layer 11 by cutting the reinforcing insulating resin film 178, the insulating film 171, the reinforcing insulating resin film 170, and the fluorescer film 179 by a method such as, for example, blade dicing, laser dicing, etc.
  • a method such as, for example, blade dicing, laser dicing, etc.
  • FIG. 125 is a circuit diagram showing the configuration of the semiconductor device according to the embodiment.
  • the reinforcing insulating resin film 178, the reinforcing insulating resin film 170, and the fluorescer film 179 are stacked in this order in the semiconductor device 7.
  • Two sets of external electrodes made of the copper interconnect layer 174 and the copper pillar 176 are provided inside the reinforcing insulating resin film 178.
  • One LED chip 184, one ZD chip 186, and one conduction dummy chip 196 are provided inside the reinforcing insulating resin film 170.
  • the n-side interconnect film 207 is selectively provided between the reinforcing insulating resin film 170 and the fluorescer film 179.
  • the n-side interconnect film 207 is connected to the upper surface of the conduction dummy chip 196, the n-electrodes 12a of the LED chip 184, and one selected from the back surface electrode 188 and the front surface electrode 194 of the ZD chip 186.
  • the lower surface of the conduction dummy chip 196 is connected to the copper interconnect layer 174 on the cathode side.
  • the copper interconnect layer 174 on the anode side is connected to the p-electrode 12b of the LED chip 184 and the other selected from the back surface electrode 188 and the front surface electrode 194 of the ZD chip 186.
  • the LED chip 184 and the ZD chip 186 are connected in parallel between the copper pillar 176 on the cathode side and the copper pillar 176 on the anode side.
  • a current flows in the path of (the copper pillar 176 on the anode side - the copper interconnect layer 174 on the anode side - the p-electrode 12b of the LED chip 184 - the p-type GaN layer lib of the LED layer 11 - the active layer 11c - the n-type GaN layer 11a - the n-electrodes 12a - the n-side interconnect film 207 - the conduction dummy chip 196 - the copper interconnect layer 174 on the cathode side - the copper pillar 176 on the cathode side); and the LED layer 11 emits light.
  • the LED chip 184 is protected by the ZD chip 186 allowing a current to flow when an excessive voltage is applied between the copper pillar 176 on the anode side and the copper pillar 176 on the cathode side.
  • the conduction dummy chip 196 functions as an interconnect member piercing the reinforcing insulating resin film 170 in the thickness direction.
  • the p-electrode 12b made of a metal having a high optical reflectance is provided in the region directly under the central portion of the LED layer 11 ;
  • the n-electrodes 12a made of a metal having a high optical reflectance are provided in the regions directly under the side and peripheral portion of the LED layer 11 ; and the end portions of the p-electrode 12b and the end portions of the n-electrodes 12a overlap as viewed from above. Therefore, the light that is emitted from the LED layer 11 sideward and downward is reflected reliably by the p-electrode 12b and the n-electrodes 12a and emitted upward.
  • the n-side interconnect film 207 made of a metal having a high optical reflectance is provided below the fluorescer film 179, the light that is emitted downward from the fluorescer film 179 is reflected by the n-side interconnect film 207 and emitted upward. Therefore, the light extraction efficiency of the semiconductor device 7 is high.
  • the n-electrode 12a is formed previously in the modification.
  • FIG. 126A to FIG. 128B are drawings showing a method for manufacturing the semiconductor device according to the modification.
  • the LED layer 11 is formed by epitaxially growing the n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer lib in this order on the crystal growth substrate 10.
  • the n-type GaN layer 11 is divided into multiple portions by performing high-mesa patterning of the LED layer 11. Then, the n-type GaN layer
  • the passivation film 13 is formed; and openings are made in the regions directly above the n-electrodes 12a and the region directly above the p-type GaN layer l ib.
  • the p-electrode 12b that is connected to the p-type GaN layer l ib and an extension n-electrode 12c that is connected to the n-electrodes 12a are formed to be insulated from each other by forming a metal film on the entire surface and by patterning.
  • the extension n-electrode 12c is formed not only in the region directly above the n-electrodes 12a but also on the side surface of the LED layer 11 and on the upper surface of the substrate 10.
  • FIGS. 97A and 97B to FIGS. 124A to 124C are implemented.
  • the light that is emitted from the LED layer 11 can be utilizing efficiently because the extension n-electrode 12c is disposed on the side surface of the LED layer 11. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the modification are similar to those of the seventh embodiment described above.
  • the modification is an example in which a ZD chip and a conduction dummy chip are combined after previously arranging an LED chip.
  • FIG. 129A to FIG 140B are drawings showing the method for manufacturing the semiconductor device according to the modification.
  • an LED chip 184 such as that shown in FIGS. 100A to lOOC is made by implementing the processes shown in FIGS. 93A and 93B to FIGS. 99A and 99B. Also, a conduction dummy chip 196 such as that shown in FIGS. 100G and 100H is made.
  • the bump 205 is bonded on the front surface electrode 194 of the ZD chip 186 or on the back surface electrode 188 of the ZD chip 186.
  • a tray 210 of an arranging machine is prepared.
  • the recess 201 with which the LED chip 184 engages is made in the upper surface of the tray 210.
  • the multiple LED chips 186 are fed onto the tray 210; and the tray 210 is caused to vibrate.
  • the LED chips 184 are arranged by engaging with the recesses 201 of the tray 210.
  • a transfer tray 211 is caused to oppose the tray 210 and is brought into contact with the tray 210.
  • a recess 212 is made in the transfer tray 211 at a position opposing the recess 201 of the tray 210.
  • the recess 212 has a configuration with which the portion of the LED chip 184 protruding from the recess 201 engages.
  • the coupled body of the tray 210 and the transfer tray 211 is vertically inverted.
  • the LED chip 184 moves from the recess 201 side toward the recess 212 side inside the space where the recess 201 and the recess 212 communicate.
  • the tray 210 is removed from the transfer tray 211 ; and instead of the tray 210, a final tray 215 is brought into contact with the transfer tray 211.
  • a recess 216, a recess 217, and a recess 218 (referring to FIG. 140A) are made in the final tray 215.
  • the recess 216 is made in a position opposing the recess 212 of the transfer tray 211 and has a configuration with which the portion of the LED chip 184 protruding from the recess 212 engages.
  • the recess 217 has a configuration with which the ZD chip 186, to which the bump 205 is bonded, engages with the bump 205 on the lower side.
  • the recess 218 has a configuration with which the conduction dummy chip 196 engages.
  • the coupled body of the transfer tray 211 and the final tray 215 is vertically inverted.
  • the LED chip 184 moves from the recess 212 side toward the recess 216 side inside the space where the recess 212 and the recess 216 communicate.
  • the transfer tray 211 is removed from the final tray 215.
  • a ZD tray 220 is prepared as shown in FIG. 136.
  • a recess 221 is made in the ZD tray 220.
  • the size of the recess 221 is such that the portion of the ZD chip 186, to which the bump 205 is bonded, that engages the recess 221 is the side where the bump 205 is not bonded. Then, multiple ZD chips 186 are fed onto the ZD tray 220; and the ZD tray 220 is caused to vibrate.
  • the ZD chips 186 are arranged by engaging with the recesses 221 of the ZD tray 220.
  • the bump 205 is disposed at the top of the ZD chip 186.
  • a ZD guide jig 223 is caused to cover the final tray 215.
  • the LED chip 184 engages with the recess 216 of the final tray 215.
  • the ZD guide jig 223 at the position opposing the recess 216 of the final tray 215 is used as a lid 224 covering the LED chip 184; and a through-portion 225 through which the ZD chip 186 can pass is made in the ZD guide jig 223 at the position opposing the recess 217.
  • the coupled body of the final tray 215 and the ZD guide jig 223 is vertically inverted and brought into contact with the ZD tray 220 so that the through-portion 225 opposes the recess 221.
  • the LED chip 184 inside the recess 216 is held by the lid 224 of the ZD guide jig 223.
  • the coupled body in which the ZD tray 220, the ZD guide jig 223, and the final tray 215 are stacked is vertically inverted.
  • the ZD chip 186 that was engaged with the recess 221 of the ZD tray 220 moves from the recess 221 to the recess 217 of the final tray 215 through the through-portion 225 of the ZD guide jig 223 and engages with the recess 217.
  • the LED chip 184 is fixed inside the recess 216; and the ZD chip 186 is fixed inside the recess 217.
  • the ZD tray 220 and the ZD guide jig 223 are removed from the final tray 215.
  • the conduction dummy chip 196 is caused to engage with the recess 218 of the final tray 215 by a method similar to the method for transferring the ZD chip 186 described above.
  • the LED chip 184 is fixed inside the recess 216; the ZD chip 186 is fixed inside the recess 217; and the conduction dummy chip 196 is fixed inside the recess 218.
  • the subsequent processes are similar to the processes shown in FIG. 103 to FIGS. 124A to 124C of the seventh embodiment described above.
  • the modification there is little trouble such as chips snagging in recesses, etc., because the chips are fed onto the tray one type at a time. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the modification are similar to those of the seventh embodiment described above.
  • the embodiment differs from the seventh embodiment described above in that the connection in the thickness direction is made using a laser via instead of the dummy chip.
  • FIG. 141A to FIG. 173C are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
  • the LED layer 11 is formed by epitaxially growing the n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer l ib in this order on the crystal growth substrate 10 by, for example, O-CVD.
  • the LED layer 11 is subdivided into multiple portions.
  • the configuration of each of the portions of the LED layer 11 is a rectangle; and the multiple portions are arranged in a matrix configuration.
  • p-mesa patterning of the LED layer 11 is performed. Thereby, the p-type GaN layer l ib, the active layer, and the upper layer portion of the n-type GaN layer 11a are removed at the peripheral portion of the LED layer 11. As a result, a stepped portion is formed in the region of the side surface of the LED layer 11 where the n-type GaN layer 11a is exposed; and the active layer is positioned higher than the stepped portion.
  • the p-mesa patterning may be omitted.
  • the passivation film 13 is formed on the entire surface as shown in FIGS. 144A and 144B.
  • An insulating material such as, for example, silicon oxide, silicon nitride, etc., is deposited by PVD or CVD.
  • the passivation film 13 is patterned by, for example, lithography and RIE to make openings in the regions directly above the central portions of the p-type GaN layers l ib.
  • the p-mesa patterning being performed in the process shown in FIGS. 143A and 143B, the side surfaces of the active layers are reliably covered with the passivation film 13; and the reliability increases.
  • the p-electrodes 12b are formed inside the openings of the passivation film 13. Specifically, a metal film is formed by depositing a metal having a high optical reflectance, e.g., silver (Ag), by PVD; a resist mask is formed by lithography; and the metal film is patterned by performing RIE or wet etching.
  • the p-electrodes 12b are connected to the p-type GaN layers lib.
  • a barrier metal layer (not shown) may be formed on the p-electrodes 12b.
  • the structural bodies in which the LED layers 11, etc., are formed on the substrate 10 are adhered to the dicing tape 37.
  • the upper surfaces of the structural bodies, i.e., the p-electrodes 12b, are bonded to the dicing tape 37.
  • the dicing tape 37 and the structural bodies are inverted; and the trench 14b is made in a lattice configuration in the lower surface of the substrate 10 by, for example, a diamond blade (not shown).
  • the modified portion 162 is formed by irradiating laser light so that the focal point of the laser light is positioned the interior of the substrate 10. Then, the antistatic film 163 is formed on the entire surface. The order of the laser modification and the formation of the antistatic film 163 may be reversed.
  • the dicing tape 37 is caused to expand (expand).
  • the relatively brittle modified portion 162 fractures; and the substrate 10 is singulated every LED layer 11.
  • the intermediate structural body that includes the LED layer 11 hereinbeiow, called the "LED chip 230" is made.
  • the LED layer 11 is provided on the substrate 10 in the LED chip 230.
  • the n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer lib are stacked in this order in the LED layer 11.
  • the configuration of the LED layer 11 is a rectangle as viewed from above; and the p-type GaN layer l ib, the active layer 11c, and the upper layer portion of the n-type GaN layer 11a are removed at the peripheral region.
  • the p-type GaN layer l ib is exposed at the upper surface in the region of the LED layer 11 other than the peripheral portion.
  • the p-electrode 12b is provided on the upper surface of the portion of the p-type GaN layer l ib other than the peripheral portion.
  • the passivation film 13 is provided on the regions of the side surface of the LED layer 11 and the upper surface of the LED layer 11 not contacting the p-electrode 12b.
  • a rectangular parallelepiped protrusion is formed in the lower surface of the substrate 10.
  • the antistatic film 163 is provided on the lower surface of the substrate 10.
  • the protrusion of the substrate 10 and the antistatic film 163 provided on the lower surface of the protrusion and on the side surface of the protrusion are called a lower portion 230a of the LED chip 230; and the other portions are called an upper portion 230b.
  • the lower portion 230a is finer than the upper portion 230b.
  • the ZD chip 186 shown in FIGS. 100D to 100F also is prepared.
  • the embodiment differs from the seventh embodiment described above in that the conduction dummy chip 196 (referring to FIGS. 100G and H) is not used.
  • a tray 232 of the arranging machine 100 (referring to FIG. 7) is prepared.
  • a recess 233 with which the LED chip 230 engages and the recess 202 with which the ZD chip 186 engages are made in the upper surface of the tray 232.
  • the recess 233 is arranged in a matrix configuration as viewed from above.
  • the recess 202 is disposed on one longitudinal-direction side of the recess 233 as viewed from the recess 233.
  • One unit includes one recess 233 and one recess 202.
  • the recess 233 has a two-step configuration; and a lower portion 233b is formed in the lower surface central portion of an upper portion 233a.
  • the configurations of the upper portion 233a and the lower portion 233b are rectangular parallelepipeds.
  • the lower portion 233b of the recess 233 has a configuration with which the lower portion 230a of the LED chip 230 engages but the upper portion 230b of the LED chip 230 does not engage; and the upper portion 233a of the recess 233 has a configuration with which the upper portion 230b of the LED chip 230 engages.
  • the depths of the recess 233 and the recess 202 are set so that the upper surface of the LED chip 230 engaging with the recess 233 and the upper surface of the ZD chip 186 engaging with the recess 202 are at the same height.
  • the LED chip 230 and the ZD chip 186 are fed simultaneously onto the tray 232; and the tray 232 is caused to vibrate.
  • the LED chip 230 is fixed in the vertical direction and contained inside the recess 233 by the lower portion 230a of the LED chip 230 engaging with the lower portion 233b of the recess 233 and the upper portion 230b of the LED chip 230 engaging with the upper portion 233a of the recess 233.
  • the ZD chip 186 engages with the recess 202.
  • the orientation of the vertical direction of the ZD chip 186 is not restricted and may have the two orientations of the orientation in which the front surface electrode 194 is positioned on the upper side and the orientation in which the back surface electrode 188 is positioned on the upper side.
  • problems do not occur because the functions of the ZD chip 186 are vertically symmetric.
  • LED chip 230 and the ZD chip 186 are bonded to the heat-resistant tape 169; and the chips are removed from the tray 232.
  • a wafer support system in which an adhesive layer is formed on a support substrate may be used.
  • the chips are disposed on the heat-resistant tape 169.
  • the upper surface of the ZD chip 186 is positioned lower than the stepped surface of the boundary between the lower portion 230a and the upper portion 230b of the LED chip 230.
  • the gold stud bump 205 is adhered to the electrode on the upper surface side of the ZD chip 186, i.e., the back surface electrode 188 or the front surface electrode 194.
  • the upper end of the bump 205 is positioned higher than the interface between the substrate 10 and the LED layer 11 of the LED chip 230.
  • the reinforcing insulating resin film 170 is formed to bury on the heat-resistant tape 169 and the chips by, for example, coating or molding. Subsequently, the heat-resistant tape 169 is peeled from the reinforcing insulating resin film 170.
  • the insulating film 171 is formed on the entire surface of the reinforcing insulating resin film 170; and openings are made to expose portions of the electrodes of each of the chips.
  • the p-side via 171a and the ZD via 171b are made in the insulating film 171; the central portion of the p-electrode 12b of the LED chip 230 is exposed at the p-side via 171a; and the central portion of the back surface electrode 188 or front surface electrode 194 of the ZD chip 186 is exposed at the ZD via 171b.
  • the seed layer 172 is formed on the entire surface by, for example, PVD.
  • the thick film resist 173 is formed and patterned.
  • the thick film resist 173 is patterned into a lattice configuration so that one block is set to include both the LED chip 230 and the ZD chip 186 and one block is set to include neither the LED chip 230 nor the ZD chip 186.
  • the copper interconnect layer 174 is formed in the regions where the thick film resist 173 is not formed. At this time, the upper portion of the thick film resist 173 protrudes from the upper surface of the copper interconnect layer 174. Also, the copper interconnect layer 174 is connected to the p-electrode 12b of the LED chip 230 and the back surface electrode 188 or front surface electrode 194 of the ZD chip 186 via the seed layer 172.
  • the thick film resist 175 is formed on the copper interconnect layer 174 to cover the thick film resist 173; and the thick film resist 175 is patterned.
  • the thick film resist 175 is formed in a lattice configuration.
  • the thick film resist 175 is formed to cover the region where dicing is to be performed in a subsequent process, cover the region having the band configuration extending in the arrangement direction of the LED chip 230 and the ZD chip 186 in which both the LED chip 230 and the ZD chip 186 are disposed, and leave the rectangular regions on two lateral-direction sides of the LED chip 230 as viewed from the region having the band configuration exposed.
  • the copper pillars 176 are formed in the regions where the thick film resist 175 is not formed by forming copper (Cu) on the entire surface by electroplating.
  • the copper pillars 176 are connected to the copper interconnect layer 174.
  • the thick film resist 175 and the thick film resist 173 are removed as shown in FIGS. 160A to 160C.
  • the portion of the seed layer 172 not covered with the copper interconnect layer 174 is removed by etching using the copper pillars 176 and the copper interconnect layer 174 as a mask.
  • two sets of the set made of the copper interconnect layer 174 and the copper pillar 176 are partitioned every unit made of one LED chip 230 and one ZD chip 186; one set is connected to both the ZD chip 186 and the p-electrode 12b of the LED chip 230; and the other set is connected to neither the LED chip 230 nor the ZD chip 186.
  • the reinforcing insulating resin film 178 is formed on the entire surface as shown in FIGS. 161A to 161C.
  • the reinforcing insulating resin film 170 is thinned by polishing from the lower surface side by, for example, a back side grinder. Thereby, the lower portions 230a of the LED chips 230 are removed to expose the substrates 10. Also, the bumps 205 that are bonded to the ZD chips 186 are exposed.
  • the crystal growth substrates 10 of the LED chips 230 are removed by etching. Thereby, the LED layers 11 are exposed.
  • via holes 235 are made by selectively removing the reinforcing insulating resin film 170 and the insulating film 171 by, for example, laser patterning.
  • the via holes 235 are made in regions directly above the copper interconnect layers 174 and are connected to neither the LED chip 230 nor the ZD chip 186. Thereby, the copper interconnect layers 174 are exposed at the bottom surfaces of the via holes 235.
  • patterning by RIE is possible as well.
  • a dummy silicon chip may be buried in the process of forming the reinforcing insulating resin film 170 shown in FIG. 154; and the silicon chip also may be removed by etching when etching the substrate 10 in the process shown in FIGS. 164A to 164C.
  • the n-side interconnect film 207 is formed by depositing a conductive material having a low resistivity on the entire surface. It is favorable for the upper surface of the n-side interconnect film 207 to be formed of a material having a high optical reflectance, e.g., silver (Ag), aluminum (Al), etc.
  • the n-side interconnect film 207 is connected to the n-type GaN layers 11a of the LED chips 230 and the bumps 205 bonded to the ZD chips 186 and is connected to the copper interconnect layers 174 in the interior of the via holes 235 by being formed on the inner surfaces of the via holes 235 as well.
  • the hard mask film 208 is formed on the entire surface as shown in FIGS. 167A to 167C. It is favorable for the hard mask film 208 to be an inorganic film that covers and protects the n-side interconnect film 207 and has high light-shielding properties, e.g., to be formed by depositing silicon oxide (Si0 2 ) by CVD. Then, the hard mask film 208 is patterned to make openings in the region where dicing is to be performed in a subsequent process, at the entire central portions of the LED layers 11, and at portions of the peripheral portions of the LED layers 11.
  • Si0 2 silicon oxide
  • the n-side interconnect film 207 is patterned by etching the n-side interconnect film 207 using the hard mask film 208 as a mask. Thereby, the n-side interconnect film 207 is partitioned every portion connected to one LED chip 230 and one ZD chip 186. Also, the n-side interconnect film 207 that is on the LED layers 11 is selectively removed.
  • the passivation film 209 is formed on the entire surface. It is favorable for the passivation film 209 to be an inorganic film having high light-shielding properties, e.g., it is favorable to be a silicon oxide film formed by CVD. Then, the passivation film 209 is patterned to cover the n-side interconnect film 207 and leave the LED layers 11 exposed.
  • the fluorescer film 179 is formed on the reinforcing insulating resin film 170 as shown in FIGS. 171A to 171C.
  • the copper pillars 176 are exposed by polishing the reinforcing insulating resin film 178 from the lower surface side by, for example, a back side grinder.
  • singulation is performed every LED layer 11 by cutting the reinforcing insulating resin film 178, the insulating film 171, the reinforcing insulating resin film 170, and the fluorescer film 179 by, for example, a method such as blade dicing, laser dicing, etc.
  • a method such as blade dicing, laser dicing, etc.
  • FIG. 174 is a circuit diagram showing the semiconductor device according to the embodiment.
  • the reinforcing insulating resin film 178, the reinforcing insulating resin film 170, and the fluorescer film 179 are stacked in this order in the semiconductor device 8.
  • Two sets of the external electrodes made of the copper interconnect layer 174 and the copper pillar 176 are provided inside the reinforcing insulating resin film 178.
  • One LED chip 230 and one ZD chip 186 are provided inside the reinforcing insulating resin film 170.
  • the via hole 235 is made in the reinforcing insulating resin film 170 to pierce the reinforcing insulating resin film 170 in the thickness direction.
  • the n-side interconnect film 207 is selectively provided between the reinforcing insulating resin film 170 and the fluorescer film 179.
  • the n-side interconnect film 207 is provided also on the inner surface of the via hole 235.
  • the copper interconnect layer 174 on the cathode side is connected to the n-side interconnect film 207 through the via hole 235.
  • the n-side interconnect film 207 is connected to the n-type GaN layer 11a of the LED chip 230 and one selected from the back surface electrode 188 and the front surface electrode 194 of the ZD chip 186.
  • the copper interconnect layer 174 on the anode side is connected to the p-electrode 12b of the LED chip 230 and the other selected from the back surface electrode 188 and the front surface electrode 194 of the ZD chip 186.
  • the LED chip 230 and the ZD chip 186 are connected in parallel between the copper pillar 176 on the anode side and the copper pillar 176 on the cathode side.
  • the current flows in the path of (the copper pillar 176 on the anode side - the copper interconnect layer 174 on the anode side - the p-electrode 12b of the LED chip 230 - the p-type GaN layer l ib of the LED layer 11 - the active layer - the n-type GaN layer 11a - the n-side interconnect film 207 (including the portion formed on the inner surface of the via hole 235) - the copper interconnect layer 174 on the cathode side - the copper pillar 176 on the cathode side); and the LED layer 11 emits light.
  • the LED chip 230 is protected by the ZD chip 186 allowing a current to flow when an excessive voltage is applied between the copper pillar 176 on the anode side and the copper pillar 176 on the cathode side.
  • the n-side interconnect film 207 that is formed on the inner surface of the via hole 235 is used as the interconnect member piercing the reinforcing insulating resin film 170 in the thickness direction.
  • a semiconductor device that is similar to the seventh embodiment described above can be realized by making the via hole 235 instead of providing the conduction dummy chip 196.
  • a semiconductor device and a method for manufacturing the semiconductor device having high heat dissipation and a low manufacturing cost can be realized.

Abstract

A method for manufacturing a semiconductor device according to an embodiment includes making intermediate structural bodies. A configuration of an upper portion of the intermediate structural body and a configuration of a lower portion of it are different from each other. The method includes arranging the intermediate structural bodies to be separated from each other by causing one portion selected from the upper portion and the lower portion to engage with a recess multiply made in an upper surface of a tray by causing the intermediate structural bodies to tumble on the tray. The one portion is configured to engage with the recess. The other portion selected from the upper portion and the lower portion is configured not to engage with the recess. The method includes forming an external electrode connected to an electrode of the intermediate structural body.

Description

[DESCRIPTION] [Title]
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
[FIELD]
Embodiments of the invention relates to a semiconductor device and a method for manufacturing the same.
[Background]
Conventionally, methods have been proposed to manufacture semiconductor devices by the crystal growth of a semiconductor layer on a wafer, forming electrodes on the semiconductor layer, and removing the wafer after sealing with a resin body. According to such methods, the fine structural bodies that are formed on the wafer can be packaged as-is; and fine packages can be manufactured efficiently. However, there are cases where sufficient heat dissipation is difficult for such semiconductor devices because the package size is small.
[Citation List]
[Patent Literature]
[PTL 1]
JP-A 2010-251359
[BRIEF DESCRIPTION OF THE DRAWINGS]
FIG. 1A is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment. FIG. IB is a cross-sectional view along line A-A' shown in FIG. 1A.
FIG. 2A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 2B is a cross-sectional view along line A-A' shown in FIG. 2A.
FIG. 3A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 3B is a cross-sectional view along line A-A' shown in FIG. 3A.
FIG. 4A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4B is a cross-sectional view along line A-A' shown in FIG. 4A.
FIG. 5A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5B is a cross-sectional view along line A-A' shown in FIG. 5A.
FIG. 6A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6B is a cross-sectional view along line A-A' shown in FIG. 6A.
FIG. 7 is a cross-sectional view showing an arranging machine used in the first embodiment.
FIGS. 8A and 8B are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.
FIG. 9A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 9B is a cross-sectional view along line A-A' shown in FIG. 9A.
FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
FIG. 11 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
FIGS. 12A and 12B are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.
FIGS. 13A and 13B are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 14A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 14B is a cross-sectional view along line A-A' shown in FIG. 14A.
FIG. 15A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 15B is a cross-sectional view along line A-A' shown in FIG. 15A.
FIG. 16A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 16B is a cross-sectional view along line A-A' shown in FIG. 16A.
FIG. 17A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 17B is a cross-sectional view along line A-A' shown in FIG. 17A.
FIG. 18A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 18B is a cross-sectional view along line A-A' shown in FIG. 18A.
FIGS. 19A and 19B are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.
FIGS. 20A and 20B are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.
FIG. 21A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 21B is a cross-sectional view along line A-A' shown in FIG. 21A.
FIG. 22A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment; and FIG. 22B is a cross-sectional view along line A-A' shown in FIG. 22A.
FIG. 23 is a plan view showing an intermediate structural body of a first modification of the first embodiment. FIG. 24 is a plan view showing an intermediate structural body of a second modification of the first embodiment.
FIG. 25 is a plan view showing an intermediate structural body of a third modification of the first embodiment.
FIG. 26A is a plan view showing an intermediate structural body of a fourth modification of the first embodiment; FIG. 26B is a cross-sectional view along line A-A' shown in FIG. 26A; and FIG . 26C is a perspective view as viewed from the lower side.
FIG. 27A is a cross-sectional view showing an intermediate structural body of a fifth modification of the first embodiment; FIG. 27B is a perspective view showing the intermediate structural body and the recess; and FIG. 27C is a perspective view showing the state in which the intermediate structural body engages with the recess.
FIGS. 28A to 28D are cross-sectional views showing a method for manufacturing a semiconductor device according to the sixth modification of the first embodiment.
FIGS. 29A and 29B are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh modification of the first embodiment.
FIGS. 30A and 30B are cross-sectional views showing a method for manufacturing a semiconductor device according to an eighth modification of the first embodiment.
FIG . 31A is a plan view showing a method for manufacturing a semiconductor device according to a second embodiment; and FIG. 31 B is a cross-sectional view along line
A-A' shown in FIG. 31A.
FIG . 32A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG . 32B is a cross-sectional view along line A-A' shown in FIG. 32A.
FIG. 33A is a plan view showing the method for manufacturing the semiconductor device according to the second em bodiment; and FIG . 33B is a cross-sectional view along line A-A' shown in FIG. 33A. FIG. 34A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 34B is a cross-sectional view along line A-A' shown in FIG. 34A.
FIGS. 35A and 35B and FIG. 36 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.
FIG. 37A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 37B is a cross-sectional view along line A-A' shown in FIG. 37A.
FIGS. 38A and 38B are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.
FIG. 39A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 39B is a cross-sectional view along line A-A' shown in FIG. 39A.
FIG. 40A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 40B is a cross-sectional view along line A-A' shown in FIG. 40A.
FIG. 41A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 41B is a cross-sectional view along line A-A' shown in FIG. 41A.
FIG. 42A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 42B is a cross-sectional view along line A-A' shown in FIG. 42A.
FIG. 43A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 43B is a cross-sectional view along line A-A' shown in FIG. 43A.
FIG. 44A is a plan view showing the method for manufacturing the semiconductor device according to the second embodiment; and FIG. 44B is a cross-sectional view along line A-A' shown in FIG. 44A.
FIG. 45 is a plan view showing a method for manufacturing a semiconductor device according to a third embodiment.
FIG. 46 is a plan view showing a method for manufacturing a semiconductor device according to a modification of the third embodiment.
FIG. 47 and FIG. 48 are perspective views showing a method for manufacturing a semiconductor device according to a fourth embodiment.
FIG. 49A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 49B is a cross-sectional view along line A-A' shown in FIG. 49A.
FIG. 50A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 50B is a cross-sectional view along line A-A' shown in FIG. 50A.
FIG. 51 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment.
FIG. 52A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 52B is a cross-sectional view along line A-A' shown in FIG. 52A.
FIG. 53A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 53B is a cross-sectional view along line A-A' shown in FIG. 53A.
FIG. 54A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 54B is a cross-sectional view along line A-A' shown in FIG. 54A.
FIG. 55A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 55B is a cross-sectional view along line A-A' shown in FIG. 55A.
FIG. 56A is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment; and FIG. 56B is a cross-sectional view along line A-A' shown in FIG. 56A.
FIGS. 57A and 57B and FIG. 58 are cross-sectional views showing the method for manufacturing the semiconductor device according to the fourth embodiment.
FIG. 59 is a drawing comparing the configurations of an
LED layer and a semiconductor substrate of the fourth embodiment.
FIG. 60A is a plan view showing a method for manufacturing a semiconductor device according to a fifth embodiment; FIG. 60B is a plan view showing the semiconductor device; and FIG. 60C is a drawing showing a relationship between configurations of semiconductor members.
FIGS. 61A to 61D are drawings comparing configurations of intermediate structural bodies of a modification of the fifth embodiment.
FIG. 62A is a plan view showing a method for manufacturing a semiconductor device according to a sixth embodiment; and FIG. 62B is a cross-sectional view along line A-A' shown in FIG. 62A.
FIG. 63A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 63B is a cross-sectional view along line A-A' shown in FIG. 63A.
FIG. 64A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 64B is a cross-sectional view along line A-A' shown in FIG. 64A.
FIG. 65A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 65B is a cross-sectional view along line A-A' shown in FIG. 65A. FIG. 66A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 66B is a cross-sectional view along line A-A' shown in FIG. 66A.
FIG. 67A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 67B is a cross-sectional view along line A-A' shown in FIG. 67A.
FIG. 68A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 68B is a cross-sectional view along line A-A' shown in FIG. 68A.
FIGS. 69A to 69C are drawings showing the method for manufacturing the semiconductor device according to the sixth embodiment; FIG. 69A is a plan view of an intermediate structural body as viewed from a crystal growth substrate side; FIG. 69B is a plan view as viewed from an LED layer side; and FIG. 69C is a cross-sectional view along line A-A' shown in FIG. 69B.
FIG. 70 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the sixth embodiment.
FIG. 71A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 71B is a cross-sectional view along line A-A' shown in FIG. 71A.
FIGS. 72 to 75 are cross-sectional views showing the method for manufacturing the semiconductor device according to the sixth embodiment.
FIG. 76A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 76B is a cross-sectional view along line A-A' shown in FIG. 76A.
FIG. 77A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 77B is a cross-sectional view along line A-A' shown in FIG. 77A.
FIG. 78A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 78B is a cross-sectional view along line A-A' shown in FIG. 78A.
FIG. 79A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 79B is a cross-sectional view along line A-A' shown in FIG. 79A.
FIG. 80A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 80B is a cross-sectional view along line A-A' shown in FIG. 80A.
FIG. 81A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 81B is a cross-sectional view along line A-A' shown in FIG. 81A.
FIG. 82A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 82B is a cross-sectional view along line A-A' shown in FIG. 82A.
FIG. 83A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 83B is a cross-sectional view along line A-A' shown in FIG. 83A.
FIG. 84A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 84B is a cross-sectional view along line A-A' shown in FIG. 84A.
FIG. 85A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 85B is a cross-sectional view along line A-A' shown in FIG. 85A.
FIG. 86A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 86B is a cross-sectional view along line A-A' shown in FIG. 86A.
FIG. 87A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 87B is a cross-sectional view along line A-A' shown in FIG. 87A.
FIG. 88A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 88B is a cross-sectional view along line A-A' shown in FIG. 88A.
FIG. 89A is a plan view showing the method for manufacturing the semiconductor device according to the sixth embodiment; and FIG. 89B is a cross-sectional view along line A-A' shown in FIG. 89A.
FIG. 90A is a plan view showing a method for manufacturing a semiconductor device according to a modification of the sixth embodiment; and FIG. 90B is a cross-sectional view along line A-A' shown in FIG. 90A.
FIG. 91A is a plan view showing the method for manufacturing the semiconductor device according to the modification of the sixth embodiment; and FIG. 91B is a cross-sectional view along line A-A' shown in FIG. 91A.
FIG. 92A is a plan view showing the method for manufacturing the semiconductor device according to the modification of the sixth embodiment; and FIG. 92B is a cross-sectional view along line A-A' shown in FIG. 92A.
FIG. 93A is a plan view showing a method for manufacturing a semiconductor device according to a seventh embodiment; and FIG. 93B is a cross-sectional view along line A-A' shown in FIG. 93A.
FIG. 94A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 94B is a cross-sectional view along line A-A' shown in FIG. 94A.
FIG. 95A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 95B is a cross-sectional view along line A-A' shown in FIG. 95A.
FIG. 96A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 96B is a cross-sectional view along line A-A' shown in FIG. 96A.
FIG. 97A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 97B is a cross-sectional view along line A-A' shown in FIG. 97A.
FIG. 98A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 98B is a cross-sectional view along line A-A' shown in FIG. 98A.
FIG. 99A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 99B is a cross-sectional view along line A-A' shown in FIG. 99A.
FIGS. 100A to 100H are drawings showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 100A is a plan view of the LED chip as viewed from the crystal growth substrate side; FIG. 100B is a cross-sectional view along line A-A' shown in FIG. 100A; FIG. lOOC is a plan view as viewed from the LED layer side; FIG. 100D is a plan view of the Zener diode chip as viewed from the upper surface side; FIG. 100E is a cross-sectional view; FIG. 100F is a plan view as viewed from the lower surface side; FIG. 100G is a top view showing the conduction dummy chip; and FIG. 100H is a side view.
FIG. 101 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the seventh embodiment.
FIG. 102A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; and FIG. 102B is a cross-sectional view along line A-A' shown in FIG. 102A.
FIG. 103 and FIG. 104 are cross-sectional views showing the method for manufacturing the semiconductor device according to the seventh embodiment.
FIGS. 105A and 105B and FIGS. 106A and 106B are cross-sectional views showing the method for manufacturing the semiconductor device according to the seventh embodiment.
FIG. 107A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 107B is a cross-sectional view along line A-A' shown in FIG. 107A; and FIG. 107C is a cross-sectional view along line B-B' shown in FIG 107A.
FIG. 108A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 108B is a cross-sectional view along line A-A' shown in FIG. 108A; and FIG. 108C is a cross-sectional view along line B-B' shown in FIG 108A.
FIG. 109A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 109B is a cross-sectional view along line A-A' shown in FIG. 109A; and FIG. 109C is a cross-sectional view along line B-B' shown in FIG 109A.
FIG. 110A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. HOB is a cross-sectional view along line A-A' shown in FIG. 110A; and FIG. HOC is a cross-sectional view along line B-B' shown in FIG 110A.
FIG. 111A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 111B is a cross-sectional view along line A-A' shown in FIG. 111A; and FIG. 111C is a cross-sectional view along line B-B' shown in FIG 111A.
FIG. 112A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 112B is a cross-sectional view along line A-A' shown in FIG. 112A; and FIG. 112C is a cross-sectional view along line B-B' shown in FIG 112A.
FIG. 113A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 113B is a cross-sectional view along line A-A' shown in FIG. 113A; and FIG. 113C is a cross-sectional view along line B-B' shown in FIG 113A.
FIG. 114A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 114B is a cross-sectional view along line A-A' shown in FIG. 114A; and FIG. 114C is a cross-sectional view along line B-B' shown in FIG 114A.
FIG. 115A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 115B is a cross-sectional view along line A-A' shown in FIG. 115A; and FIG. 115C is a cross-sectional view along line B-B' shown in FIG 115A.
FIG. 116A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 116B is a cross-sectional view along line A-A' shown in FIG. 116A; and FIG. 116C is a cross-sectional view along line B-B' shown in FIG 116A.
FIG. 117A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 117B is a cross-sectional view along line A-A' shown in FIG. 117A; and FIG. 117C is a cross-sectional view along line B-B' shown in FIG 117A.
FIG. 118A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 118B is a cross-sectional view along line A-A' shown in FIG. 118A; and FIG. 118C is a cross-sectional view along line B-B' shown in FIG 118A.
FIG. 119A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 119B is a cross-sectional view along line A-A' shown in FIG. 119A; and FIG. 119C is a cross-sectional view along line B-B' shown in FIG 119A.
FIG. 120A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 120B is a cross-sectional view along line A-A' shown in FIG. 120A; and FIG. 120C is a cross-sectional view along line B-B' shown in FIG 120A.
FIG. 121A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 121B is a cross-sectional view along line A-A' shown in FIG. 121A; and FIG. 121C is a cross-sectional view along line B-B' shown in FIG 121A.
FIG. 122A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 122B is a cross-sectional view along line A-A' shown in FIG. 122A; and FIG. 122C is a cross-sectional view along line B-B' shown in FIG 122A.
FIG. 123A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 123B is a cross-sectional view along line A-A' shown in FIG. 123A; and FIG. 123C is a cross-sectional view along line B-B' shown in FIG 123A.
FIG. 124A is a plan view showing the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 124B is a cross-sectional view along line A-A' shown in FIG. 124A; and FIG. 124C is a cross-sectional view along line B-B' shown in FIG 124A.
FIG. 125 is a circuit diagram showing a configuration of the semiconductor device according to the seventh embodiment.
FIG. 126A is a plan view showing a method for manufacturing a semiconductor device according to a first modification of the seventh embodiment; and FIG. 126B is a cross-sectional view along line A-A' shown in FIG 126A.
FIG. 127A is a plan view showing the method for manufacturing the semiconductor device according to the first modification of the seventh embodiment; and FIG. 127B is a cross-sectional view along line A-A' shown in FIG 127A.
FIG. 128A is a plan view showing the method for manufacturing the semiconductor device according to the first modification of the seventh embodiment; and FIG. 128B is a cross-sectional view along line A-A' shown in FIG 128A.
FIGS. 129A to 129C are drawings showing a method for manufacturing a semiconductor device according to a second modification of the seventh embodiment; FIG. 129A is a plan view of a Zener diode chip as viewed from an upper surface side; FIG. 129B is a cross-sectional view; and FIG. 129C is a plan view as viewed from a lower surface side.
FIGS. 130 to 139 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second modification of the seventh embodiment.
FIG. 140A is a plan view showing the method for manufacturing the semiconductor device according to the second modification of the seventh embodiment; and FIG. 140B is a cross-sectional view along line A-A' shown in FIG 140A.
FIG. 141A is a plan view showing a method for manufacturing a semiconductor device according to an eighth embodiment; and FIG. 141B is a cross-sectional view along line A-A' shown in FIG 141A.
FIG. 142A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 142B is a cross-sectional view along line A-A' shown in FIG 142A.
FIG. 143A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 143B is a cross-sectional view along line A-A' shown in FIG 143A.
FIG. 144A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 144B is a cross-sectional view along line A-A' shown in FIG 144A.
FIG. 145A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 145B is a cross-sectional view along line A-A' shown in FIG 145A.
FIG. 146A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 146B is a cross-sectional view along line A-A' shown in FIG 146A.
FIG. 147A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 147B is a cross-sectional view along line A-A' shown in FIG 147A.
FIG. 148A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 148B is a cross-sectional view along line A-A' shown in FIG 148A.
FIGS. 149A to 149C are drawings showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 149A is a plan view of an LED chip as viewed from a crystal growth substrate side; FIG. 149B is a cross-sectional view along line A-A' shown in FIG. 149A; and FIG. 149C is a plan view as viewed from an LED layer side.
FIG. 150 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment.
FIG. 151A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 151B is a cross-sectional view along line A-A' shown in FIG 151A.
FIGS. 152 to 155 are cross-sectional views showing the method for manufacturing the semiconductor device according to the eighth embodiment.
FIG. 156A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 156B is a cross-sectional view along line A-A' shown in FIG 156A.
FIG. 157A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; and FIG. 157B is a cross-sectional view along line A-A' shown in FIG 157A.
FIG. 158A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 158B is a cross-sectional view along line A-A' shown in FIG. 158A; and FIG. 158C is a cross-sectional view along line B-B' shown in FIG 158A.
FIG. 159A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 159B is a cross-sectional view along line A-A' shown in FIG. 159A; and FIG. 159C is a cross-sectional view along line B-B' shown in FIG 159A.
FIG. 160A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 160B is a cross-sectional view along line A-A' shown in FIG. 160A; and FIG. 160C is a cross-sectional view along line B-B' shown in FIG 160A.
FIG. 161A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 161B is a cross-sectional view along line A-A' shown in FIG. 161A; and FIG. 161C is a cross-sectional view along line B-B' shown in FIG 161A.
FIG. 162A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 162B is a cross-sectional view along line A-A' shown in FIG. 162A; and FIG. 162C is a cross-sectional view along line B-B' shown in FIG 162A.
FIG. 163A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 163B is a cross-sectional view along line A-A' shown in FIG. 163A; and FIG. 163C is a cross-sectional view along line B-B' shown in FIG 163A.
FIG. 164A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 164B is a cross-sectional view along line A-A' shown in FIG. 164A; and FIG. 164C is a cross-sectional view along line B-B' shown in FIG 164A.
FIG. 165A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 165B is a cross-sectional view along line A-A' shown in FIG. 165A; and FIG. 165C is a cross-sectional view along line B-B' shown in FIG 165A.
FIG. 166A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 166B is a cross-sectional view along line A-A' shown in FIG. 166A; and FIG. 166C is a cross-sectional view along line B-B' shown in FIG 166A.
FIG. 167A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 167B is a cross-sectional view along line A-A' shown in FIG. 167A; and FIG. 167C is a cross-sectional view along line B-B' shown in FIG 167A.
FIG. 168A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 168B is a cross-sectional view along line A-A' shown in FIG. 168A; and FIG. 168C is a cross-sectional view along line B-B' shown in FIG 168A.
FIG. 169A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 169B is a cross-sectional view along line A-A' shown in FIG. 169A; and FIG. 169C is a cross-sectional view along line B-B' shown in FIG 169A.
FIG. 170A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 170B is a cross-sectional view along line A-A' shown in FIG. 170A; and FIG. 170C is a cross-sectional view along line B-B' shown in FIG 170A.
FIG. 171A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 171B is a cross-sectional view along line A-A' shown in FIG. 171A; and FIG. 171C is a cross-sectional view along line B-B' shown in FIG 171A.
FIG. 172A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 172B is a cross-sectional view along line A-A' shown in FIG. 172A; and FIG. 172C is a cross-sectional view along line B-B' shown in FIG 172A.
FIG. 173A is a plan view showing the method for manufacturing the semiconductor device according to the eighth embodiment; FIG. 173B is a cross-sectional view along line A-A' shown in FIG. 173A; and FIG. 173C is a cross-sectional view along line B-B' shown in FIG 173A.
FIG. 174 is a circuit diagram showing the semiconductor device according to the eighth embodiment.
[Detailed Description]
A method for manufacturing a semiconductor device according to an embodiment includes making a plurality of intermediate structural bodies. Each of the plurality of intermediate structural bodies includes an electrode and a semiconductor member. The electrode is formed on the semiconductor member. A configuration of an upper portion and a configuration of a lower portion are different from each other as viewed from above for each of the plurality of intermediate structural bodies. The method includes arranging the plurality of intermediate structural bodies to be separated from each other by causing one portion selected from the upper portion and the lower portion for each of the intermediate structural bodies to engage with a recess multiply made in an upper surface of a tray by causing the plurality of intermediate structural bodies to tumble on the tray. The one portion is configured to engage with the recess. The other portion selected from the upper portion and the lower portion is configured not to engage with the recess. And, the method includes forming an external electrode connected to the electrode. A portion of the external electrode extends outside the intermediate structural body as viewed from above.
A semiconductor device according to an embodiment includes a semiconductor member having a configuration having ?-fold rotational symmetry (/? being an integer not less than 2), an electrode provided on the semiconductor member and disposed with n-fold rotational symmetry, and an external electrode connected to the electrode with a portion of the external electrode extending outside the semiconductor member as viewed from above.
Embodiments of the invention will now be described with reference to the drawings.
First, a method for manufacturing a semiconductor device common to the following multiple embodiments will be described summarily.
In the embodiments recited below, multiple intermediate structural bodies are made by dividing a substrate after forming electrodes, etc., on the substrate. Semiconductor members are included in the intermediate structural bodies. Then, these intermediate structural bodies are fed onto a tray having an upper surface in which multiple recesses are made; and these intermediate structural bodies are caused to engage with the recesses by causing the intermediate structural bodies to tumble by causing the tray to vibrate. Thereby, the multiple intermediate structural bodies are arranged on the tray to be separated from each other. Subsequently, an external electrode is formed collectively on the intermediate structural bodies in the arranged state; and multiple semiconductor devices are manufactured by performing singulation. Further, in each of the embodiments described below, combinations of the configurations of the recesses and the configurations of the intermediate structural bodies are contrived to fix the intermediate structural bodies in appropriate orientations when arranging the multiple intermediate structural bodies on the tray.
(First embodiment)
A first embodiment will now be described.
In the embodiment, inversion of front and back is prevented by making the front and back of the intermediate structural body asymmetric; and discrepancies are prevented from occurring even when the intermediate structural body rotates by making the configuration of the intermediate structural body rotationally symmetric and by making the dispositions of the electrodes rotationally symmetric.
The semiconductor device according to the embodiment is, for example, an LED (light emitting diode) chip. In this case, the semiconductor member is an LED layer.
First, a method for manufacturing the semiconductor device according to the embodiment will be described.
FIG. 1A to FIG. 22 are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
First, a crystal growth substrate 10 (hereinbelow, also called simply the "substrate 10") is prepared as shown in FIGS. 1A and IB. The substrate 10 is, for example, a silicon wafer, a sapphire wafer, or a silicon carbide (a SiC) wafer, and favorably, a silicon wafer. FIGS. 1A and IB show a portion of a wafer having a disc configuration as the substrate 10. This is similar also for the other drawings described below. Then, for example, an n-type GaN layer 11a, an active layer (not shown), and a p-type GaN layer l i b are epitaxially grown in this order on the substrate 10 by MO-CVD (Metal Organic Chemical Vapor Deposition). Thereby, an LED layer 11 is formed.
Then, as shown in FIGS. 2A and 2B, the LED layer 11 is divided into multiple portions by, for example, selectively removing the LED layer 11 by RIE (Reactive Ion Etching). In other words, high-mesa patterning of the LED layer 11 is performed. When viewed from above, the configuration of the LED layer 11 after dividing is a square and accordingly, has 4-fold rotational symmetry.
Then, as shown in FIGS. 3A and 3B, the p-type GaN layer l i b is removed from the corners of the divided LED layer 11 by, for example, p-mesa patterning by RIE. Thereby, the n-type GaN layer 11a is exposed at the upper surface at the corners of the LED layer 11. On the other hand, the p-type GaN layer l i b is exposed at the upper surface at the cross-shaped portion other than the corners of the LED layer 11. Then, as shown in FIGS. 4A and 4B, by forming a conductive film by sputtering, CVD (Chemical Vapor Deposition : chemical vapor deposition), etc., and selective removal by wet processing, RIE, lift-off, etc., n-electrodes 12a are formed on the n-type GaN layer 11a; and a p-electrode 12b is formed on the p-type GaN layer l ib. At this time, as viewed from above, the dispositions of the n-electrodes 12a and the p-electrode 12b have 4-fold rotational symmetry because the n-electrodes 12a are disposed at the corners of four locations of the square LED layer 11 and the p-electrode 12b is disposed in the region of the cross-shape other than the corners. Then, by forming a passivation film 13 in the region between the p-electrode 12b and the n-electrodes 12a on each of the LED layers 11, the active layer that is exposed at the side surface in the p-mesa patterning is covered. The passivation film 13 is formed to cover the end portions of the n-electrodes 12a and the end portion of the p-electrode 12b. Although the manufacturing of the example is performed in the order of high mesa, and then subsequently p-mesa, electrode formation, and passivation film, the order may be modified as necessary. For example, the high mesa may be last; and the passivation film may be formed prior to the electrode. Also, the p-mesa and/or passivation film formation may be performed between the p-electrode formation and the n-electrode formation. Further, annealing may be performed as necessary after the electrode formation.
Then, as shown in FIGS. 5A and 5B, a trench 14a is made in the upper portion of the substrate 10 from above using, for example, a diamond blade. The trench 14a is made in a lattice configuration between the LED layers 11 to partition the substrate 10 every LED layer 11. However, the trench 14a is made not to pierce the substrate 10. Instead of the diamond blade, the trench 14a may be made by RIE or laser patterning.
Then, as shown in FIGS. 6A and 6B, a trench 14b is made in the lower portion of the substrate 10 from below using, for example, a diamond blade. Instead of the diamond blade, the trench 14b may be made by wet processing, RIE, or laser patterning. The trench 14b is made in a region including the region directly under the trench 14a to be wider than the trench 14a and to communicate with the trench 14a. As a result, the substrate 10 is cut every LED layer 11 by the trench 14a and the trench 14b; and the multiple intermediate structural bodies 16 are made. However, because the trench 14b is wider than the trench 14a, a lower portion 16b of the intermediate structural body 16 cut by the trench 14b is finer than an upper portion 16a of the intermediate structural body 16 cut by the trench 14a. In other words, the outer edge of the lower portion 16b is positioned inside the outer edge of the upper portion 16a as viewed from above.
The order of the process of making the trench 14a shown in FIGS. 5A and 5B and the process of making the trench 14b shown in FIGS. 6A and 6B may be reversed.
On the other hand, an arranging machine 100 is prepared as shown in FIG. 7. A tray 102 that has an upper surface in which multiple recesses 101 are made, and a vibration unit 103 that vibrates the tray 102 are provided in the arranging machine 100. When viewed from above, the configuration of the tray 102 is a configuration corresponding to the exterior form of a wafer, the exterior form of a printed circuit board, or the exterior form of a liquid crystal panel. Also, the recess 101 is arranged in, for example, a matrix configuration. The configuration of each of the recesses 101 is a rectangular parallelepiped configuration; and the size is such that the lower portion 16b of the intermediate structural body 16 engages but the upper portion 16a does not engage.
Then, as shown in FIG. 8A, the multiple intermediate structural bodies 16 are fed onto the tray 102. Then, the vibration unit 103 causes the tray 102 to vibrate. Thereby, the intermediate structural bodies 16 tumble randomly on the tray 102. Then, as shown in FIG. 8B, the intermediate structural bodies 16 of which the lower portion 16b has engaged with the recess 101 do not tumble anymore and are stabilized in that position. Thus, as shown in FIGS. 9A and 9B, ultimately, all of the intermediate structural bodies 16 engage respectively with the recesses 101 ; and the positions are fixed. As a result, the multiple intermediate structural bodies 16 are arranged periodically in a matrix configuration and separated from each other.
Then, as shown in FIG. 10, a porous chuck 105 is brought to a position above the tray 102 and lowered from that position. Thereby, the lower surface of the porous chuck 105 contacts the upper surfaces of the intermediate structural bodies 16. Then, the porous chuck 105 is lifted in the state in which the intermediate structural bodies 16 are held by suction. Thereby, the multiple intermediate structural bodies 16 are lifted collectively and removed from the tray 102. An adhesive film may be used instead of the porous chuck 105.
Then, as shown in FIG. 11, the porous chuck 105 is moved to a position above an adhesive film 20 and lowered. Thereby, the lower surfaces of the intermediate structural bodies 16 contact and are bonded to the adhesive film 20. Subsequently, the porous chuck 105 releases the intermediate structural bodies 16; and the porous chuck 105 is lifted. Thereby, the multiple intermediate structural bodies 16 are transferred collectively from the porous chuck 105 to the adhesive film 20. At this time, the relative positional relationship of the multiple intermediate structural bodies 16 remains in the state of the arrangement on the tray 102. It is favorable for the configuration of the adhesive film 20 to be, for example, a configuration corresponding to the exterior form of a wafer having a large diameter, the exterior form of a printed circuit board, or the exterior form of a liquid crystal panel. Thereby, the subsequent processes can be implemented using existing equipment. Further, a support substrate such as a silicon wafer, etc., may be used instead of the adhesive film 20.
Then, as shown in FIG. 12A, a resin film 21 is formed by coating a resin material on the adhesive film 20 by a method such as spin coating, printing, etc., to bury the intermediate structural bodies 16.
Then, as shown in FIG. 12B, planarization of the upper surface of the resin film 21 is performed as necessary.
Then, as shown in FIG. 13A, the upper portions of the upper portions 16a of the intermediate structural bodies 16 are exposed by etching the resin film 21 by wet processing, dry processing, etc.
Then, as shown in FIG. 13B, an insulating film 22 is formed by, for example, CVD, sputtering, etc. Then, openings 22a and 22b are made by removing the portions of the insulating film 22 corresponding to the regions directly above the n-electrodes 12a and the portion of the insulating film 22 corresponding to the region directly above the p-electrode 12b. Then, a thin seed layer (not shown) is formed by depositing a metal on the entire surface by, for example, sputtering.
Then, as shown in FIGS. 14A and 14B, a resist pattern 23 is formed by forming a resist film on the entire surface and by patterning. The resist pattern 23 has openings in the regions where plating is to be performed in a subsequent process. At this time, the resist pattern 23 is formed to partition the region of each of the intermediate structural bodies 16 including the four n-electrodes 12a as one continuous region 23a and partition the region of each of the intermediate structural bodies 16 including the one p-electrode 12b as one continuous region 23b. More specifically, the region 23a is set to be substantially C-shaped; and the region 23b is set to be substantially T-shaped. The insulating film 22 is not shown in FIG. 14A.
Then, as shown in FIGS. 15A and 15B, a seed layer of a metal such as, for example, copper (Cu), etc., is electroplated as a plating contact line. At this time, copper is plated and a copper film 24 is formed in the regions 23a and 23b where the resist pattern 23 is not provided.
Then, as shown in FIGS. 16A and 16B, a resist pattern 25 is formed by forming a resist film on the entire surface and by patterning. The resist pattern 25 is formed to partition one I-shaped region 25a in a portion of the region 23a and partition one T-shaped region 25b in a portion of the region 23b. Then, for example, a metal such as copper, etc., is electroplated. Thereby, copper is plated and a copper film 26 is formed in the regions 25a and 25b where the resist pattern 25 is not provided.
Then, as shown in FIGS. 17A and 17B, the resist patterns 25 and 23 are removed by wet processing, ashing, etc. Then, the seed layer (not shown) is removed by performing wet processing. Thereby, an n-pillar 27a and a p-pillar 27b are formed of the stacked body of the copper films 24 and 26. The n-pillar 27a is connected to the n-electrodes 12a; and the p-pillar 27b is connected to the p-electrode 12b. Also, a portion of the n-pillar 27a and a portion of the p-pillar 27b extend outside the intermediate structural body 16 as viewed from above.
Then, as shown in FIGS. 18A and 18B, a sealing resin film 28 is formed to cover the n-pillars 27a and the p-pillars 27b by coating a resin material such as, for example, an epoxy resin, etc., on the entire surface by, for example, printing or molding.
Then, the adhesive film 20 is removed as shown in FIG.
19A. For the removal method, an appropriate method can be selected to match the material properties of the adhesive film 20. For example, the peeling from the resin film 21 may be performed by heating or by using a solvent to dissolve a portion of the adhesive film 20. Also, the adhesive film 20 may be removed by wet processing or dry processing. Further, mechanical polishing may be performed in the case where a hard support substrate is used instead of the adhesive film 20. The lower surfaces of the substrates 10 of the intermediate structural bodies 16 are exposed by removing the adhesive film 20.
Then, the resin film 21 is removed as shown in FIG. 19B. For the removal method of the resin film 21 as well, an appropriate method such as a method using a solvent, wet processing, dry processing, etc., can be selected. Thereby, the insulating film 22, the entire lower portions 16b of the intermediate structural bodies 16, and the lower portions of the upper portions 16a of the intermediate structural bodies 16 are exposed.
Then, as shown in FIG. 20A, the crystal growth substrate 10 is removed from the intermediate structural bodies 16. Thereby, the LED layers 11 are exposed. For example, in the case where the substrate 10 is formed of silicon, the substrate 10 can be removed by wet processing or dry processing. On the other hand, in the case where the substrate 10 is formed of sapphire or SiC, removal is not always necessary because of the transparent properties. Then, a micro unevenness (not shown) is formed in the exposed surfaces of the LED layers 11 by, for example, performing surface roughening using a chemical liquid.
Then, as shown in FIG. 20B, a fluorescer film 29 is formed to cover the exposed surfaces of the LED layers 11 by, for example, printing. In the fluorescer film 29, a fluorescer (not shown) is dispersed in a transparent or semi-transparent resin material.
Then, as shown in FIGS. 21A and 21B, the upper surfaces of the n-pillars 27a and the upper surfaces of the p-pillars 27b are exposed by, for example, polishing the upper surface of the sealing resin film 28 by a mechanical unit.
Then, as shown in FIGS. 22A and 22B, dicing of the fluorescer film 29, the insulating film 22, and the sealing resin film 28 is performed using, for example, a diamond blade. Thereby, the multiple semiconductor devices 1 are manufactured.
The configuration of the semiconductor device 1 according to the embodiment will now be described.
As shown in FIGS. 22A and 22B, in each of the semiconductor devices 1, the fluorescer film 29 is provided; and the LED layer 11 is provided as a semiconductor member on the fluorescer film 29. The n-type GaN layer 11a, the active layer (not shown), and the p-type GaN layer lib are stacked in this order in the LED layer 11. As shown in FIG. 6A, the configuration of the LED layer 11 is a square as viewed from above. At the corners of the LED layer 11, the p-type GaN layer l ib is removed; and the n-type GaN layer 11a is exposed at the upper surface. Four n-electrodes 12a that are connected to the n-type GaN layer 11a and one cross-shaped p-electrode 12b that is connected to the p-type GaN layer l ib are provided on the LED layer 11. The dispositions of the n-electrodes 12a and the p-electrode 12b have 4-fold rotational symmetry as viewed from above. The passivation film 13 is provided between the p-electrode 12b and the n-electrodes 12a.
The insulating film 22 is provided to cover the fluorescer film 29, the LED layer 11, the n-electrodes 12a, the p-electrode 12b, and the passivation film 13. The n-pillar 27a and the p-pillar 27b are provided on the insulating film 22. The n-pillar 27a is connected to the n-electrodes 12a via the opening 22a of the insulating film 22; and the p-pillar 27b is connected to the p-electrode 12b via the opening 22b of the insulating film 22. A portion of the n-pillar 27a and a portion of the p-pillar 27b extend outside the LED layer 11 as viewed from above. Then, the sealing resin film 28 is provided on the insulating film 22 to fill around the n-pillar 27a and the p-pillar 27b. The upper surface of the n-pillar 27a and the upper surface of the p-pillar 27b are exposed at the upper surface of the sealing resin film 28. Thereby, the n-pillar 27a and the p-pillar 27b function as external electrodes.
Effects of the embodiment will now be described.
In the embodiment as shown in FIGS. 9A and 9B, the intermediate structural bodies 16 are fed onto the tray 102 of the arranging machine 100; and the intermediate structural bodies 16 are caused to tumble on the tray 102 and engage with the recesses 101 by the vibration unit 103 causing the tray 102 to vibrate. Thereby, the multiple intermediate structural bodies 16 can be aligned with high precision and arranged in a matrix configuration in a mutually-separated state. As a result, in subsequent processes, fine structural bodies can be formed collectively on the multiple intermediate structural bodies 16. Thereby, as shown in FIGS. 17A and 17B, the n-pillar 27a and the p-pillar 27b that extend outside the LED layer 11 are formed; and the multiple semiconductor devices 1 having exterior forms larger than the exterior forms of the LED layers 11 can be manufactured collectively.
By connecting the large n-pillar 27a and the large p-pillar 27b to the LED layer 11, the heat that is generated can be dissipated efficiently from the LED layer 11. The heat dissipation also can be increased when the multiple semiconductor devices 1 are mounted on a mounting substrate because the spacing between the LED layers 11 increases. Further, by forming the semiconductor device 1 to be larger than the LED layer 11, even in the case where the LED layer 11 is downscaled, good handling can be maintained without the handling of the semiconductor device 1 becoming difficult. Further, because the fluorescer film 29 can be provided in a region wider than the LED layer 11, it is easy to, for example, adjust the light distribution properties using a lens, etc. Thus, according to the embodiment, a semiconductor device 1 having high heat dissipation, easy handling, and high extensibility can be manufactured inexpensively.
Then, as shown in FIGS. 6A and 6B, in the intermediate structural body 16, the configuration of the upper portion 16a and the configuration of the lower portion 16b are different from each other; and the lower portion 16b is finer than the upper portion 16a. On the other hand, as shown in FIGS. 8A and 8B, the recess 101 that is made in the tray 102 of the arranging machine 100 has a configuration with which the lower portion 16b of the intermediate structural body 16 engages but with which the upper portion 16a of the intermediate structural body 16 does not engage. Thereby, when arranging the intermediate structural bodies 16, the lower portions 16b always engage with the recesses 101 ; and the intermediate structural bodies 16 are fixed in an orientation in which the LED layers 11 face upward. As a result, the intermediate structural bodies 16 can be prevented from flipping; and all of the intermediate structural bodies 16 can be arranged in a state in which the LED layers 11 face upward.
Also, as shown in FIGS. 6A and 6B, the configuration of the intermediate structural body 16 has 4-fold rotational symmetry (90-degree symmetry) as viewed from above. Therefore, when the lower portion 16b of the intermediate structural body 16 engages with the recess 101, the intermediate structural body 16 can have four orientations in the plane. However, in the intermediate structural body 16, the dispositions of the n-electrodes 12a and the p-electrode 12b also have 4-fold rotational symmetry. Therefore, the positional relationships of the n-electrodes 12a and the p-electrode 12b are equivalent no matter which orientation of the four orientations the intermediate structural body 16 has. Accordingly, it is unnecessary to consider the orientation of the intermediate structural body 16 in the plane.
Thus, in the embodiment, the multiple intermediate structural bodies 16 can be arranged in the appropriate orientation on the tray 102. Thereby, repair work to rearrange intermediate structural bodies 16 disposed at inappropriate orientations becomes unnecessary; and after the arrangement, the transition to the next process can be performed immediately. As a result, the manufacturing cost of the semiconductor device 1 can be reduced even further.
Further, the configuration of the adhesive film 20 can be any configuration because the arrangement and processing of the multiple intermediate structural bodies 16 can be performed inside any region. For example, if the exterior form of the adhesive film 20 is made to match the exterior form of a wafer, the exterior form of a printed circuit board, or the exterior form of a liquid crystal panel, subsequent processes can be implemented using the existing manufacturing line of a semiconductor device, manufacturing line of a printed circuit board, or manufacturing line of a liquid crystal panel. Therefore, the semiconductor device 1 can be manufactured inexpensively and efficiently. Modifications of the first embodiment will now be described.
As described above, in the first embodiment, both the configuration of the intermediate structural body 16 and the dispositions of the n-electrodes 12a and the p-electrode 12b are made to have 4-fold rotational symmetry. Thereby, no matter which orientation of the four orientations the intermediate structural body 16 has, the dispositions of the electrodes are equivalent; and the external electrodes, i.e., the n-piilar 27a and the p-pillar 27b, can be formed collectively. However, the configuration of the intermediate structural body 16 and the electrode dispositions are not limited to 4-fold rotational symmetry; and it is sufficient to have /7-fold rotational symmetry, where n is an integer not less than 2. Also, the types of the electrodes are not limited to the two types. In first to fourth modifications of the first embodiment described below, examples are described in which the symmetry and number of types of the electrodes are different. Also, although an example is illustrated in the first embodiment in which the configuration of the intermediate structural body 16 is made to be front-and-back asymmetric by forming the two types of trenches 14a and 14b in the substrate 10, the method for making the front-and-back asymmetry is not limited thereto. An example is described in a fifth modification of the first embodiment in which the intermediate structural bodies are front-and-back asymmetric by using a bump. Further, examples are described in sixth to eighth modifications of the first embodiment in which a conductive film for electrostatic countermeasures is formed in the outer surface of the intermediate structural body.
(First modification of first embodiment)
First, a first modification will be described .
The semiconductor device according to the modification is, for example, a low pin count IC (Integrated Circuit) chip. FIG. 23 is a plan view showing the intermediate structural body of the modification.
As shown in FIG. 23, the configuration of an intermediate structural body 36a of the modification is a square as viewed from above and accordingly has 4-fold rotational symmetry (90-degree symmetry). Also, four sets of a set made of three types of electrodes 32a, 32b, and 32c are provided in the intermediate structural body 36a. One of each of the electrodes 32a, 32b, and 32c belonging to each set are arranged in one column along each side of the intermediate structural body 36a. Thereby, the electrodes 32a to 32c are disposed with 4-fold rotational symmetry.
In the modification as well, although the intermediate structural body 36a may have four orientations when engaging with the recess of the tray, the positional relationships between the electrodes are equivalent for any orientation. Therefore, the external electrodes, etc., can be formed collectively for multiple intermediate structural bodies 36a. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above.
(Second modification of first embodiment)
A second modification will now be described.
The semiconductor device according to the modification also is, for example, a low pin count IC chip.
FIG. 24 is a plan view showing the intermediate structural body of the modification.
As shown in FIG. 24, the configuration of the intermediate structural body 36b of the modification is a rectangle as viewed from above and accordingly has 2-fold rotational symmetry (180-degree symmetry). Also, two sets of a set made of five types of electrodes 32a to 32e are provided in the intermediate structural body 36b. One of each of the electrodes 32a to 32e belonging to each set are arranged in an L-shaped configuration along two mutually-adjacent sides of the intermediate structural body 36b. Thereby, the electrodes 32a to 32e are disposed with 2-fold rotational symmetry. Therefore, although the intermediate structural body 36b may have two orientations when engaging with the recess of the tray, the positional relationships between the electrodes are equivalent regardless of the orientation of the fixation. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above.
(Third modification of first embodiment)
A third modification will now be described.
The semiconductor device according to the modification also is, for example, a low pin count IC chip.
FIG. 25 is a plan view showing the intermediate structural body of the modification.
As shown in FIG. 25, the configuration of the intermediate structural body 36c of the modification is a rectangle as viewed from above and accordingly has 2-fold rotational symmetry (180-degree symmetry). Also, two sets of a set made of six types of electrodes 32a to 32f are provided in the intermediate structural body 36c. One of each of the electrodes 32a to 32f belonging to each set are arranged on two sides of the center line of the intermediate structural body 36c extending in the longitudinal direction in one column each along the center line. However, the arrangement direction of the electrodes inside each set is reversed between the two sets. Thereby, the electrodes 32a to 32f are disposed with 2-fold rotational symmetry. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above.
(Fourth modification of first embodiment)
A fourth modification will now be described.
The semiconductor device according to the modification is, for example, an LED chip. FIG. 26A is a plan view showing the intermediate structural body of the modification; FIG. 26B is a cross-sectional view along line A-A' shown in FIG. 26A; and FIG. 26C is a perspective view as viewed from the lower side.
As shown in FIGS. 26A to 26C, the configuration of the intermediate structural body 36d of the modification is an equilateral triangle as viewed from above. Also, the lower portion of the intermediate structural body 36d is smaller than the upper portion of the intermediate structural body 36d. Therefore, the configuration of the intermediate structural body 36d is front-and-back asymmetric and has 3-fold rotational symmetry. Also, the configuration of the recess (not shown) made in the upper surface of the tray of the arranging machine is an equilateral triangular prism having a size such that the lower portion of the intermediate structural body 36d engages but the upper portion of the intermediate structural body 36d does not engage. As shown in FIG. 26B, although the widths of the p-type GaN layer lib and the p-electrodes 12b are narrower than the width of the other portion, these can be ignored regarding the engagement with the recess because the thicknesses of the p-type GaN layer l ib and the p-electrodes 12b are exceedingly thin compared to the thickness of the crystal growth substrate 10.
Further, the n-electrodes 12a are provided on the upper surface of the intermediate structural body 36d at each of the three equilateral triangle corners. Also, one hexagonal p-electrode 12b is provided in the region of the upper surface of the intermediate structural body 36d where the n-electrodes 12a are not provided. Therefore, in the intermediate structural body 36d, the dispositions of the n-electrodes 12a and the p-electrode 12b have 3-fold rotational symmetry.
In the modification as well, the intermediate structural body 36d does not flip when being fixed due to the engagement with the recess of the tray because the configuration of the intermediate structural body 36d is front-and-back asymmetric. Also, the positional relationships of the electrodes are equivalent for any orientation of the three orientations in which the intermediate structural body 36d may engage with the recess because the configuration of the intermediate structural body 36d and the dispositions of the electrodes both have 3-fold rotational symmetry. Therefore, the external electrodes, etc., are formed collectively in the state in which the multiple intermediate structural bodies 36d are arranged periodically and separated from each other. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above.
(Fifth modification of first embodiment)
A fifth modification will now be described.
FIG. 27A is a cross-sectional view showing the intermediate structural body of the modification; FIG. 27B is a perspective view showing the intermediate structural body and the recess; and FIG. 27C is a perspective view showing the state in which the intermediate structural body engages with the recess.
The semiconductor device according to the modification is a Zener diode chip.
In the intermediate structural body 36e of the modification as shown in FIGS. 27A to 27C, an electrode 32 is formed on a semiconductor substrate 30; and a bump 33 is bonded onto the upper surface of the electrode 32. A Zener diode is formed in the semiconductor substrate 30 as the semiconductor member; and electrodes are connected to the upper surface and lower surface of the Zener diode. The configuration of the intermediate structural body 36e is a square as viewed from above. Also, the electrodes can be disposed with point symmetry because it is sufficient to provide one on each of the front and back surfaces of the semiconductor substrate 30. On the other hand, multiple recesses 111 are made in the upper surface of a tray 112 of the arranging machine. The configurations of the recesses 111 are rectangular parallelepipeds. The intermediate structural body 36e is engageable with the recess 111 when the orientation of the intermediate structural body 36e is such that the bump 33 is positioned on the upper side. On the other hand, when the orientation is such that the bump 33 is positioned on the lower side, the bump 33 becomes an obstruction; and the intermediate structural body 36e cannot engage with the recess il l. Therefore, the intermediate structural body 36e always is fixed by engaging with the recess 111 in the orientation in which the bump 33 faces upward and is not fixed when flipped. Also, although the intermediate structural body 36e may have four orientations because the configuration of the intermediate structural body 36e has 4-fold rotational symmetry, the positional relationships of the electrodes are equivalent regardless of the orientation because the dispositions of the electrodes are point-symmetric. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above. (Sixth modification of first embodiment)
A sixth modification will now be described.
FIGS. 28A to 28D are cross-sectional views showing the method for manufacturing the semiconductor device according to the modification.
First, the processes shown in FIGS. 1 to FIG. 4 are implemented.
Then, as shown in FIG. 28A, dicing tape 37 is adhered to the passivation film 13 side.
Then, as shown in FIG. 28B, the trench 14b is made by performing wide dicing from the backside, i.e., the crystal growth substrate 10 side.
Then, as shown in FIG. 28C, the trench 14a is made in the bottom surface of the trench 14b by performing narrow dicing in the interior of the trench 14b. The trench 14a is finer than the trench 14b and pierces the substrate 10. Thereby, the substrate 10 is cut apart by the trench 14b and the trench 14a every LED layer 11 ; and the multiple intermediate structural bodies 16 are made.
Then, as shown in FIG. 28D, a conductive film 38 is formed on the lower surfaces of the intermediate structural bodies 16 and on the side surfaces of the intermediate structural bodies 16 from the substrate 10 side. It is favorable for the conductive film 38 to be a continuous film having good coverage. Also, it is favorable for the substrate 10 itself to be conductive and for the contact resistance between the substrate 10 and the conductive film 38 to be low. The conductive film 38 may be formed by, for example, coating a conductive polymer or may be formed by sputtering a metal. Subsequently, the dicing tape 37 is removed.
The subsequent processes are similar to the processes shown in FIGS. 7 to FIG. 22. The greater part of the conductive film 38 is removed with the crystal growth substrate 10 when removing the crystal growth substrate 10 in the process shown in FIG. 20A.
Effects of the modification will now be described.
In the modification, the conductive film 38 is formed on the lower surfaces of the intermediate structural bodies 16 and on the side surfaces of the intermediate structural bodies 16 in the process shown in FIG. 28D. Therefore, the intermediate structural bodies 16 can be prevented from scattering due to static electricity when the multiple intermediate structural bodies 16 are fed onto the arranging machine 100 in the process shown in FIG. 7.
Also, when the conductive film 38 is formed in the process shown in FIG. 28D, the side surfaces of each of the intermediate structural bodies 16 are exposed in the state in which all of the intermediate structural bodies 16 are arranged inside a wafer-shaped region using the dicing tape 37. Therefore, the formation of the conductive film 38 is easy; and the conductive film 38 can be formed in a wide region on the side surfaces of each of the intermediate structural bodies 16.
Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above.
Although an example is illustrated in the modification in which the conductive film 38 is formed after making the trench 14a by the narrow dicing, the conductive film 38 may be formed after making the trench 14b by the wide dicing and prior to making the trench 14a.
(Seventh modification of first embodiment)
A seventh modification will now be described.
FIGS. 29A and 29B are cross-sectional views showing a method for manufacturing the semiconductor device according to the modification.
First, after implementing the processes shown in FIGS. 1 to FIG. 4, the process shown in FIG. 28A is implemented.
Then, as shown in FIG. 29A, laser light 150 is irradiated into the interior of the trench 14b so that the focal point fits the bottom surface of the trench 14b. Thereby, a crystal alteration portion 39 is formed by the crystal of the silicon of which the substrate 10 is formed being altered by the energy of the laser light 150 at a portion of the crystal growth substrate 10 corresponding to the region directly under the trench 14b.
Then, as shown in FIG. 29B, the dicing tape 37 is caused to expand (expand). Thereby, the substrate 10 is cleaved at the crystal alteration portion 39; and the substrate 10 is singulated into the multiple intermediate structural bodies 16. Subsequently, similarly to the sixth modification described above, the conductive film 38 (referring to FIG. 28C) is formed on the lower surfaces of the intermediate structural bodies 16 and on the side surfaces of the intermediate structural bodies 16.
The subsequent processes are similar to the processes shown in FIGS. 7 to FIG. 22.
According to the modification, compared to dicing by a blade, the number of chips per production unit can be increased because the width of the laser light 150 can be finer. This effect is particularly large for an extremely small chip such as an LED chip.
Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the sixth modification of the first embodiment described above.
(Eighth modification of first embodiment)
An eighth modification will now be described.
FIGS. 30A and 30B are cross-sectional views showing a method for manufacturing the semiconductor device according to the modification.
First, after implementing the processes shown in FIGS. 1 to FIG. 4, the processes shown in FIGS. 28A and 28B are implemented; and the process shown in FIG. 29A is implemented.
Then, as shown in FIG. 30A, the conductive film 38 is formed from the substrate 10 side. At this time, the conductive film 38 is formed on the lower surface of the substrate 10 and on the inner surface of the trench 14b.
Then, as shown in FIG. 30B, the dicing tape 37 is caused to expand. Thereby, the substrate 10 is cleaved at the crystal alteration portion 39; and the multiple intermediate structural bodies 16 are singulated.
The subsequent processes are similar to the processes shown in FIGS. 7 to FIG. 22.
According to the modification, the formation of the conductive film 38 is easier compared to the seventh modification described above because the conductive film 38 is formed prior to singulating the substrate 10. On the other hand, according to the seventh modification, because the conductive film 38 is formed after the substrate 10 is singulated, the conductive film 38 can be formed in a wider region of the side surfaces of the intermediate structural bodies 16.
Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the seventh modification of the first embodiment described above. (Second embodiment)
A second embodiment will now be described.
Similarly to the first embodiment described above, the embodiment is an example in which inversion of front and back is prevented by making the front and back of the intermediate structural body asymmetric. However, as the reverse of the first embodiment, the upper portion of the intermediate structural body is made to be smaller than the lower portion of the intermediate structural body so that the upper portion engages with the recess of the tray. Also, in the embodiment, unlike the first embodiment, the intermediate structural body is fixed with respect to the tray by engaging with the recess in a designated orientation by making the dispositions of the electrodes rotationally asymmetric and making the configuration of the intermediate structural body rotationally asymmetric.
First, a method for manufacturing the semiconductor device according to the embodiment will be described.
FIG. 31A to FIG. 44B are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
First, as shown in FIGS. 31A and 31B, multiple semiconductor circuits 41 are formed on a semiconductor substrate 40. The semiconductor substrate 40 is, for example, a silicon wafer; and the semiconductor circuit 41 includes an interconnect layer formed on a semiconductor element such as a transistor, etc. When viewed from above, the semiconductor circuits 41 are arranged in a matrix configuration; and the configuration of each of the semiconductor circuits 41 is a rectangle. In the specification, squares also are included in " rectangle."
Then, electrodes 42 are formed on each of the semiconductor circuits 41. For example, ten electrodes 42 are formed and arranged in an annular configuration along the outer edge of the semiconductor circuit 41. The roles of the ten electrodes that are formed on one semiconductor circuit 41 are different from each other. Accordingly, the dispositions of the electrodes 42 are rotationally asymmetric.
Then, as shown in FIGS. 32A and 32B, a bump 43 made of, for example, gold (Au) is formed on one of the electrodes 42 formed on each of the semiconductor circuits 41 using, for example, a stud bump bonder (not shown). At this time, the bump 43 is provided on the electrode 42 that is formed at the same position on each of the semiconductor circuits 41. Also, because the electrodes 42 are disposed at a position distal to the central axis C of the semiconductor circuit 41, the bump 43 is disposed at a position distal to the central axis C of the semiconductor circuit 41.
Then, as shown in FIGS. 33A and 33B, a trench 44a is made in the upper surface of the semiconductor substrate 40 using a relatively wide blade; and then, a trench 44b is made in the bottom surface of the trench 44a using a relatively fine blade. The trench 44b is deeper and finer than the trench 44a. The upper portion of the semiconductor substrate 40 is partitioned every semiconductor circuit 41 by the trenches 44a and 44b.
Then, as shown in FIGS. 34A and 34B, the back surface of the semiconductor substrate 40 is polished until the trench 44b is reached. Thereby, the semiconductor substrate 40 is singulated every semiconductor circuit 41 to become multiple intermediate structural bodies 46. The order of the processes of making the trenches 44a and 44b shown in FIGS. 33A and 33B and the process of polishing the back surface shown in FIGS. 34A and 34B may be reversed. In each of the intermediate structural bodies 46, the integrated circuit as the semiconductor member includes the semiconductor substrate 40 and the semiconductor circuit 41.
An upper portion 46a of the intermediate structural body 46, i.e., the portion on the side where the electrodes 42 are formed, is subdivided by the relatively wide trench 44a and therefore is relatively fine. On the other hand, a lower portion 46b of the intermediate structural body 46, i.e., the portion on the semiconductor substrate 40 side, is subdivided by the relatively fine trench 44b and therefore is relatively wide. Accordingly, the configuration of the intermediate structural body 46 is front-and-back asymmetric. Also, the configuration of the intermediate structural body 46 is rotationally asymmetric because the bump 43 is provided at a position distal to the central axis C of the intermediate structural body 46.
Then, as shown in FIG. 35A, the multiple intermediate structural bodies 46 are fed onto a tray 122 of an arranging machine. Multiple recesses 121 are formed in a matrix configuration in the upper surface of the tray 122. The configuration of each of the recesses 121 is a two-step configuration; and a lower portion 121b that has a rectangular parallelepiped configuration smaller than an upper portion 121a is made at one location at the bottom surface of the upper portion 121a having a rectangular parallelepiped configuration. The upper portion 121a of the recess 121 has a configuration with which the portion of the upper portion 46a of the intermediate structural body 46 other than the bump 43 engages; and the lower portion 121b has a configuration in which the bump 43 is contained. On the other hand, the lower portion 46b of the intermediate structural body 46 does not engage with the recess 121 because the lower portion 46b of the intermediate structural body 46 is larger than the upper portion 46a of the intermediate structural body 46. Thereby, as shown in FIG. 35B, the upper portion 46a of the intermediate structural body 46 engages with the recess 121. At this time, the orientation of the intermediate structural body 46 is constrained to one orientation because it is necessary for the bump 43 to fit in the lower portion 121b.
Then, as shown in FIG. 36, an adhesive film 51 that is provided on the lower surface of a support substrate 50 is adhered over the intermediate structural bodies 46 from above and subsequently lifted. Thereby, the intermediate structural bodies 46 are removed from the recesses 121. Then, as shown in FIGS. 37A and 37B, up and down are inverted. Thereby, the multiple intermediate structural bodies 46 are transferred onto the support substrate 50 with the adhesive film 51 interposed while maintaining the positional relationship between the multiple intermediate structural bodies 46.
Then, as shown in FIG. 38A, a resin film 52 is formed on the entire surface of the adhesive film 51 by, for example, coating. The resin film 52 covers the intermediate structural body 46.
Then, as shown in FIG. 38B, the upper portion of the upper portion 46a of the intermediate structural body 46 is exposed by causing the resin film 52 to recede by etching.
Then, as shown in FIGS. 39A and 39B, an insulating film 53 is formed by, for example, coating. Then, openings 53a are made by removing portions of the insulating film 53 corresponding to the regions directly above the electrodes 42. The electrodes 42 are exposed inside the openings 53a of the insulating film 53. Also, the bump 43 protrudes from the upper surface of the insulating film 53 via the opening 53a.
Then, as shown in FIGS. 40A and 40B, a thin seed layer 54 is formed by, for example, depositing a metal onto the entire surface by sputtering. Then, a resist film is formed on the entire surface; and a resist pattern (not shown) is formed by patterning. The resist pattern has openings in regions where plating is to be performed in a subsequent process. Then, the seed layer 54 of a metal such as, for example, copper (Cu), etc., is electroplated as a plating contact line. At this time, copper is plated in the regions where the resist pattern is not provided. Then, the resist pattern is removed by wet processing, ashing, etc. Then, the portion of the seed layer 54 exposed at the no-copper-plating portion is removed by performing wet processing.
Thereby, re-interconnect layers 55 made of, for example, copper are formed on the insulating film 53. An interconnect portion 55a having an arm-like configuration and a pad portion 55b having a disc configuration are provided in each of the re-interconnect layers 55. One end of each of the interconnect portions 55a is connected to each of the electrodes 42 via each of the openings 53a. The electrode 42 to which the bump 43 is bonded is connected to the interconnect portion 55a via the bump 43. Or, the interconnect portion 55a and the electrode 42 are directly connected in a form in which the bump 43 is enveloped in the interior of the interconnect portion 55a. Also, as viewed from above, at least a portion of the other end of the interconnect portion 55a and the entire pad portion 55b extend outside the intermediate structural body 46.
Then, as shown in FIGS. 41A and 41B, a solder resist 56 is formed by depositing an insulating material. Then, openings 56a are made by removing the regions of the solder resist 56 directly above the pad portions 55b by exposing and developing the solder resist 56.
Then, as shown in FIGS. 42A and 42B, the back surface of the support substrate 50 is made thin as necessary by polishing. The support substrate 50 may be peeled.
Then, as shown in FIGS. 43A and 43B, BGA (Ball Grid
Array) balls 57 are formed on the pad portions 55b of the re-interconnect layers 55. The BGA balls 57 protrude from the upper surface of the solder resist 56 via the openings 56a.
Then, as shown in FIGS. 44A and 44B, singulation is performed every semiconductor substrate 40 by dicing the support substrate 50, the adhesive film 51, the resin film 52, the insulating film 53, and the solder resist 56. Thereby, the multiple semiconductor devices 2 are manufactured.
The configuration of the semiconductor device 2 according to the embodiment will now be described.
As shown in FIGS. 44A and 44B, as viewed from above, the configuration of the intermediate structural body 46 is a rectangle; and the upper portion 46a is smaller than the lower portion 46b. In the intermediate structural body 46, the semiconductor circuit 41 is provided on the semiconductor substrate 40; a plurality, e.g., ten, electrodes 42 are provided on the semiconductor circuit 41; and the bump 43 made of, for example, gold is provided on one of the electrodes 42.
The resin film 52 is provided around the intermediate structural body 46; and the insulating film 53 is provided on the resin film 52 and on the intermediate structural body 46. The number of re-interconnect layers 55 provided on the insulating film 53 substantially corresponds to the electrodes 42. Each of the re-interconnect layers 55 is made of, for example, copper; and the interconnect portion 55a and the pad portion 55b are formed as one body. When viewed from above, a portion of the interconnect portion 55a and the entire pad portion 55b extend outside the semiconductor substrate 40 and the semiconductor circuit 41. The interconnect portions 55a are connected to the electrodes 42 via the openings 53a of the insulating film 53; and the pad portions 55b are connected to the BGA balls 57 provided on the pad portions 55b. The solder resist 56 that is insulative is provided on the insulating film 53 to cover the entire re-interconnect layers 55 and the lower portions of the BGA balls 57.
Effects of the embodiment will now be described.
In the embodiment, similarly to the first embodiment described above, the semiconductor device 2 has high heat dissipation and easy handling because the re-interconnect layers 55 extend outside the region directly above the semiconductor substrate 40, and the BGA balls 57 can be disposed outside the region directly above the semiconductor substrate 40. Also, in the case where the semiconductor device 2 is a versatile device, the package size can be standardized. Further, even in the case where the number of electrodes 42 and the number of BGA balls 57 corresponding to the electrodes 42 are high, the size and pitch necessary for the substrate mounting can be ensured because the BGA balls 57 can be disposed in a region greater than the size of the semiconductor device 2.
Further, as shown in FIGS. 35A and 35B, the multiple intermediate structural bodies 46 can be arranged easily in a matrix configuration and separated from each other in one orientation by making the configuration of the intermediate structural body 46 front-and-back asymmetric and rotationally asymmetric and making the configuration of the recess 121 of the tray 122 to be a configuration with which the upper portion 46a of the intermediate structural body 46 engages and the lower portion 46b of the intermediate structural body 46 does not engage. As a result, the multiple semiconductor devices 2 can be manufactured collectively; and the manufacturing cost can be reduced. Otherwise, the effects of the embodiment are similar to those of the first embodiment described above.
(Third embodiment)
A third embodiment will now be described.
The embodiment is an example in which the configuration of the intermediate structural body is rotationally asymmetric and mirror-image asymmetric. Further, the configuration of the recess of the tray also is a configuration that fits the intermediate structural body. Thereby, when the intermediate structural body engages with the recess of the tray, the orientation of the intermediate structural body is constrained to one orientation. In other words, the intermediate structural body is not flipped and is oriented in a designated direction.
FIG. 45 is a plan view showing the method for manufacturing the semiconductor device according to the embodiment.
FIG. 45 shows a process in which multiple intermediate structural bodies 61 are singulated. As shown in FIG. 45, as viewed from above, the configuration of the intermediate structural body 61 is a trapezoid that is not an isosceles trapezoid. Therefore, the configuration of the intermediate structural body 61 is rotationally asymmetric and mirror-image asymmetric. It is difficult to singulate the intermediate structural body 61 by only blade dicing, but it is sufficient to use, for example, laser patterning or RIE. Otherwise, the configuration, the manufacturing method, and the effects of the embodiment are similar to those of the first embodiment described above.
(Modification of third embodiment)
A modification of the third embodiment will now be described.
FIG. 46 is a plan view showing the method for manufacturing the semiconductor device according to the modification.
In the modification as shown in FIG. 46, the configuration of an intermediate structural body 62 is made to be a pentagonal prism configuration formed of a rectangular parallelepiped having a so-called chamfer. This also makes the configuration of the intermediate structural body 62 rotationally asymmetric and mirror-image asymmetric. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the third embodiment described above. (Fourth embodiment)
A fourth embodiment will now be described.
The embodiment is an example in which two intermediate structural bodies selected from the intermediate structural bodies described in the first to third embodiments or modifications of the first to third embodiments described above are provided together in one package. In this case, two types of recesses are made in the tray of the arranging machine; only a first intermediate structural body engages with a first recess; a second intermediate structural body is made not to engage with the first recess; only the second intermediate structural body engages with a second recess; and the first intermediate structural body is made not to engage with the second recess.
First, a method for manufacturing the semiconductor device according to the embodiment will be described.
FIG. 47 to FIG. 58 are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
As shown in FIG. 47, the embodiment is an example in which the intermediate structural body 36d (referring to FIGS. 26A to 26C) shown in the fourth modification of the first embodiment and the intermediate structural body 36e (referring to FIGS. 27A to 27C) shown in the fifth modification of the first embodiment described above are provided together in one package. The intermediate structural body 36d includes an LED layer as the semiconductor member; and the intermediate structural body 36e includes a Zener diode as the semiconductor member. Therefore, the semiconductor device 4 (referring to FIG. 58) that is manufactured in the embodiment is an LED package including a Zener diode. Also, as described above, the configuration of the intermediate structural body 36d and the dispositions of the electrodes have 3-fold rotational symmetry; and the configuration of the intermediate structural body 36e and the dispositions of the electrodes have 4-fold rotational symmetry.
First, an arranging machine is prepared in which a tray 132 is provided. Multiple regions corresponding to the semiconductor devices 4 to be manufactured are arranged in the tray 132 in a matrix configuration; and each of two types of recesses 131d and 131e are formed in each region. The positions of the recesses 131d and 131e inside each region are the same between the regions. The configuration of the recess 131d is a triangular prism configuration and is a configuration with which the lower portion of the intermediate structural body 36d engages but the upper portion of the intermediate structural body 36d and the intermediate structural body 36e do not engage. The configuration of the recess 131e is a rectangular parallelepiped configuration and is a configuration with which the lower portion of the intermediate structural body 36e, i.e., the portion on the side where the bump 33 is not provided, engages but the upper portion of the intermediate structural body 36e, i.e., the portion on the side where the bump 33 is provided, and the intermediate structural body 36d do not engage.
Then, the multiple intermediate structural bodies 36d and the multiple intermediate structural bodies 36e are fed onto the tray 132. Then, the intermediate structural bodies 36d and 36e are caused to tumble on the tray 132 by the vibration unit (not shown) causing the tray 132 to vibrate.
Thereby, as shown in FIG. 48, the lower portion of the intermediate structural body 36d engages with the recess 131d of the tray 132; and the lower portion of the intermediate structural body 36e engages with the recess 131e. As a result, the intermediate structural bodies 36d and 36e are fixed in a constant positional relationship to form a pair; and the pair is arranged in a matrix configuration. At this time, because the configurations of the recess 131d and the intermediate structural body 36d have 3-fold rotational symmetry, the intermediate structural body 36d can have three orientations; but the positional relationships of the electrodes are equivalent for any of the orientations. Similarly, because the configuration of the intermediate structural body 36e has 4-fold rotational symmetry, the intermediate structural body 36e can have four orientations; but the positional relationships of the electrodes are equivalent for any of the orientations.
Then, as shown in FIGS. 49A and 49B, the intermediate structural bodies 36d and 36e that are arranged on the tray 132 are picked up using, for example, a porous chuck (not shown), etc., and are transferred onto the support substrate 50. The adhesive film 51 is adhered to the support substrate 50. In FIG. 49A, the frames illustrated by the double dot-dash lines show the regions that become the semiconductor devices 4. This is similar for subsequent drawings as well.
Then, as shown in FIGS. 50A and 50B, the resin film 52 is formed on the entire surface of the adhesive film 51 to bury the intermediate structural bodies 36d and 36e. Then, the upper portions of the intermediate structural bodies 36d and the upper portions of the intermediate structural bodies 36e are exposed by etching the resin film 52. Then, the openings 53a are made in the regions directly above the n-electrodes 12a, the p-electrodes 12b, and the electrodes 32 by forming and patterning the insulating film 53.
Then, a seed layer 64 made of, for example, copper is formed on the entire surface; a resist pattern (not shown) is formed on the seed layer 64; and copper is electroplated. Thereby, re-interconnect layers 65a and 65b are formed. The re-interconnect layers 65a are connected to the n-electrodes 12a of the intermediate structural bodies 36d via the seed layer 64. The re-interconnect layers 65b are connected to the p-electrodes 12b of the intermediate structural bodies 36d via the seed layer 64 and are connected to the electrodes 32 of the intermediate structural bodies 36e via the seed layer 64 and the bumps 33.
Then, a resist pattern (not shown) is formed again; and copper plating is performed. Then, the resist pattern is removed by ashing, etc. ; and the exposed portion of the seed layer 64 is removed by etching, etc. Thereby, n-pillars 67a and p-pillars 67b are formed. The n-pillars 67a are connected to the re-interconnect layers 65a. The p-pillars 67b are connected to the re-interconnect layers 65b.
Then, as shown in FIG. 51, a sealing resin film 68 is formed on the entire surface to bury the n-pillars 67a and the p-pillars 67b.
Then, as shown in FIGS. 52A and 52B, front and back are inverted; and the support substrate 50 (referring to FIG. 51) and the adhesive film 51 (referring to FIG. 51) are removed. Then, the resin film 52 (referring to FIG. 51) is removed. Thereby, the crystal growth substrates 10 and the semiconductor substrates 30 are exposed from the insulating film 53.
Then, as shown in FIGS. 53A and 53B, a protective film 69 is formed to cover the exposed portions of the semiconductor substrates 30. Then, the LED layers 11 are exposed by removing the crystal growth substrates 10 (referring to FIG. 52B). Then, as shown in FIGS. 54A and 54B, a fine unevenness is formed in the exposed surfaces of the LED layers 11 by performing frosting.
Then, a transparent insulating film 71 is formed on the entire surface as shown in FIGS. 55A and 55B. Then, a photoresist (not shown) is formed; and after exposing and developing the photoresist, the transparent insulating film 71 is patterned by RIE; and anisotropic etching such as RIE, etc., is performed using the transparent insulating film 71 as a hard mask. Thereby, via holes 72a are made in portions of the portions of the transparent insulating film 71 and the insulating film 53 corresponding to regions directly above the re-interconnect layers 65a; and via holes 72b are made in portions of the portions of the transparent insulating film 71 and the protective film 69 corresponding to regions directly above the semiconductor substrates 30.
Then, as shown in FIGS. 56A and 56B, ESD (Electrostatic Discharge) protection interconnects 73 are formed in a region to link the interiors of the via holes 72a and 72b and the regions on the transparent insulating film 71 directly above the via holes 72a and 72b.
Then, as shown in FIG. 57A, a fluorescer film 74 is formed on the entire surface of the transparent insulating film 71 to cover the ESD protection interconnects 73.
Then, as shown in FIG. 57B, the lowers surface of the n-pillars 67a and the lower surfaces of the p-pillars 67b are exposed by polishing the sealing resin film 68 from the lower surface (back surface) side.
Then, singulation by dicing is performed as shown in FIG. 58. Thereby, the multiple semiconductor devices 4 are manufactured.
The configuration of the semiconductor device 4 according to the embodiment will now be described.
FIG. 59 is a drawing comparing the configurations of the LED layer and the semiconductor substrate of the embodiment.
As shown in FIG. 58, the configuration of the semiconductor device 4 is a rectangular parallelepiped configuration. The sealing resin film 68, the insulating film 53, the transparent insulating film 71, and the fluorescer film 74 are stacked in this order from the bottom upward in the semiconductor device 4. The n-pillar 67a, the p-pillar 67b, the re-interconnect layer 65a, and the re-interconnect layer 65b are provided inside the sealing resin film 68.
The n-pillar 67a and the re-interconnect layer 65a are connected to each other and pierce the sealing resin film 68. The p-pillar 67b and the re-interconnect layer 65b are connected to each other and pierce the sealing resin film 68. The lower surface of the n-pillar 67a and the lower surface of the p-pillar 67b are exposed at the lower surface of the semiconductor device 4. The seed layer 64 is provided on the upper surfaces of the re-interconnect layers 65a and 65b.
The LED layer 11 is provided inside the insulating film 53. The p-type GaN layer l ib, the active layer (not shown), and the n-type GaN layer 11a are stacked in this order from the bottom upward in the LED layer 11; and frosting of the upper surface of the LED layer 11 is performed. The n-type GaN layer 11a is connected to the re-interconnect layer 65a via the n-electrodes 12a; and the p-type GaN layer l ib is connected to the re-interconnect layer 65b via the p-electrode 12b. When viewed from below, the configuration of the LED layer 11 is an equilateral triangle; and the n-electrodes 12a are disposed at the corners of the equilateral triangle. Also, the bump 33 is provided inside the insulating film 53 and is connected to the re-interconnect layer 65b.
The semiconductor substrate 30 that is included in the Zener diode is provided inside the fluorescer film 74. The lower surface of the semiconductor substrate 30 is connected to the re-interconnect layer 65b via the electrode 32 and the bump 33. When viewed from below, the configuration of the semiconductor substrate 30 is a square; and the dispositions of the electrode 32 are point-symmetric. Also, the end portions of the side surfaces and upper surface of the semiconductor substrate 30 are covered with the protective film 69. The transparent insulating film 71 covers the upper surfaces of the insulating film 53, the LED layer 11, and the protective film 69. Also, the ESD protection interconnect 73 is provided between the transparent insulating film 71 and the fluorescer film 74. One end of the ESD protection interconnect 73 is connected to the re-interconnect layer 65a through the via hole 72a made in the insulating film 53; and the other end of the ESD interconnect 73 is connected to the upper surface of the semiconductor substrate 30 through the via hole 72b made in the protective film 69.
By such a configuration, a first current path of (the n-pillar 67a - the re-interconnect layer 65a - the n-electrodes 12a - the LED layer 11 - the p-electrode 12b - the re-interconnect layer 65b - the p-pillar 67b) and a second current path of (the n-pillar 67a - the re-interconnect layer 65a - the ESD protection interconnect 73 - the semiconductor substrate 30 - the electrode 32 - the bump 33 - the re-interconnect layer 65b - the p-pillar 67b) are formed in parallel between the n-pillar 67a and the p-pillar 67b which are external electrodes. As a result, an LED package including a Zener diode is realized in which the LED layer 11 and the semiconductor substrate 30 are connected in parallel between the n-pillar 67a and the p-pillar 67b.
Also, as shown in FIG. 59, when the outer edge of the
LED layer 11 used as the first semiconductor member as viewed from above and the outer edge of the semiconductor substrate 30 used as the second semiconductor member as viewed from above are overlaid virtually, the outer edge of the LED layer 11 and the outer edge of the semiconductor substrate 30 always intersect. Further, as viewed from below, a portion of the n-pillar 67a extends outside the LED layer 11 ; and a portion of the p-pillar 67b extends outside the LED layer 11 and the semiconductor substrate 30.
Effects of the embodiment will now be described.
In the embodiment as shown in FIG. 47, the electrode dispositions and configuration of the intermediate structural body 36d including the LED layer 11 are made to have 3-fold rotational symmetry; and the electrode dispositions and configuration of the intermediate structural body 36e including the Zener diode are made to have 4-fold rotational symmetry. Also, the recess 131d of the tray 132 is made to have a configuration with which only the lower portion of the intermediate structural body 36d is engageable; and the recess 131e is made to have a configuration with which only the lower portion of the intermediate structural body 36e is engageable. Thereby, the intermediate structural bodies 36d and 36e can be arranged periodically in a state in which the intermediate structural bodies 64d and 64e are held with a mutually-separated constant positional relationship and equivalent electrode dispositions are realized. As a result, in the multiple semiconductor devices 4, the re-interconnect layers 65a and 65b, the n-pillars 67a, the p-pillars 67b, the ESD protection interconnects 73, etc., can be formed collectively; and the manufacturing cost can be reduced. Otherwise, the manufacturing method, the configuration, and the effects of the embodiment are similar to those of the first or second embodiments described above.
(Fifth embodiment)
A fifth embodiment will now be described.
The embodiment is an example in which two intermediate structural bodies are provided together in one package similarly to the fourth embodiment described above but differs in that the configurations of the intermediate structural bodies as viewed from above both are rectangles. In this case, selective engagement with the recesses of the tray is possible by providing the lengths of each side of the rectangle with a prescribed relationship.
FIG. 60A is a plan view showing the method for manufacturing the semiconductor device according to the embodiment; FIG. 60B is a plan view showing the semiconductor device; and FIG. 60C is a drawing showing the relationship between the configurations of the semiconductor members.
In the embodiment as shown in FIG. 60A, the two types of intermediate structural bodies 81a and 81b are fed onto a tray 142 of an arranging machine. A semiconductor member 82a is provided in the entire upper surface of the intermediate structural body 81a; and a semiconductor member 82b is provided in the entire upper surface of the intermediate structural body 81b. The configurations of the intermediate structural bodies 81a and 81b are front-and-back asymmetric.
When viewed from above, the configurations of the intermediate structural bodies 81a and 81b both are rectangles; but the dimensions of the configurations are different from each other. When viewed from above, a long side La of the intermediate structural body 81a is longer than a long side Lb of the intermediate structural body 81b, and a short side Wb of the intermediate structural body 81b is longer than a short side Wa of the intermediate structural body 81a, where the length of the long side of the intermediate structural body 81a is La, the length of the short side is Wa, the length of the long side of the intermediate structural body 81b is Lb, and the length of the short side is Wb. In other words, the lengths La, Wa, Lb, and Wb satisfy the relationships of Formulas ( 1) and (2) recited below. As described above, although squares are included in "rectangle," in the case where the configuration of the intermediate structural body is a square, the length of the short side and the length of the long side of the square are equal to each other.
La > Lb (1) Wa < Wb (2) On the other hand, in the upper surface of the tray 142, a recess 141a with which the lower portion of the intermediate structural body 81a engages and the intermediate structural body 81b does not engage, and a recess 141b with which the lower portion of the intermediate structural body 81b engages and the intermediate structural body 81a does not engage are made.
By using such a tray 142, the intermediate structural bodies 81a and 81b can be arranged regularly. Then, the multiple semiconductor devices 5 are manufactured by forming external electrodes 83a and 83b collectively by a method similar to that of the fourth embodiment described above.
The configuration of the semiconductor device 5 according to the embodiment will now be described.
As shown in FIG. 60B, in the semiconductor device 5 after completion, the semiconductor members 82a and 82b are provided to be separated from each other. The semiconductor member 82a includes, for example, an integrated circuit; and the semiconductor member 82b includes, for example, a passive element. Also, in the semiconductor device 5, the external electrodes 83a that are connected to the semiconductor member 82a are multiply provided; and the external electrodes 83b that are connected to the semiconductor member 82b are multiply provided. When viewed from above, a portion of each of the external electrodes 83a extends outside the semiconductor member 82a; and a portion of each of the external electrodes 83b extends outside the semiconductor member 82b. The external electrodes 83a and 83b are exposed at the outer surface of the semiconductor device 5. Further, an electrode may be formed to provide a direct electrical connection between the semiconductor member 82a and the semiconductor member 82b. Also, in this case, a portion of the electrical connection unit may be provided to be exposed at the outer surface of the semiconductor device 5.
As shown in FIG. 60C, the outer edge of the semiconductor member 82a as viewed from above and the outer edge of the semiconductor member 82b as viewed from above always intersect when these outer edges are overlaid virtually. Otherwise, the manufacturing method, the configuration, and the effects of the embodiment are similar to those of the fourth embodiment described above. (Modification of fifth embodiment)
A modification of the fifth embodiment will now be described .
Although an example is illustrated in the fifth embodiment described above in which one semiconductor device is manufactured by providing two intermediate structu ra l bodies together, the number of intermediate structural bodies that are provided together is not limited to two and may be three or more. In such a case as well, if the configurations of the intermediate structural bodies are selected so that the outer edges of the intermediate structural bodies as viewed from above always intersect when the outer edges are overlaid on each other, each of the recesses of the tray can have a designated intermediate structural body that is caused to selectively engage with the recess; and the arrangement can be performed in a state in which a prescribed positional relationship is realized for the multiple types of intermediate structural bodies.
FIGS. 61A to 61D are drawings comparing configurations of the intermediate structural bodies of the modification .
In the modification as shown in FIGS. 61A to 61D, the number of types of intermediate structural bodies is m (m being an integer not less than 2) ; and all of the configurations of the intermediate structural bodies are rectangles as viewed from above. Also, Formulas (3) and (4) recited below are satisfied, where the length of the long side of the /th (/ being an integer not less than 1 and not more than (m-l)) intermediate structural body 86/ is L„- and the length of the short side of the intermediate structural body 86, is W,.
Li > Li + 1 (3)
Figure imgf000059_0001
In the modification as well, effects similar to those of the fifth embodiment described above can be obtained. Otherwise, the manufacturing method, the configuration, and the effects of the modification are similar to those of the fifth embodiment described above.
(Sixth embodiment)
A sixth embodiment will now be described.
The embodiment is an example in which a reflective film is formed at the side of the LED layer.
First, a method for manufacturing the semiconductor device according to the embodiment will be described.
FIG. 62A to FIG. 89B are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
First, as shown in FIGS. 62A and 62B, the n-type GaN layer 11a, an active layer 11c, and the p-type GaN layer lib are epitaxially grown in this order on the crystal growth substrate 10 by, for example, MO-CVD. Thereby, the LED layer 11 is formed.
Then, as shown in FIGS. 63A and 63B, high-mesa patterning of the LED layer 11 is performed by, for example, RIE. Thereby, the LED layer 11 is divided into multiple portions arranged in a matrix configuration. The configuration of each of the portions is a rectangle as viewed from above. Then, p-mesa patterning of the LED layers 11 is performed. Thereby, at the corners of four locations of each of the divided LED layers 11, the n-type GaN layer 11a is exposed at the upper surface by removing the p-type GaN layer lib and the active layer; and the p-type GaN layer lib is exposed at the upper surface of the remaining cross-shaped portion. Then, by forming a conductive film by, for example, PVD, etc., and patterning by, for example, wet processing, lift-off, etc., the n-electrodes 12a are formed on the n-type GaN layer 11a; and the p-electrode 12b is formed on the p-type GaN layer l ib.
Then, as shown in FIGS. 64A and 64B, the passivation film 13 is formed on the entire surface by, for example, CVD. Then, the passivation film 13 is patterned by, for example, RIE to have openings on the n-electrodes 12a and on the p-electrode 12b.
Then, as shown in FIGS. 65A and 65B, a reflective metal layer 161 is formed on the entire surface by, for example, depositing a metal material having a high optical reflectance such as aluminum (Al), silver (Ag), platinum (Pt), etc., by PVD. The reflective metal layer 161 is formed on the upper surfaces of the LED layers 11 and is connected to the n-electrodes 12a and the p-electrodes 12b via the openings of the passivation film 13. Also, the reflective metal layer 161 is formed on the side surfaces of the LED layers 11. Then, the reflective metal layer 161 is patterned to be divided into portions connected to the n-electrodes 12a and portions connected to the p-electrodes 12b.
Then, as shown in FIGS. 66A and 66B, the structural bodies that include the LED layers 11, etc., formed on the substrate 10 are adhered to the dicing tape 37. At this time, the upper surfaces of the structural bodies, i.e., the reflective metal layer 161, are bonded to the dicing tape 37. Then, the dicing tape 37 and the structural bodies are inverted; and the trench 14b is made in a lattice configuration in the lower surface of the substrate 10, i.e., the surface on the side where the LED layers 11 are not formed, by using, for example, a diamond blade (not shown).
Then, as shown in FIGS. 67A and 67B, laser light, e.g., YAG laser light, is irradiated inside the trench 14b. At this time, the focal point of the laser light is set to be positioned in the interior of the substrate 10. Thereby, a portion of the substrate 10 is modified to form a modified portion 162. The crystal of the substrate 10 of the modified portion 162 degrades and becomes brittle. Then, an antistatic film 163 is formed on the entire surface. As the antistatic film 163, a conductive film having good adhesion with the substrate 10 and a surface that does not oxidize easily is favorable; and, for example, a titanium (Ti)/titanium nitride (TiN) stacked film, a metal film such as a gold (Au) film or a platinum (Pt) film, or a conductive resin film can be used. The metal film can be formed by, for example, PVD or plating; and the conductive resin film can be formed by, for example, spraying, etc. The modified portion 162 may be formed by irradiating laser light after forming the antistatic film 163.
Then, as shown in FIGS. 68A and 68B, the dicing tape 37 is caused to expand (expand). Thereby, the modified portion 162, which is more brittle than the surroundings, fractures; and the substrate 10 is singulated every LED layer 11. As a result, an intermediate structural body 164 is made every LED layer 11.
In the intermediate structural body 164 as shown in FIGS. 69A to 69C, the LED layer 11 is provided on the substrate 10. The n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer l ib are stacked in this order in the LED layer 11. The upper surface is formed of the n-type GaN layer 11a at the corners of the LED layer 11 and is formed of the p-type GaN layer lib at the other portions.
The n-electrodes 12a are provided on the upper surface of the n-type GaN layer 11a; and the p-electrode 12b is provided on the upper surface Of the p-type GaN layer l ib. The passivation film 13 is provided to cover the side surfaces and upper surface of the LED layer 11; and the reflective metal layer 161 is provided on the outer side of the passivation film 13. The portion of the reflective metal layer 161 positioned in the region directly above the p-type GaN layer l ib is connected to the p-electrode 12b via the opening of the passivation film 13; and the portion of the reflective metal layer 161 positioned in the region directly above the n-type GaN layer 11a and at the sides of the LED layer 11 is connected to the n-electrodes 12a via the openings of the passivation film 13.
On the other hand, a rectangular parallelepiped protrusion is formed in the lower surface of the substrate 10. Also, the antistatic film 163 is provided on the lower surface of the substrate 10. Hereinbelow, the protrusion of the substrate 10 and the antistatic film 163 provided on the lower surface of the protrusion and on the side surface of the protrusion are called a lower portion 164a of the intermediate structural body 164; and the other portions are called an upper portion 164b of the intermediate structural body 164. The lower portion 164a is finer than the upper portion 164b.
On the other hand, as shown in FIG. 70, a tray 166 of the arranging machine 100 (referring to FIG. 7) is prepared. A recess 167 is made in the upper surface of the tray 166. The recess 167 is arranged in a matrix configuration as viewed from above. The recess 167 has a two-step configuration; and a lower portion 167b is formed in the lower surface central portion of an upper portion 167a. The configurations of the upper portion 167a and the lower portion 167b are rectangular parallelepipeds. The lower portion 167b of the recess 167 has a configuration with which the lower portion 164a of the intermediate structural body 164 engages but with which the upper portion 164b does not engage. Also, the size of the upper portion 167a of the recess 167 is such that the upper portion 164b of the intermediate structural body 164 engages. Then, the intermediate structural bodies 164 are fed onto the tray 166; and the tray 166 is caused to vibrate. Thereby, the intermediate structural bodies 164 tumble randomly on the tray 166.
Thereby, as shown in FIGS. 71A and 71B, the intermediate structural bodies 164 are fixed inside the recesses 167 and no longer tumble due to the lower portions 164a of the intermediate structural bodies 164 engaging with the lower portions 167b of the recesses 167 and the lower portions of the upper portions 164b of the intermediate structural bodies 164 engaging with the upper portions 167a of the recesses 167. As a result, the multiple intermediate structural bodies 164 are arranged periodically in a matrix configuration and separated from each other. At this time, the vertical orientation of the intermediate structural bodies 164 is fixed. The planar configuration of the intermediate structural body 164 has 2-fold rotational symmetry and can have two mutually-opposite orientations because the planar configuration is a rectangle; but problems do not occur because the electrode dispositions of the intermediate structural body 164 also have 2-fold rotational symmetry.
Then, as shown in FIG. 72, after bonding the upper surfaces of the intermediate structural bodies 164 to a heat-resistant tape 169, the intermediate structural bodies 164 are extracted from the recesses 167 of the tray 166 by moving the heat-resistant tape 169 in a direction away from the tray 166. At this time, the p-mesa portions are buried inside the heat-resistant tape 169 because the stepped portions of the p-mesa portions of the intermediate structural bodies 164 are about several microns and the thickness of the heat-resistant tape 169 is about several millimeters. A wafer support system in which an adhesive layer is formed on a support substrate may be used instead of the heat-resistant tape 169.
Then, as shown in FIG. 73, the intermediate structural bodies 164 are disposed on the heat-resistant tape 169 by inverting up and down.
Then, as shown in FIG. 74, a reinforcing insulating resin film 170 is formed on the heat-resistant tape 169 to bury the intermediate structural bodies 164 by, for example, coating or molding. The reinforcing insulating resin film 170 favorably is a resin film that reflects light and can be, for example, a resin film into which titanium oxide is mixed. The reinforcing insulating resin film 170 may be transparent. In this case, the resin material favorably is a material that is transparent and has excellent lightfastness such as, for example, a silicone resin, an acrylic resin, etc., but may be an epoxy resin.
Then, as shown in FIG. 75, the heat-resistant tape 169 is peeled from the reinforcing insulating resin film 170. At this time, the intermediate structural bodies 164 remain inside the reinforcing insulating resin film 170; and the p-mesa portions are exposed.
Then, as shown in FIG. 76, up and down of the reinforcing insulating resin film 170 are inverted; and the p-mesa portions of the intermediate structural bodies 164 are exposed at the upper surface of the reinforcing insulating resin film 170.
Then, as shown in FIG. 77, an insulating film 171 is formed on the entire surface of the reinforcing insulating resin film 170 to cover the exposed portions of the intermediate structural bodies 164; and openings are made to expose portions of the reflective metal layers 161. The insulating film 171 may be an inorganic film or may be an organic film. In the case where the inorganic film is used as the insulating film 171, for example, the film formation is performed by PVD or CVD; and the patterning is performed by photolithography and RIE. In the case where the organic film is used as the insulating film 171, for example, the film formation is performed by spin coating; if photosensitive, the patterning is performed by exposing and developing; and if non-photosensitive, the patterning is performed by developing by wet processing after photolithography or by forming a hard mask and performing RIE after photolithography.
Then, as shown in FIG. 78, a seed layer 172 is formed on the entire surface by, for example, PVD. For example, a titanium (Ti)/copper (Cu) stacked film or an aluminum (AI)/copper (Cu) stacked film is formed by sputtering.
Then, as shown in FIGS. 79A and 79B, a thick film resist 173 is formed and patterned. Thereby, the thick film resist 173 is patterned into a lattice configuration and partitioned into regions where the n-electrodes 12a are exposed and regions where the p-electrodes 12b are exposed. Then, copper (Cu) is formed on the entire surface by electroplating. Thereby, a copper interconnect layer 174 is formed in the regions where the thick film resist 173 is not formed. At this time, the copper interconnect layer 174 is partitioned by the thick film resist 173 because the upper portion of the thick film resist 173 protrudes from the upper surface of the copper interconnect layer 174. Then, each of the portions of the partitioned copper interconnect layer 174 is connected to the n-electrodes 12a or the p-electrode 12b via the seed layer 172.
Then, as shown in FIGS. 80A and 80B, a thick film resist 175 is formed on the copper interconnect layer 174 to cover the thick film resist 173; and patterning is performed. Then, copper pillars 176 are formed in the regions where the thick film resist 175 is not formed by forming copper (Cu) on the entire surface by electroplating. The copper pillars 176 are connected to the copper interconnect layer 174.
Then, as shown in FIGS. 81A and 81B, the thick film resist 175 and the thick film resist 173 (referring to FIG. 80B) are removed by performing wet processing or ashing processing. Then, the seed layer 172 is removed by etching using the copper pillars 176 and the copper interconnect layer 174 as a mask. Thereby, the copper interconnect layer 174 and the copper pillar 176 that are connected to the n-electrodes 12a and the copper interconnect layer 174 and the copper pillar 176 that are connected to the p-electrode 12b are electrically isolated from each other.
Then, as shown in FIGS. 82A and 82B, a reinforcing insulating resin film 178 is formed on the reinforcing insulating resin film 170 to cover the copper interconnect layer 174 and the copper pillars 176 by, for example, coating an epoxy resin, a polyimide resin, or a silicone resin by screen printing or compression molding.
Then, as shown in FIGS. 83A and 83B, the reinforcing insulating resin film 170 is thinned by polishing from the lower surface side by, for example, a method of a back side grinder, etc. Thereby, the lower portions 164a of the intermediate structural bodies 164 also are removed; and the substrate 10 is exposed.
Then, as shown in FIGS. 84A and 84B, up and down are inverted. Then, the crystal growth substrate 10 is removed as shown in FIGS. 85A and 85B. For example, in the case where the substrate 10 is formed of silicon, the removal is performed by wet etching or dry etching. In the case where the substrate 10 is formed of sapphire, an excimer laser is irradiated and lift-off is performed; or the substrate 10 is polished until the substrate 10 vanishes in the process shown in FIGS. 84A and 84B described above. Thereby, the LED layers 11 are exposed.
Then, as shown in FIGS. 86A and 86B, surface roughening of the LED layers 11 is performed. For example, an unevenness may be formed by performing wet etching using a strongly alkaline aqueous solution and utilizing the crystal anisotropy of the n-type GaN layer 11a; or the unevenness may be formed by performing etching such as RIE, etc., using a patterned mask.
Then, as shown in FIGS. 87A and 87B, a fluorescer film 179 is formed on the reinforcing insulating resin film 170 by, for example, screen printing, etc.
Then, as shown in FIGS. 88A and 88B, the reinforcing insulating resin film 178 is thinned by polishing from the lower surface side by, for example, a method of a back side grinder, etc. Thereby, the copper pillars 176 are exposed.
Then, as shown in FIGS. 89A and 89B, singulation is performed every LED layer 11 by cutting the reinforcing insulating resin film 178, the insulating film 171, the reinforcing insulating resin film 170, and the fluorescer film 179 by a method such as, for example, blade dicing, laser dicing, etc. Thus, the semiconductor device 6 according to the embodiment is manufactured.
The configuration and the effects of the semiconductor device 6 according to the embodiment will now be described.
Also, in the semiconductor device 6 as shown in FIGS. 89A and 89B, the reflective metal layers 161 are provided below and at the side of the LED layers 11. Therefore, the light extraction efficiency of the semiconductor device 6 is high.
Otherwise, the configuration, the manufacturing method, and the effects of the embodiment are similar to those of the first embodiment described above.
(Modification of sixth embodiment)
A modification of the sixth embodiment will now be described.
FIG. 90A to FIG. 92B are drawings showing the method for manufacturing the semiconductor device according to the modification.
First, the processes shown in FIGS. 62A and 62B to FIGS.
86A and 86B are implemented.
Then, as shown in FIGS. 90A and 90B, transparent members 181 having dome configurations are formed to cover the LED layers 11. For example, a transparent resin material or transparent glass material having a semi-liquid state is formed in a dome configuration by dropping by a dispenser or by imprinting.
Then, as shown in FIGS. 91A and 91B, the fluorescer film 179 is formed on the reinforcing insulating resin film 170 to cover the transparent members 181.
Then, as shown in FIGS. 92A and 92B, the copper pillars 176 are exposed by backgrinding the reinforcing insulating resin film 178. Then, singulation is performed every LED layer 11. Thereby, the semiconductor device 6a according to the modification is manufactured.
In the semiconductor device 6a according to the modification as shown in FIG. 92B, the light that is emitted from the LED layer 11 is incident substantially perpendicularly to the interface between the transparent member 181 and the fluorescer film 179. Therefore, little of the light undergoes a total internal reflection at the interface; and the light extraction efficiency is high.
Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the sixth embodiment described above.
Other than the LED layer 11, a Zener diode may be mounted in the sixth embodiment and the modification of the sixth embodiment described above.
(Seventh embodiment)
A seventh embodiment will now be described.
In the embodiment, an LED chip and a Zener diode chip are mounted inside one semiconductor device and connected to each other using a dummy chip.
First, a method for manufacturing the semiconductor device according to the embodiment will be described.
FIG. 93A to FIG. 124C are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
First, as shown in FIGS. 93A and 93B, the n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer lib are epitaxially grown in this order on the crystal growth substrate 10 by, for example, MO-CVD. Thereby, the LED layer 11 is formed.
Then, as shown in FIGS. 94A and 94B, p-mesa patterning and high-mesa patterning of the LED layer 11 are performed by, for example, RIE. Thereby, the n-type GaN layer 11a is exposed at the upper surface at the corners of four locations of the LED layer 11 ; and the p-type GaN layer lib is exposed at the upper surface of the remaining cross-shaped portion. Then, the p-electrode 12b is formed on the p-type GaN layer lib. At this stage, the n-electrodes 12a are not formed.
Then, as shown in FIGS. 95A and 95B, the passivation film 13 is formed; and openings are made on the exposed surface of the n-type GaN layer 11a by, for example, RIE. The passivation film 13 covers the p-electrode 12b, the p-type GaN layer lib, the side surface of the n-type GaN layer 11a, and the upper surface of the substrate 10 and leaves a portion of the n-type GaN layer 11a exposed.
Then, as shown in FIGS. 96A and 96B, the n-electrodes 12a are formed on the passivation film 13. The n-electrodes 12a are formed in the regions other than the region directly above the central portion of the p-electrode 12b and are connected to the n-type GaN layer 11a via openings of the passivation film 13. Also, as viewed from above, the end portions of the n-electrodes 12a are made to overlap the end portions of the p-electrode 12b. However, the n-electrodes 12a are separated from the p-electrode 12b by the passivation film 13.
Then, as shown in FIGS. 97A and 97B, the structural bodies in which the LED layers 11 , etc., are formed on the substrate 10 are adhered to the dicing tape 37. At this time, the upper surfaces of the structural bodies, i.e., the n-electrodes 12a, are bonded to the dicing tape 37. Then, the dicing tape 37 and the structural bodies are inverted ; and the trench 14b is made in a lattice configuration in the lower surface of the substrate 10, i.e., the surface on the side where the LED layers 11 are not formed, by using, for example, a diamond blade (not shown) .
Then, as shown in FIGS. 98A and 98B, the modified portion 162 is formed by irradiating laser light toward the interior of the trench 14b so that the focal point of the laser light is positioned in the interior of the substrate 10. Then, the antistatic film 163 is formed on the entire surface. The order of the laser modification and the formation of the antistatic film 163 may be reversed .
Then, as shown in FIGS. 99A and 99B, the dicing tape 37 is caused to expand (expand) . Thereby, the relatively brittle the modified portion 162 fractures; and the substrate 10 is singulated every LED layer 11. As a result, the intermediate structural body that includes the LED layer 11 (hereinbelow, called the "LED chip 184") is made.
In the LED chip 184 as shown in FIGS. 100A to lOOC, the LED layer 11 is provided on the substrate 10. The n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer l i b are stacked in this order in the LED layer 11. The configuration of the LED layer 11 is a rectangle as viewed from above. The p-type GaN layer l ib and the active layer 11c are removed at the four corners of the LED layer 11 to expose the n-type GaN layer 11a at the upper surface. The p-type GaN layer lib is exposed at the upper surface in the cross-shaped region other than the four corners of the LED layer 11.
The p-electrode 12b is provided on the upper surface of the p-type GaN layer l ib. The passivation film 13 is provided to cover the p-electrode 12b and the side surfaces and upper surface of the LED layer 11 and leave the exposed surfaces of the n-type GaN layer 11a exposed. The n-electrodes 12a are provided on the passivation film 13. The n-electrodes 12a are disposed to cover the upper surface of the end portion and side surface of the stacked body made of the LED layer 11 and the p-electrode 12b and are connected to the n-type GaN layer 11a via openings of the passivation film 13. When viewed from above, the end portions of the p-electrode 12b and the end portions of the n-electrodes 12a overlap with the passivation film 13 interposed.
A rectangular parallelepiped protrusion is formed at the lower surface of the substrate 10. Also, the antistatic film 163 is provided on the lower surface of the substrate 10 and on the side surface of the substrate 10. Hereinbelow, the protrusion of the substrate 10 and the antistatic film 163 provided on the lower surface of the protrusion and on the side surface of the protrusion are called a lower portion 184a of the LED chip 184; and the other portions are called an upper portion 184b of the LED chip 184. The lower portion 184a is finer than the upper portion 184b.
On the other hand, as shown in FIGS. 100D to 100H, other than the LED chip 184, a Zener diode chip 186 (hereinbelow, also called the "ZD chip 186") and a conduction dummy chip 196 are prepared.
The configuration of the ZD chip 186 is a substantially rectangular parallelepiped and is a square as viewed from above. The conduction dummy chip 196 is a rectangular parallelepiped block made of a high electrical conductivity material such as copper (Cu), etc. In the ZD chip 186 as shown in FIGS. 100D to 100 F, an n-type semiconductor layer 189 is provided on a back surface electrode 188. The n-type semiconductor layer 189 is connected to the back surface electrode 188. A recess is made in the central portion of the upper surface of the n-type semiconductor layer 189; a p-type semiconductor layer 190 is provided on the inner surface of the recess; and an n-type semiconductor layer 191 is provided on the p-type semiconductor layer 190. Thereby, the n-type semiconductor layer 189 and the n-type semiconductor layer 191 are separated from each other with the p-type semiconductor layer 190 interposed. A semiconductor block 192 is formed of the n-type semiconductor layer 189, the p-type semiconductor layer 190, and the n-type semiconductor layer 191.
An insulative passivation film 193 is provided on the end portion of the semiconductor block 192; and a front surface electrode 194 is provided on the central portion of the semiconductor block 192. The front surface electrode 194 is connected to the n-type semiconductor layer 191. Accordingly, the back surface electrode 188, the n-type semiconductor layer 189, the p-type semiconductor layer 190, the n-type semiconductor layer 191, and the front surface electrode 194 are connected in series in this order in the ZD chip 186.
Then, as shown in FIG. 101 and FIGS. 102A and 102B, a tray 200 of the arranging machine 100 (referring to FIG. 7) is prepared. A recess 201 with which the LED chip 184 engages, a recess 202 with which the ZD chip 186 engages, and a recess 203 with which the conduction dummy chip 196 engages are made in the upper surface of the tray 200. The recess 201 is arranged in a matrix configuration as viewed from above. Also, the recess 202 is disposed on one longitudinal-direction side of the recess 201 as viewed from the recess 201; and the recess 203 is disposed on one lateral-direction side of the recess 201 as viewed from the recess 201. One unit includes one recess 201, one recess 202, and one recess 203.
The recess 201 has a two-step configuration; and a lower portion 201b is formed in the lower surface central portion of an upper portion 201a. The configurations of the upper portion 201a and the lower portion 201b are rectangular parallelepipeds. The lower portion 201b of the recess 201 has a configuration with which the lower portion 184a of the LED chip 184 engages but the upper portion 184b does not engage; and the size of the upper portion 201a of the recess 201 is such that the upper portion 184b of the LED chip 184 engages. The configurations of the recess 202 and the recess 203 are rectangular parallelepipeds. Also, the depths of the recesses 201 to 203 are set so that the upper surface of the LED chip 184 engaging with the recess 201, the upper surface of the ZD chip 186 engaging with the recess 202, and the upper surface of the conduction dummy chip 196 engaging with the recess 203 are at the same height.
As shown in FIGS. 102A and 102B, the LED chip 184, the ZD chip 186, and the conduction dummy chip 196 (hereinbelow, also generally called the "chips") are simultaneously fed onto the tray 200; and the tray 200 is caused to vibrate. Thereby, after the chips are caused to tumble on the tray 200, the LED chip 184 engages with the recess 201; the ZD chip 186 engages with the recess 202; and the conduction dummy chip 196 engages with the recess 203.
At this time, because the recess 201 has a two-step configuration, the vertical orientation of the LED chip 184 is restricted; and the upper portion 184b is disposed higher than the lower portion 184a. On the other hand, the vertical orientation of the ZD chip 186 is not restricted, the ZD chip 186 may have the two orientations of the orientation in which the front surface electrode 194 is positioned on the upper side and the orientation in which the back surface electrode 188 is positioned on the upper side. Similarly, the vertical orientation of the conduction dummy chip 196 also is not restricted. However, problems do not occur because the functions of the ZD chip 186 are vertically symmetric and the conduction dummy chip 196 is a single block. Then, as shown in FIG. 103, the upper surfaces of the chips are bonded to the heat-resistant tape 169; and these chips are extracted from the tray 200 by moving the heat-resistant tape 169 in a direction away from the tray 200. A wafer support system in which an adhesive layer is formed on a support substrate may be used instead of the heat-resistant tape 169.
Then, as shown in FIG. 104, up and down are inverted; and the chips are disposed on the heat-resistant tape 169. At this time, the upper surface of the ZD chip 186 is positioned lower than the stepped surface of the boundary between the lower portion 184a and the upper portion 184b of the LED chip 184 and positioned lower than the upper surface of the conduction dummy chip 196.
Then, a bump 205, e.g., a gold stud bump, is adhered to the electrode on the upper surface side of the ZD chip 186, i.e., the back surface electrode 188 or the front surface electrode 194. At this time, the upper end of the bump 205 is positioned higher than the interface between the substrate 10 and the LED layer 11 of the LED chip 184 and positioned higher than the upper surface of the conduction dummy chip 196.
Then, as shown in FIGS. 105A and 105B, the reinforcing insulating resin film 170 is formed on the heat-resistant tape 169 to bury the chips by, for example, coating or molding. Subsequently, the heat-resistant tape 169 is peeled from the reinforcing insulating resin film 170.
Then, as shown in FIGS. 106A and 106B, up and down of the reinforcing insulating resin film 170 are inverted. Thereby, the p-mesa portion of the LED chip 184, the surface of the ZD chip 186 on the side where the bump 205 is not bonded, and one surface of the conduction dummy chip 196 are exposed at the upper surface of the reinforcing insulating resin film 170.
Then, as shown in FIGS. 107A to 107C, the insulating film 171 is formed on the entire surface on the reinforcing insulating resin film 170 to cover each of the exposed portions of the chips and is provided with openings so that portions of the electrodes of each of the chips are exposed. More specifically, a p-side via 171a, a ZD via 171b, and an n-interconnect via 171c are made in the insulating film 171; the central portion of the p-electrode 12b of the LED chip 184 is exposed at the p-side via 171a; the central portion of the back surface electrode 188 or front surface electrode 194 of the ZD chip 186 is exposed at the ZD via 171b; and the central portion of the conduction dummy chip 196 is exposed at the n-interconnect via 171c.
Then, as shown in FIGS. 108A to 108C, the seed layer
172 is formed on the entire surface by, for example, PVD. Then, the thick film resist 173 is formed and patterned. At this time, the thick film resist 173 is patterned into a lattice configuration so that the LED chip 184 and the ZD chip 186 are partitioned in one block and the conduction dummy chip 196 is partitioned in one block.
Then, as shown in FIGS. 109A to 109C, copper (Cu) is formed on the entire surface by electroplating, etc. Thereby, the copper interconnect layer 174 is formed in the regions where the thick film resist 173 is not formed. At this time, the copper interconnect layer 174 is divided into multiple portions because the upper portion of the thick film resist 173 protrudes from the upper surface of the copper interconnect layer 174. Also, the copper interconnect layer 174 is connected to the p-electrode 12b of the LED chip 184, the back surface electrode 188 or front surface electrode 194 of the ZD chip 186, and the conduction dummy chip 196 via the seed layer 172. On the other hand, the n-electrodes 12a of the LED chip 184 are not connected to the copper interconnect layer 174 because the n-electrodes 12a are covered with the insulating film 171.
Then, as shown in FIGS. 110A to HOC, the thick film resist 175 is formed on the copper interconnect layer 174 to cover the thick film resist 173; and the thick film resist 175 is patterned. At this time, the thick film resist 175 is formed in a lattice configuration to cover the region where the LED chip 184 and the ZD chip 186 are disposed and leave exposed the region where the conduction dummy chip 196 is disposed and the region positioned on the side opposite to the region where the conduction dummy chip 196 is disposed as viewed from the region where the LED chip 184 and the ZD chip 186 are disposed. Then, by forming copper (Cu) on the entire surface by electroplating, the copper pillars 176 are formed in the regions where the thick film resist 175 is not formed. The copper pillars 176 are connected to the copper interconnect layer 174.
Then, the thick film resist 175 and the thick film resist
173 are removed as shown in FIGS. 111A to 111C. Then, the seed layer 172 is selectively removed by etching using the copper pillars 176 and the copper interconnect layer 174 as a mask. Thereby, the copper interconnect layer 174 and the copper pillar 176 that are connected to the p-electrode 12b of the LED chip 184 and the back surface electrode 188 or front surface electrode 194 of the ZD chip 186 and the copper interconnect layer 174 and the copper pillar 176 that are connected to the conduction dummy chip 196 are electrically isolated from each other.
Then, as shown in FIGS. 112A to 112C, the reinforcing insulating resin film 178 is formed on the entire surface.
Then, as shown in FIGS. 113A to 113C, the reinforcing insulating resin film 170 is thinned by polishing from the lower surface side by, for example, a back side grinder. Thereby, the lower portion 184a of the LED chip 184 is removed; and the substrates 10 is exposed. Also, the bump 205 that is bonded to the ZD chip 186 is exposed. Further, the surface of the conduction dummy chip 196 opposite to the surface connected to the copper interconnect layer 174 is exposed.
Then, as shown in FIGS. 114A to 114C, up and down are inverted.
Then, the crystal growth substrate 10 of the LED chip 184 is removed as shown in FIGS. 115A to 115C. Thereby, the n-type GaN layer 11a of the LED layer 11 is exposed.
Then, as shown in FIGS. 116A to 116C, the portion of the passivation film 13 of the LED chip 184 disposed at the side of the LED layer 11 is removed. Thereby, the n-electrodes 12a are exposed.
Then, as shown in FIGS. 117A to 117C, an n-side interconnect film 207 is formed by depositing a conductive material on the entire surface. It is favorable for the upper surface of the n-side interconnect film 207 to be formed of a material having a high optical reflectance, e.g., silver (Ag), aluminum (Al), etc.
Then, as shown in FIGS. 118A to 118C, a hard mask film
208 is formed on the entire surface. Favorably, the hard mask film 208 covers and protects the n-side interconnect film 207 and is an inorganic film having high light-shielding properties, e.g., by being formed by depositing silicon oxide (SiO2) by CVD. Then, the hard mask film 208 is patterned into a matrix configuration and removed from the region where dicing is to be performed in a subsequent process.
Then, as shown in FIGS. 119A to 119C, the n-side interconnect film 207 is patterned by etching the n-side interconnect film 207 using the hard mask film 208 as a mask. Thereby, the n-side interconnect film 207 is partitioned at every portion connected to one LED chip 184, one ZD chip 186, and one conduction dummy chip 196 and is removed from on top of the LED layer 11.
Then, as shown in FIGS. 120A to 120C, a passivation film
209 is formed on the entire surface. The passivation film 209 favorably is an inorganic film having high light-shielding properties and can be formed by, for example, depositing silicon oxide (Si02) by CVD. Then, the LED layer 11 is exposed by patterning the passivation film 209.
Then, as shown in FIGS. 121A to 121C, surface roughening of the LED layer 11 is performed. For example, an unevenness is formed by utilizing the crystal anisotropy of the n-type GaN layer 11a by performing wet etching using a strongly alkaline aqueous solution, or an unevenness is formed by etching such as RIE, etc., using a patterned mask. Then, as shown in FIGS. 122A to 122C, the fluorescer film 179 is formed on the reinforcing insulating resin film 170 by, for example, screen printing, etc.
Then, as shown in FIGS. 123A to 123C, the copper pillars 176 are exposed by polishing the reinforcing insulating resin film 178 from the lower surface side by, for example, a back side grinder.
Then, as shown in FIGS. 124A to 124C, singulation is performed every LED layer 11 by cutting the reinforcing insulating resin film 178, the insulating film 171, the reinforcing insulating resin film 170, and the fluorescer film 179 by a method such as, for example, blade dicing, laser dicing, etc. Thus, the semiconductor device 7 according to the embodiment is manufactured.
The configuration and the operations of the semiconductor device according to the embodiment will now be described.
FIG. 125 is a circuit diagram showing the configuration of the semiconductor device according to the embodiment.
As shown in FIGS. 124A to 124C, the reinforcing insulating resin film 178, the reinforcing insulating resin film 170, and the fluorescer film 179 are stacked in this order in the semiconductor device 7. Two sets of external electrodes made of the copper interconnect layer 174 and the copper pillar 176 are provided inside the reinforcing insulating resin film 178. One LED chip 184, one ZD chip 186, and one conduction dummy chip 196 are provided inside the reinforcing insulating resin film 170. The n-side interconnect film 207 is selectively provided between the reinforcing insulating resin film 170 and the fluorescer film 179.
Then, the n-side interconnect film 207 is connected to the upper surface of the conduction dummy chip 196, the n-electrodes 12a of the LED chip 184, and one selected from the back surface electrode 188 and the front surface electrode 194 of the ZD chip 186. The lower surface of the conduction dummy chip 196 is connected to the copper interconnect layer 174 on the cathode side. On the other hand, the copper interconnect layer 174 on the anode side is connected to the p-electrode 12b of the LED chip 184 and the other selected from the back surface electrode 188 and the front surface electrode 194 of the ZD chip 186.
Thereby, as shown in FIG. 125, the LED chip 184 and the ZD chip 186 are connected in parallel between the copper pillar 176 on the cathode side and the copper pillar 176 on the anode side. As a result, normally, a current flows in the path of (the copper pillar 176 on the anode side - the copper interconnect layer 174 on the anode side - the p-electrode 12b of the LED chip 184 - the p-type GaN layer lib of the LED layer 11 - the active layer 11c - the n-type GaN layer 11a - the n-electrodes 12a - the n-side interconnect film 207 - the conduction dummy chip 196 - the copper interconnect layer 174 on the cathode side - the copper pillar 176 on the cathode side); and the LED layer 11 emits light. Also, the LED chip 184 is protected by the ZD chip 186 allowing a current to flow when an excessive voltage is applied between the copper pillar 176 on the anode side and the copper pillar 176 on the cathode side. At this time, the conduction dummy chip 196 functions as an interconnect member piercing the reinforcing insulating resin film 170 in the thickness direction.
Effects of the embodiment will now be described.
In the semiconductor device 7 according to the embodiment, the p-electrode 12b made of a metal having a high optical reflectance is provided in the region directly under the central portion of the LED layer 11 ; the n-electrodes 12a made of a metal having a high optical reflectance are provided in the regions directly under the side and peripheral portion of the LED layer 11 ; and the end portions of the p-electrode 12b and the end portions of the n-electrodes 12a overlap as viewed from above. Therefore, the light that is emitted from the LED layer 11 sideward and downward is reflected reliably by the p-electrode 12b and the n-electrodes 12a and emitted upward.
Also, because the n-side interconnect film 207 made of a metal having a high optical reflectance is provided below the fluorescer film 179, the light that is emitted downward from the fluorescer film 179 is reflected by the n-side interconnect film 207 and emitted upward. Therefore, the light extraction efficiency of the semiconductor device 7 is high.
Otherwise, the configuration, the manufacturing method, and the effects of the embodiment are similar to those of the sixth embodiment described above. (First modification of seventh embodiment)
A first modification of the seventh embodiment will now be described.
Although the p-electrode 12b is formed previously on the LED layer 11 in the seventh embodiment described above, the n-electrode 12a is formed previously in the modification.
FIG. 126A to FIG. 128B are drawings showing a method for manufacturing the semiconductor device according to the modification.
First, as shown in FIGS. 93A and 93B, the LED layer 11 is formed by epitaxially growing the n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer lib in this order on the crystal growth substrate 10.
Then, as shown in FIGS. 126A and 126B, the LED layer
11 is divided into multiple portions by performing high-mesa patterning of the LED layer 11. Then, the n-type GaN layer
11a is exposed at the corners of the LED layer 11 by performing p-mesa patterning of the LED layer 11. Then, the n-electrodes
12a are formed on the exposed surface of the n-type GaN layer
11a.
Then, as shown in FIGS. 127A and 127B, the passivation film 13 is formed; and openings are made in the regions directly above the n-electrodes 12a and the region directly above the p-type GaN layer l ib.
Then, as shown in FIGS. 128A and 128B, the p-electrode 12b that is connected to the p-type GaN layer l ib and an extension n-electrode 12c that is connected to the n-electrodes 12a are formed to be insulated from each other by forming a metal film on the entire surface and by patterning. The extension n-electrode 12c is formed not only in the region directly above the n-electrodes 12a but also on the side surface of the LED layer 11 and on the upper surface of the substrate 10.
Subsequently, the processes shown in FIGS. 97A and 97B to FIGS. 124A to 124C are implemented.
According to the modification, the light that is emitted from the LED layer 11 can be utilizing efficiently because the extension n-electrode 12c is disposed on the side surface of the LED layer 11. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the modification are similar to those of the seventh embodiment described above.
(Second modification of seventh embodiment)
A second modification of the seventh embodiment will now be described.
The modification is an example in which a ZD chip and a conduction dummy chip are combined after previously arranging an LED chip.
FIG. 129A to FIG 140B are drawings showing the method for manufacturing the semiconductor device according to the modification.
First, an LED chip 184 such as that shown in FIGS. 100A to lOOC is made by implementing the processes shown in FIGS. 93A and 93B to FIGS. 99A and 99B. Also, a conduction dummy chip 196 such as that shown in FIGS. 100G and 100H is made. On the other hand, as shown in FIGS. 129A to 129C, the bump 205 is bonded on the front surface electrode 194 of the ZD chip 186 or on the back surface electrode 188 of the ZD chip 186.
Then, as shown in FIG. 130, a tray 210 of an arranging machine is prepared. The recess 201 with which the LED chip 184 engages is made in the upper surface of the tray 210. Then, the multiple LED chips 186 are fed onto the tray 210; and the tray 210 is caused to vibrate. Thereby, as shown in FIG. 131, the LED chips 184 are arranged by engaging with the recesses 201 of the tray 210.
Then, as shown in FIG. 132, a transfer tray 211 is caused to oppose the tray 210 and is brought into contact with the tray 210. A recess 212 is made in the transfer tray 211 at a position opposing the recess 201 of the tray 210. The recess 212 has a configuration with which the portion of the LED chip 184 protruding from the recess 201 engages.
Then, as shown in FIG. 133, the coupled body of the tray 210 and the transfer tray 211 is vertically inverted. Thereby, the LED chip 184 moves from the recess 201 side toward the recess 212 side inside the space where the recess 201 and the recess 212 communicate.
Then, as shown in FIG. 134, the tray 210 is removed from the transfer tray 211 ; and instead of the tray 210, a final tray 215 is brought into contact with the transfer tray 211. A recess 216, a recess 217, and a recess 218 (referring to FIG. 140A) are made in the final tray 215. The recess 216 is made in a position opposing the recess 212 of the transfer tray 211 and has a configuration with which the portion of the LED chip 184 protruding from the recess 212 engages. The recess 217 has a configuration with which the ZD chip 186, to which the bump 205 is bonded, engages with the bump 205 on the lower side. The recess 218 has a configuration with which the conduction dummy chip 196 engages.
Then, as shown in FIG. 135, the coupled body of the transfer tray 211 and the final tray 215 is vertically inverted. Thereby, the LED chip 184 moves from the recess 212 side toward the recess 216 side inside the space where the recess 212 and the recess 216 communicate. Then, the transfer tray 211 is removed from the final tray 215.
On the other hand, a ZD tray 220 is prepared as shown in FIG. 136. A recess 221 is made in the ZD tray 220. The size of the recess 221 is such that the portion of the ZD chip 186, to which the bump 205 is bonded, that engages the recess 221 is the side where the bump 205 is not bonded. Then, multiple ZD chips 186 are fed onto the ZD tray 220; and the ZD tray 220 is caused to vibrate.
Thereby, as shown in FIG. 137, the ZD chips 186 are arranged by engaging with the recesses 221 of the ZD tray 220. At this time, the bump 205 is disposed at the top of the ZD chip 186.
Then, as shown in FIG. 138, a ZD guide jig 223 is caused to cover the final tray 215. At this time, the LED chip 184 engages with the recess 216 of the final tray 215. The ZD guide jig 223 at the position opposing the recess 216 of the final tray 215 is used as a lid 224 covering the LED chip 184; and a through-portion 225 through which the ZD chip 186 can pass is made in the ZD guide jig 223 at the position opposing the recess 217. Then, the coupled body of the final tray 215 and the ZD guide jig 223 is vertically inverted and brought into contact with the ZD tray 220 so that the through-portion 225 opposes the recess 221. At this time, the LED chip 184 inside the recess 216 is held by the lid 224 of the ZD guide jig 223.
Then, as shown in FIG. 139, the coupled body in which the ZD tray 220, the ZD guide jig 223, and the final tray 215 are stacked is vertically inverted. Thereby, the ZD chip 186 that was engaged with the recess 221 of the ZD tray 220 moves from the recess 221 to the recess 217 of the final tray 215 through the through-portion 225 of the ZD guide jig 223 and engages with the recess 217. Thereby, in the final tray 215, the LED chip 184 is fixed inside the recess 216; and the ZD chip 186 is fixed inside the recess 217. Subsequently, the ZD tray 220 and the ZD guide jig 223 are removed from the final tray 215.
Then, as shown in FIGS. 140A and 140B, the conduction dummy chip 196 is caused to engage with the recess 218 of the final tray 215 by a method similar to the method for transferring the ZD chip 186 described above. Thereby, in the final tray 215, the LED chip 184 is fixed inside the recess 216; the ZD chip 186 is fixed inside the recess 217; and the conduction dummy chip 196 is fixed inside the recess 218. The subsequent processes are similar to the processes shown in FIG. 103 to FIGS. 124A to 124C of the seventh embodiment described above.
According to the modification, there is little trouble such as chips snagging in recesses, etc., because the chips are fed onto the tray one type at a time. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the modification are similar to those of the seventh embodiment described above.
(Eighth embodiment)
An eighth embodiment will now be described.
The embodiment differs from the seventh embodiment described above in that the connection in the thickness direction is made using a laser via instead of the dummy chip.
First, a method for manufacturing the semiconductor device according to the embodiment will be described.
FIG. 141A to FIG. 173C are drawings showing the method for manufacturing the semiconductor device according to the embodiment.
First, as shown in FIGS. 141A and 141B, the LED layer 11 is formed by epitaxially growing the n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer l ib in this order on the crystal growth substrate 10 by, for example, O-CVD.
Then, as shown in FIGS. 142A and 142B, high-mesa patterning of the LED layer 11 is performed. Thereby, the LED layer 11 is subdivided into multiple portions. When viewed from above, the configuration of each of the portions of the LED layer 11 is a rectangle; and the multiple portions are arranged in a matrix configuration.
Then, as shown in FIGS. 143A and 143B, p-mesa patterning of the LED layer 11 is performed. Thereby, the p-type GaN layer l ib, the active layer, and the upper layer portion of the n-type GaN layer 11a are removed at the peripheral portion of the LED layer 11. As a result, a stepped portion is formed in the region of the side surface of the LED layer 11 where the n-type GaN layer 11a is exposed; and the active layer is positioned higher than the stepped portion. The p-mesa patterning may be omitted.
Then, the passivation film 13 is formed on the entire surface as shown in FIGS. 144A and 144B. An insulating material such as, for example, silicon oxide, silicon nitride, etc., is deposited by PVD or CVD. Then, the passivation film 13 is patterned by, for example, lithography and RIE to make openings in the regions directly above the central portions of the p-type GaN layers l ib. At this time, by the p-mesa patterning being performed in the process shown in FIGS. 143A and 143B, the side surfaces of the active layers are reliably covered with the passivation film 13; and the reliability increases.
Then, as shown in FIGS. 145A and 145B, the p-electrodes 12b are formed inside the openings of the passivation film 13. Specifically, a metal film is formed by depositing a metal having a high optical reflectance, e.g., silver (Ag), by PVD; a resist mask is formed by lithography; and the metal film is patterned by performing RIE or wet etching. The p-electrodes 12b are connected to the p-type GaN layers lib. A barrier metal layer (not shown) may be formed on the p-electrodes 12b.
Then, as shown in FIGS. 146A and 146B, the structural bodies in which the LED layers 11, etc., are formed on the substrate 10 are adhered to the dicing tape 37. At this time, the upper surfaces of the structural bodies, i.e., the p-electrodes 12b, are bonded to the dicing tape 37. Then, the dicing tape 37 and the structural bodies are inverted; and the trench 14b is made in a lattice configuration in the lower surface of the substrate 10 by, for example, a diamond blade (not shown).
Then, as shown in FIGS. 147A and 147B, the modified portion 162 is formed by irradiating laser light so that the focal point of the laser light is positioned the interior of the substrate 10. Then, the antistatic film 163 is formed on the entire surface. The order of the laser modification and the formation of the antistatic film 163 may be reversed.
Then, as shown in FIGS. 148A and 148B, the dicing tape 37 is caused to expand (expand). Thereby, the relatively brittle modified portion 162 fractures; and the substrate 10 is singulated every LED layer 11. As a result, the intermediate structural body that includes the LED layer 11 (hereinbeiow, called the "LED chip 230") is made.
As shown in FIGS. 149A to 149C, the LED layer 11 is provided on the substrate 10 in the LED chip 230. The n-type GaN layer 11a, the active layer 11c, and the p-type GaN layer lib are stacked in this order in the LED layer 11. The configuration of the LED layer 11 is a rectangle as viewed from above; and the p-type GaN layer l ib, the active layer 11c, and the upper layer portion of the n-type GaN layer 11a are removed at the peripheral region. The p-type GaN layer l ib is exposed at the upper surface in the region of the LED layer 11 other than the peripheral portion. The p-electrode 12b is provided on the upper surface of the portion of the p-type GaN layer l ib other than the peripheral portion. The passivation film 13 is provided on the regions of the side surface of the LED layer 11 and the upper surface of the LED layer 11 not contacting the p-electrode 12b.
A rectangular parallelepiped protrusion is formed in the lower surface of the substrate 10. Also, the antistatic film 163 is provided on the lower surface of the substrate 10. Hereinbeiow, the protrusion of the substrate 10 and the antistatic film 163 provided on the lower surface of the protrusion and on the side surface of the protrusion are called a lower portion 230a of the LED chip 230; and the other portions are called an upper portion 230b. The lower portion 230a is finer than the upper portion 230b.
On the other hand, other than the LED chip 230, the ZD chip 186 shown in FIGS. 100D to 100F also is prepared. The embodiment differs from the seventh embodiment described above in that the conduction dummy chip 196 (referring to FIGS. 100G and H) is not used.
Then, as shown in FIG. 150, a tray 232 of the arranging machine 100 (referring to FIG. 7) is prepared. A recess 233 with which the LED chip 230 engages and the recess 202 with which the ZD chip 186 engages are made in the upper surface of the tray 232. The recess 233 is arranged in a matrix configuration as viewed from above. Also, the recess 202 is disposed on one longitudinal-direction side of the recess 233 as viewed from the recess 233. One unit includes one recess 233 and one recess 202.
The recess 233 has a two-step configuration; and a lower portion 233b is formed in the lower surface central portion of an upper portion 233a. The configurations of the upper portion 233a and the lower portion 233b are rectangular parallelepipeds. The lower portion 233b of the recess 233 has a configuration with which the lower portion 230a of the LED chip 230 engages but the upper portion 230b of the LED chip 230 does not engage; and the upper portion 233a of the recess 233 has a configuration with which the upper portion 230b of the LED chip 230 engages. Also, the depths of the recess 233 and the recess 202 are set so that the upper surface of the LED chip 230 engaging with the recess 233 and the upper surface of the ZD chip 186 engaging with the recess 202 are at the same height.
Then, as shown in FIGS. 151A and 151B, the LED chip
230 and the ZD chip 186 are fed simultaneously onto the tray 232; and the tray 232 is caused to vibrate. Thereby, the LED chip 230 is fixed in the vertical direction and contained inside the recess 233 by the lower portion 230a of the LED chip 230 engaging with the lower portion 233b of the recess 233 and the upper portion 230b of the LED chip 230 engaging with the upper portion 233a of the recess 233. On the other hand, the ZD chip 186 engages with the recess 202. At this time, the orientation of the vertical direction of the ZD chip 186 is not restricted and may have the two orientations of the orientation in which the front surface electrode 194 is positioned on the upper side and the orientation in which the back surface electrode 188 is positioned on the upper side. However, problems do not occur because the functions of the ZD chip 186 are vertically symmetric.
Then, as shown in FIG. 152, the upper surfaces of the
LED chip 230 and the ZD chip 186 (hereinbelow, also generally called the "chips") are bonded to the heat-resistant tape 169; and the chips are removed from the tray 232. Instead of the heat-resistant tape 169, a wafer support system in which an adhesive layer is formed on a support substrate may be used.
Then, as shown in FIG. 153, up and down are inverted; and the chips are disposed on the heat-resistant tape 169. At this time, the upper surface of the ZD chip 186 is positioned lower than the stepped surface of the boundary between the lower portion 230a and the upper portion 230b of the LED chip 230. Then, the gold stud bump 205 is adhered to the electrode on the upper surface side of the ZD chip 186, i.e., the back surface electrode 188 or the front surface electrode 194. At this time, the upper end of the bump 205 is positioned higher than the interface between the substrate 10 and the LED layer 11 of the LED chip 230.
Then, as shown in FIGS. 154A and 154B, the reinforcing insulating resin film 170 is formed to bury on the heat-resistant tape 169 and the chips by, for example, coating or molding. Subsequently, the heat-resistant tape 169 is peeled from the reinforcing insulating resin film 170.
Then, as shown in FIG. 155, up and down of the reinforcing insulating resin film 170 are inverted. Thereby, the p-electrode 12b of the LED chip 230 and the surface of the ZD chip 186 on the side where the bump 205 is not bonded are exposed at the upper surface of the reinforcing insulating resin film 170.
Then, as shown in FIGS. 156A and 156B, the insulating film 171 is formed on the entire surface of the reinforcing insulating resin film 170; and openings are made to expose portions of the electrodes of each of the chips. Specifically, the p-side via 171a and the ZD via 171b are made in the insulating film 171; the central portion of the p-electrode 12b of the LED chip 230 is exposed at the p-side via 171a; and the central portion of the back surface electrode 188 or front surface electrode 194 of the ZD chip 186 is exposed at the ZD via 171b.
Then, as shown in FIGS. 157A and 157B, the seed layer 172 is formed on the entire surface by, for example, PVD. Then, the thick film resist 173 is formed and patterned. At this time, the thick film resist 173 is patterned into a lattice configuration so that one block is set to include both the LED chip 230 and the ZD chip 186 and one block is set to include neither the LED chip 230 nor the ZD chip 186.
Then, as shown in FIGS. 158A to 158C, copper (Cu) is formed on the entire surface by electroplating, etc. Thereby, the copper interconnect layer 174 is formed in the regions where the thick film resist 173 is not formed. At this time, the upper portion of the thick film resist 173 protrudes from the upper surface of the copper interconnect layer 174. Also, the copper interconnect layer 174 is connected to the p-electrode 12b of the LED chip 230 and the back surface electrode 188 or front surface electrode 194 of the ZD chip 186 via the seed layer 172.
Then, as shown in FIGS. 159A to 159C, the thick film resist 175 is formed on the copper interconnect layer 174 to cover the thick film resist 173; and the thick film resist 175 is patterned. At this time, the thick film resist 175 is formed in a lattice configuration. Specifically, the thick film resist 175 is formed to cover the region where dicing is to be performed in a subsequent process, cover the region having the band configuration extending in the arrangement direction of the LED chip 230 and the ZD chip 186 in which both the LED chip 230 and the ZD chip 186 are disposed, and leave the rectangular regions on two lateral-direction sides of the LED chip 230 as viewed from the region having the band configuration exposed. Then, the copper pillars 176 are formed in the regions where the thick film resist 175 is not formed by forming copper (Cu) on the entire surface by electroplating. The copper pillars 176 are connected to the copper interconnect layer 174.
Then, the thick film resist 175 and the thick film resist 173 are removed as shown in FIGS. 160A to 160C. Then, the portion of the seed layer 172 not covered with the copper interconnect layer 174 is removed by etching using the copper pillars 176 and the copper interconnect layer 174 as a mask. Thereby, two sets of the set made of the copper interconnect layer 174 and the copper pillar 176 are partitioned every unit made of one LED chip 230 and one ZD chip 186; one set is connected to both the ZD chip 186 and the p-electrode 12b of the LED chip 230; and the other set is connected to neither the LED chip 230 nor the ZD chip 186.
Then, the reinforcing insulating resin film 178 is formed on the entire surface as shown in FIGS. 161A to 161C.
Then, as shown in FIGS. 162A to 162C, the reinforcing insulating resin film 170 is thinned by polishing from the lower surface side by, for example, a back side grinder. Thereby, the lower portions 230a of the LED chips 230 are removed to expose the substrates 10. Also, the bumps 205 that are bonded to the ZD chips 186 are exposed.
Then, up and down are inverted as shown in FIGS. 163A to 163C.
Then, as shown in FIGS. 164A to 164C, the crystal growth substrates 10 of the LED chips 230 are removed by etching. Thereby, the LED layers 11 are exposed.
Then, as shown in FIGS. 165A to 165C, via holes 235 are made by selectively removing the reinforcing insulating resin film 170 and the insulating film 171 by, for example, laser patterning. The via holes 235 are made in regions directly above the copper interconnect layers 174 and are connected to neither the LED chip 230 nor the ZD chip 186. Thereby, the copper interconnect layers 174 are exposed at the bottom surfaces of the via holes 235. In the case where a filler is not included in the reinforcing insulating resin film 170, patterning by RIE is possible as well. Also, a dummy silicon chip may be buried in the process of forming the reinforcing insulating resin film 170 shown in FIG. 154; and the silicon chip also may be removed by etching when etching the substrate 10 in the process shown in FIGS. 164A to 164C.
Then, as shown in FIGS. 166A to 166C, the n-side interconnect film 207 is formed by depositing a conductive material having a low resistivity on the entire surface. It is favorable for the upper surface of the n-side interconnect film 207 to be formed of a material having a high optical reflectance, e.g., silver (Ag), aluminum (Al), etc. The n-side interconnect film 207 is connected to the n-type GaN layers 11a of the LED chips 230 and the bumps 205 bonded to the ZD chips 186 and is connected to the copper interconnect layers 174 in the interior of the via holes 235 by being formed on the inner surfaces of the via holes 235 as well.
Then, the hard mask film 208 is formed on the entire surface as shown in FIGS. 167A to 167C. It is favorable for the hard mask film 208 to be an inorganic film that covers and protects the n-side interconnect film 207 and has high light-shielding properties, e.g., to be formed by depositing silicon oxide (Si02) by CVD. Then, the hard mask film 208 is patterned to make openings in the region where dicing is to be performed in a subsequent process, at the entire central portions of the LED layers 11, and at portions of the peripheral portions of the LED layers 11.
Then, as shown in FIGS. 168A to 168C, the n-side interconnect film 207 is patterned by etching the n-side interconnect film 207 using the hard mask film 208 as a mask. Thereby, the n-side interconnect film 207 is partitioned every portion connected to one LED chip 230 and one ZD chip 186. Also, the n-side interconnect film 207 that is on the LED layers 11 is selectively removed.
Then, as shown in FIGS. 169A to 169C, the passivation film 209 is formed on the entire surface. It is favorable for the passivation film 209 to be an inorganic film having high light-shielding properties, e.g., it is favorable to be a silicon oxide film formed by CVD. Then, the passivation film 209 is patterned to cover the n-side interconnect film 207 and leave the LED layers 11 exposed.
Then, as shown in FIGS. 170A to 170C, surface roughening of the LED layers 11 is performed.
Then, the fluorescer film 179 is formed on the reinforcing insulating resin film 170 as shown in FIGS. 171A to 171C.
Then, as shown in FIGS. 172A to 172C, the copper pillars 176 are exposed by polishing the reinforcing insulating resin film 178 from the lower surface side by, for example, a back side grinder.
Then, as shown in FIGS. 173A to 173C, singulation is performed every LED layer 11 by cutting the reinforcing insulating resin film 178, the insulating film 171, the reinforcing insulating resin film 170, and the fluorescer film 179 by, for example, a method such as blade dicing, laser dicing, etc. Thus, the semiconductor device 8 according to the embodiment is manufactured.
The configuration and the operations of the semiconductor device according to the embodiment will now be described.
FIG. 174 is a circuit diagram showing the semiconductor device according to the embodiment.
As shown in FIGS. 173A to 173C, the reinforcing insulating resin film 178, the reinforcing insulating resin film 170, and the fluorescer film 179 are stacked in this order in the semiconductor device 8. Two sets of the external electrodes made of the copper interconnect layer 174 and the copper pillar 176 are provided inside the reinforcing insulating resin film 178. One LED chip 230 and one ZD chip 186 are provided inside the reinforcing insulating resin film 170. Also, the via hole 235 is made in the reinforcing insulating resin film 170 to pierce the reinforcing insulating resin film 170 in the thickness direction. The n-side interconnect film 207 is selectively provided between the reinforcing insulating resin film 170 and the fluorescer film 179. The n-side interconnect film 207 is provided also on the inner surface of the via hole 235.
Also, the copper interconnect layer 174 on the cathode side is connected to the n-side interconnect film 207 through the via hole 235. The n-side interconnect film 207 is connected to the n-type GaN layer 11a of the LED chip 230 and one selected from the back surface electrode 188 and the front surface electrode 194 of the ZD chip 186. On the other hand, the copper interconnect layer 174 on the anode side is connected to the p-electrode 12b of the LED chip 230 and the other selected from the back surface electrode 188 and the front surface electrode 194 of the ZD chip 186.
Thereby, as shown in FIG. 174, the LED chip 230 and the ZD chip 186 are connected in parallel between the copper pillar 176 on the anode side and the copper pillar 176 on the cathode side. As a result, normally, the current flows in the path of (the copper pillar 176 on the anode side - the copper interconnect layer 174 on the anode side - the p-electrode 12b of the LED chip 230 - the p-type GaN layer l ib of the LED layer 11 - the active layer - the n-type GaN layer 11a - the n-side interconnect film 207 (including the portion formed on the inner surface of the via hole 235) - the copper interconnect layer 174 on the cathode side - the copper pillar 176 on the cathode side); and the LED layer 11 emits light. Also, the LED chip 230 is protected by the ZD chip 186 allowing a current to flow when an excessive voltage is applied between the copper pillar 176 on the anode side and the copper pillar 176 on the cathode side. At this time, the n-side interconnect film 207 that is formed on the inner surface of the via hole 235 is used as the interconnect member piercing the reinforcing insulating resin film 170 in the thickness direction.
According to the embodiment, a semiconductor device that is similar to the seventh embodiment described above can be realized by making the via hole 235 instead of providing the conduction dummy chip 196.
Otherwise, the configuration, the manufacturing method, and the effects of the embodiment are similar to those of the seventh embodiment described above.
According to the embodiments described above, a semiconductor device and a method for manufacturing the semiconductor device having high heat dissipation and a low manufacturing cost can be realized.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention. Additionally, the embodiments described above can be combined mutually.

Claims

[CLAIMS]
[Claim 1]
A method for manufacturing a semiconductor device, comprising:
forming a plurality of LED layers arranged in a matrix configuration on a substrate, the configuration of each of the plurality of LED layers being a square as viewed from above; forming a first electrode at four corners of an upper surface of each of the LED layers and forming a second electrode in a region of the upper surface other than the four corners;
cutting the substrate into a plurality of intermediate structural bodies every each of the LED layers by making a first trench in an upper portion of the substrate to partition the plurality of LED layers from each other and making a second trench in a lower portion of the substrate to cause the first trench and the second trench to communicate with each other, the second trench being wider than the first trench;
arranging the plurality of intermediate structural bodies to be separated from each other by causing the lower portions of the intermediate structural bodies to engage with a recess multiply made in an upper surface of a tray by causing the plurality of intermediate structural bodies to tumble on the tray, the lower portion of the substrate cut by the second trench being configured to engage with the recess, the upper portion of the substrate being configured not to engage with the recess; and
forming a first external electrode and a second external electrode, the first external electrode being connected to the first electrode, a portion of the first external electrode extending outside the intermediate structural body as viewed from above, the second external electrode being connected to the second electrode, a portion of the second external electrode extending outside the intermediate structural body as viewed from above.
[Claim 2] A method for manufacturing a semiconductor device, comprising :
making a plurality of intermediate structural bodies, each of the plurality of intermediate structural bodies including an electrode and a semiconductor member, the electrode being formed on the semiconductor member, a configuration of an upper portion and a configuration of a lower portion being different from each other as viewed from above for each of the plurality of intermediate structural bodies;
arranging the plurality of intermediate structural bodies to be separated from each other by causing one portion selected from the upper portion and the lower portion for each of the intermediate structural bodies to engage with a recess multiply made in an upper surface of a tray by causing the plurality of intermediate structural bodies to tumble on the tray, the one portion being configured to engage with the recess, the other portion selected from the upper portion and the lower portion being configured not to engage with the recess; and
forming an external electrode connected to the electrode, a portion of the external electrode extending outside the intermediate structural body as viewed from above.
[Claim 3]
The method for manufacturing the semiconductor device according to claim 2, wherein
the making of the intermediate structural bodies includes:
forming the electrode on a substrate;
making a first trench in an upper portion of the substrate; and
making a second trench in a lower portion of the substrate,
a width of the first trench and a width of the second trench being different from each other,
the substrate being cut into the plurality of intermediate structural bodies by the first trench and the second trench communicating with each other; and the portion of the substrate cut by the wider trench selected from the first trench and the second trench being used as a portion of the one portion .
[Claim 4]
The method for manufacturing the semiconductor device according to claim 2, wherein
the making of the intermediate structural bodies includes forming a bump on the electrode, and
the one portion is the lower portion .
[Claim 5]
The method for manufacturing the semiconductor device according to claim 2, wherein
the making of the intermediate structural bodies includes forming a bump on the electrode, and
the one portion is the upper portion including the bump.
[Claim 6]
The method for manufacturing the semiconductor device according to claim 2, wherein
the configuration of the intermediate structural body has n-fold rotational symmetry (n being an integer not less than 2), and
the electrode is disposed with /7-fold rotational symmetry in the intermediate structural body.
[Claim 7]
The method for manufacturing the semiconductor device according to claim 2, wherein
the configuration of the intermediate structural body is rotationally asymmetric; and
the plurality of intermediate structural bodies are arranged to have a predetermined orientation in the arranging .
[Claim 8]
A method for manufacturing a semiconductor device, comprising :
making a plurality of intermediate structural bodies, each of the plurality of intermediate structural bodies including an electrode and a semiconductor member, the electrode being formed on the semiconductor member, the configuration of each of the plurality of intermediate structural bodies having /7-fold rotational symmetry (n being an integer not less than 2), the electrode being disposed with n-fold rotational symmetry;
arranging the plurality of intermediate structural bodies to be separated from each other by causing the intermediate structural bodies to engage with a recess multiply made in an upper surface of a tray by causing the plurality of intermediate structural bodies to tumble on the tray, the recesses being configured to engage with the intermediate structural bodies; and
forming an external electrode connected to the electrode, a portion of the external electrode extending outside the intermediate structural body as viewed from above.
[Claim 9]
A method for manufacturing a semiconductor device, comprising :
making a plurality of intermediate structural bodies, each of the plurality of intermediate structural bodies including an electrode and a semiconductor member, the electrode being formed on the semiconductor member, the configuration of each of the plurality of intermediate structural bodies being rotationally asymmetric, the electrode being disposed rotationally asymmetrically;
arranging the plurality of intermediate structural bodies to have the same orientation and to be separated from each other by causing the intermediate structural bodies to engage with a recess multiply made in an upper surface of a tray by causing the plurality of intermediate structural bodies to tumble on the tray, the recesses being configured to engage with the intermediate structural bodies; and
forming an external electrode connected to the electrode, a portion of the external electrode extending outside the intermediate structural body as viewed from above.
[Claim 10]
A method for manufacturing a semiconductor device, comprising :
making a plurality of intermediate structural bodies, each of the plurality of intermediate structural bodies including an electrode and a semiconductor member, the electrode being formed on the semiconductor member, the configuration of each of the plurality of intermediate structural bodies being rotationally asymmetric and mirror-image asymmetric;
arranging the plurality of intermediate structural bodies to have a predetermined orientation and to be separated from each other by causing the intermediate structural bodies to engage with a recess multiply made in an upper surface of a tray by causing the plurality of intermediate structural bodies to tumble on the tray, the recesses being configured to engage with the intermediate structural bodies; and
forming an external electrode connected to the electrode, a portion of the external electrode extending outside the intermediate structural body as viewed from above.
[Claim 11]
The method for manufacturing the semiconductor device according to claim 2, further comprising making a plurality of one other intermediate structural bodies,
the arranging also including causing the plurality of one other intermediate structural bodies to tumble on the tray,
one other recess also being multiply made in the tray, the one other recesses being configured to engage with the one other intermediate structural bodies,
the intermediate structural bodies being configured not to engage with the one other recesses, the one other intermediate structural bodies being configured not to engage with the recesses.
[Claim 12]
The method for manufacturing the semiconductor device according to claim 11, wherein
configurations of the intermediate structural bodies and the one other intermediate structural bodies are rectangles as viewed from above, a short side of the intermediate structural body is longer than a short side of the one other intermediate structural body, and
a long side of the one other intermediate structural body is longer than a long side of the intermediate structural body.
[Claim 13]
The method for manufacturing the semiconductor device according to claim 2, wherein
three or more types of the intermediate structural body are made,
the recess has three or more types,
the intermediate structural body of one type is configured to engage with only the recess of one type, and
the recess of the one type is configured to engage with only the intermediate structural body of the one type.
[Claim 14]
The method for manufacturing the semiconductor device according to claim 2, wherein
the semiconductor member is a light emitting diode, and the making of the intermediate structural bodies includes forming a reflective layer on an upper surface of the semiconductor member and on a side surface of the semiconductor member.
[Claim 15]
The method for manufacturing the semiconductor device according to claim 2, wherein
the semiconductor member is a light emitting diode, the making of the intermediate structural bodies includes:
forming the electrode connected to a first-conductivity-type layer of the light emitting diode;
forming an insulating film on the electrode; and forming one other electrode on the insulating film, the one other electrode being connected to a second-conductivity-type layer of the light emitting diode, and an end portion of the one other electrode overlapping an end portion of the electrode as viewed from above.
[Claim 16]
The method for manufacturing the semiconductor device according to claim 2, further comprising :
forming a reinforcing insulating film to bury the intermediate structural bodies;
forming a transparent member on a region of a surface of the reinforcing insulating film where the semiconductor member is exposed, the transparent member having a dome configuration; and
forming a fluorescer film on the surface of the reinforcing insulating film to cover the transparent member,
the semiconductor member being a light emitting diode.
[Claim 17]
A method for manufacturing a semiconductor device, comprising :
causing a light emitting diode chip to engage with a first recess made in an upper surface of a tray, causing a Zener diode chip to engage with a second recess made in the upper surface of the tray, and causing a conduction dummy chip to engage with a third recess made in the upper surface of the tray;
forming a reinforcing insulating film to bury the light emitting diode chip, the Zener diode chip, and the conduction dummy chip;
forming, on a lower surface of the reinforcing insulating film, a first external electrode connected to a lower surface electrode of the light emitting diode chip and a lower surface electrode of the Zener diode chip and forming, on the lower surface of the reinforcing insulating film, a second external electrode connected to a lower surface of the conduction dummy chip; and
forming an interconnect film on an upper surface of the reinforcing insulating film, the interconnect film being connected to an upper surface electrode of the light emitting diode chip, an upper surface electrode of the Zener diode chip, and an upper surface of the conduction dummy chip.
[Claim 18]
A method for manufacturing a semiconductor device, comprising :
causing a light emitting diode chip to engage with a first recess made in an upper surface of a tray and causing a Zener diode chip to engage with a second recess made in the upper surface of the tray;
forming a reinforcing insulating film to bury the light emitting diode chip and the Zener diode chip;
forming a first external electrode on a lower surface of the reinforcing insulating film and forming a second external electrode on the lower surface of the reinforcing insulating film, the first external electrode being connected to a lower surface electrode of the light emitting diode chip and a lower surface electrode of the Zener diode chip, the second external electrode being separated from the first external electrode;
making a through-hole in the reinforcing insulating film in a region directly above the second external electrode; and forming an interconnect film on an upper surface of the reinforcing insulating film, the interconnect film being connected to the second external electrode via the through-hole and connected to an upper surface electrode of the light emitting diode chip and an upper surface electrode of the Zener diode chip.
[Claim 19]
A semiconductor device, comprising :
a semiconductor member, a configuration of the semiconductor member having /7-fold rotational symmetry (n being an integer not less than 2) ;
an electrode provided on the semiconductor member and disposed with n-fold rotational symmetry; and
an external electrode connected to the electrode, a portion of the external electrode extending outside the semiconductor member as viewed from above.
[Claim 20] A semiconductor device, comprising :
a semiconductor member;
an electrode provided on the semiconductor member; a bump provided on at least a portion of the electrode and disposed at a position distal to a central axis of the semiconductor member; and
an external electrode connected to the electrode, a portion of the external electrode extending outside the semiconductor member as viewed from above.
[Claim 21]
A semiconductor device, comprising :
a semiconductor member, a configuration of the semiconductor member being rotationally asymmetric and mirror-image asymmetric;
an electrode provided on the semiconductor member; and
an external electrode connected to the electrode, a portion of the external electrode extending outside the semiconductor member as viewed from above.
[Claim 22]
The semiconductor device according to claim 19, further comprising a reflective layer provided on an upper surface of the semiconductor member and on a side surface of the semiconductor member,
the semiconductor member being a light emitting diode.
[Claim 23]
The semiconductor device according to claim 19, further comprising :
an insulating film is provided on the electrode; and one other electrode provided on the insulating film and connected to a first-conductivity-type layer of the semiconductor member,
the electrode being connected to a second-conductivity-type layer of the semiconductor member, the semiconductor member being a light emitting diode, an end portion of the electrode overlapping an end portion of the one other electrode as viewed from above.
[Claim 24]
The semiconductor device according to claim 19, further comprising :
a transparent member provided on a lower surface of the semiconductor member, the transparent member having a dome configuration; and
a fluorescer film covering the transparent member, the semiconductor member being a light emitting diode.
[Claim 25]
A semiconductor device, comprising :
a first semiconductor member;
a first external electrode connected to the first semiconductor member, a portion of the first external electrode extending outside the first semiconductor member as viewed from above;
a second semiconductor member separated from the first semiconductor member; and
a second external electrode connected to the second semiconductor member, a portion of the second external electrode extending outside the second semiconductor member as viewed from above,
an outer edge of the first semiconductor member as viewed from above and an outer edge of the second semiconductor member as viewed from above intersect each other when the outer edge of the first semiconductor member and the outer edge of the second semiconductor member are overlaid.
[Claim 26]
The semiconductor device according to claim 25, wherein a configuration of the first semiconductor member and a configuration of the second semiconductor member are rectangles as viewed from above, and
a short side of one selected from the first semiconductor member and the second semiconductor member is longer than a short side of the other selected from the first semiconductor member and the second semiconductor member, and a long side of the other selected from the first semiconductor member and the second semiconductor member is longer than a long side of the one selected from the first semiconductor member and the second semiconductor member.
[Claim 27]
The semiconductor device according to claim 25, wherein the first semiconductor member is a light emitting diode; and
the second semiconductor member is a Zener diode.
[Claim 28]
The semiconductor device according to claim 25, wherein a first semiconductor member is an integrated circuit; and
a second semiconductor member is a passive component.
[Claim 29]
A semiconductor device, comprising :
a light emitting diode chip;
a Zener diode chip;
a conduction dummy chip made of a conductor material; a reinforcing insulating film burying the light emitting diode chip, the Zener diode chip, and the conduction dummy chip;
a first external electrode provided on a lower surface of the reinforcing insulating film and connected to a lower surface electrode of the light emitting diode chip and a lower surface electrode of the Zener diode chip;
a second external electrode provided on the lower surface of the reinforcing insulating film and connected to a lower surface of the conduction dummy chip; and
an interconnect film provided on an upper surface of the reinforcing insulating film and connected to an upper surface electrode of the light emitting diode chip, an upper surface electrode of the Zener diode chip, and an upper surface of the conduction dummy chip.
[Claim 30] A semiconductor device, comprising :
a light emitting diode chip;
a Zener diode chip;
a reinforcing insulating film burying the light emitting diode chip and the Zener diode chip, a through-hole being made in the reinforcing insulating film;
a first external electrode provided on a lower surface of the reinforcing insulating film and connected to a lower surface electrode of the light emitting diode chip and a lower surface electrode of the Zener diode chip;
a second external electrode provided on the lower surface of the reinforcing insulating film and provided in a region directly under the through-hole; and
an interconnect film provided on an upper surface of the reinforcing insulating film, connected to the second external electrode via the through-hole, and connected to an upper surface electrode of the light emitting diode chip and an upper surface electrode of the Zener diode chip.
[Claim 31]
A method for manufacturing a semiconductor device, comprising :
making a plurality of intermediate structural bodies on a semiconductor member, each of the plurality of intermediate structural bodies including an electrode and having a prescribed configuration fitting in a configuration of a recess multiply made in a tray;
arranging the plurality of intermediate structural bodies to be separated from each other by causing the intermediate structural bodies to engage with the recesses by causing the plurality of intermediate structural bodies to tumble on the tray; and
forming an external electrode connected to the electrode, a portion of the external electrode extending outside the intermediate structural body as viewed from above.
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