WO2015023144A1

WO2015023144A1 - Method and device for monitoring data integrity in shared memory environment

Info

Publication number: WO2015023144A1
Application number: PCT/KR2014/007574
Authority: WO
Inventors: 조한수; 강병훈; 백윤흥; 이승욱; 신준범
Original assignee: 삼성전자 주식회사; 서울대학교산학협력단
Priority date: 2013-08-16
Filing date: 2014-08-14
Publication date: 2015-02-19
Also published as: US20160196083A1; EP3035227A4; US10168934B2; EP3035227B1; KR102167393B1; EP3035227A1; KR20150019845A

Abstract

A method for accessing memory in a memory control unit of an integrity monitoring system which shares memory with a host system, according to an embodiment of the present specification, comprises the steps of: receiving a memory access command from a local processor of an integrity monitoring system; accessing a system memory of a host system on the basis of the memory access command; receiving data, which corresponds to the access command, from the host system; and transmitting the received data to the local processor, wherein the system memory comprises a security area, which is accessible if a memory control unit has received the memory access command from the local processor. Embodiments of the present specification provide a method and a device for monitoring, in an SoC environment, the integrity of data which is processed in a host system.

Description

Data integrity monitoring device and method in memory sharing environment

Embodiments of the present disclosure relate to a snooper based kernel integrity monitoring apparatus and a control method thereof. More specifically, the present invention relates to an integrity monitoring apparatus and memory control method for sharing a memory with a main system in a system on chip environment.

As more devices use System on Chip (SoC), the need for a way to monitor malicious software attacks in data processing in the environment is increasing. In particular, the need for more efficient monitoring of the OS (Operating System) Kernel in the SoC environment increases, so that data processed in the SoC environment can be monitored to check integrity and effectively block attacks such as malicious software. A need arose. However, when a separate monitoring device is used, the addition of the processing processor and memory of the additional device entails an increase in the area of the SoC, thereby increasing the manufacturing cost and increasing the power consumption during system processing.

The embodiment of the present specification is proposed to solve the above-mentioned problem, and includes a monitoring device in an SoC environment, through which a data integrity is broken due to an attack of a malicious program and the like, and a corresponding operation is performed. An object of the present invention is to provide an apparatus and a control method which can be used.

In addition, another embodiment of the present disclosure is to provide a monitoring device and a control method that can reduce the system area and power consumption by sharing the memory with the host system for data integrity monitoring in SoC environment.

In order to achieve the above object, a memory access method in a memory control unit of an integrity monitor system sharing a memory with a host system according to an embodiment of the present disclosure comprises the steps of receiving a memory access command from a local processor of the integrity monitor system; Accessing system memory of the host system according to the memory access command; Receiving corresponding data from the host system based on the access command; And transferring the received data to the local processor, wherein the system memory comprises a secure area accessible by the memory controller when a memory access command is received from the local processor.

An integrity monitor system apparatus sharing a memory with a host system according to another exemplary embodiment of the present disclosure may include a local processor that controls an operation of the integrity monitor system; And receiving a memory access command from the local processor, accessing a system memory of the host system according to the memory access command, receiving corresponding data from the host system based on the access command, and receiving the received access command. And a memory controller for transmitting one data to the local processor, wherein the system memory includes a secure area accessible by the memory controller when a memory access command is received from the local processor.

According to one embodiment of the present specification, a method and apparatus for monitoring the integrity of data processed in a host system in an SoC environment are provided.

In addition, according to another embodiment of the present disclosure, as the apparatus for monitoring data integrity in the host system shares a memory with the host system, a method and apparatus for efficiently using the system area and reducing power consumption are provided.

According to another embodiment of the present disclosure, when the memory is shared with the host system, the reliability of the integrity monitoring apparatus may be improved by providing a control device for reading and writing a memory.

1 is a view showing the structure of a system according to an embodiment of the present disclosure.

2 is a diagram illustrating a structure of a system according to another exemplary embodiment of the present specification.

3A to 3C are diagrams illustrating a connection relationship between memory controllers according to various embodiments of the present disclosure.

4A to 4C are diagrams illustrating signal flows of respective configuration diagrams according to embodiments of the present specification.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In describing the embodiments, descriptions of technical contents which are well known in the technical field to which the present invention belongs and are not directly related to the present invention will be omitted. This is to more clearly communicate without obscure the subject matter of the present invention by omitting unnecessary description.

For the same reason, in the accompanying drawings, some components are exaggerated, omitted or schematically illustrated. In addition, the size of each component does not fully reflect the actual size. The same or corresponding components in each drawing are given the same reference numerals.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments of the present invention make the disclosure of the present invention complete and the general knowledge in the technical field to which the present invention belongs. It is provided to fully convey the scope of the invention to those skilled in the art, and the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings to describe an apparatus and method for monitoring data integrity in a memory sharing environment.

At this point, it will be understood that each block of the flowchart illustrations and combinations of flowchart illustrations may be performed by computer program instructions. Since these computer program instructions may be mounted on a processor of a general purpose computer, special purpose computer, or other programmable data processing equipment, those instructions executed through the processor of the computer or other programmable data processing equipment may be described in flow chart block (s). It creates a means to perform the functions. These computer program instructions may be stored in a computer usable or computer readable memory that can be directed to a computer or other programmable data processing equipment to implement functionality in a particular manner, and thus the computer usable or computer readable memory. It is also possible for the instructions stored in to produce an article of manufacture containing instruction means for performing the functions described in the flowchart block (s). Computer program instructions may also be mounted on a computer or other programmable data processing equipment, such that a series of operating steps may be performed on the computer or other programmable data processing equipment to create a computer-implemented process to create a computer or other programmable data. Instructions for performing the processing equipment may also provide steps for performing the functions described in the flowchart block (s).

In addition, each block may represent a portion of a module, segment, or code that includes one or more executable instructions for executing a specified logical function (s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of order. For example, the two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the corresponding function.

In this case, the term '~ part' used in the present embodiment refers to software or a hardware component such as an FPGA or an ASIC, and '~ part' performs certain roles. However, '~' is not meant to be limited to software or hardware. '~ Portion' may be configured to be in an addressable storage medium or may be configured to play one or more processors. Thus, as an example, '~' means components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, procedures, and the like. Subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functionality provided within the components and the 'parts' may be combined into a smaller number of components and the 'parts' or further separated into additional components and the 'parts'. In addition, the components and '~' may be implemented to play one or more CPUs in the device or secure multimedia card.

Referring to FIG. 1, a system of the present disclosure may include a host system 150 capable of performing computation and signal transmission and reception, and an integrity monitor system 100 for monitoring the integrity of signals transmitted and received by the host system 150. have.

In some embodiments, the integrity monitor system 100 may be implemented on the same chip as the host system 150 or may be connected to each other through a separate connection structure.

The integrity monitor system 100 of the embodiment may include one or more of a snooper 105, a verification unit 110, a local bus 115, a local memory 120, a local processor 125, and a local bridge 130. Can be.

The snooper 105 may be connected to the system bus 165 and may monitor data to and from the system bus 165 through a snooping technique.

The verification unit 110 may verify the traffic snooped by the snooper 105 to determine whether the integrity is maintained by an attack such as malicious software. The verification unit 110 may exchange data with other components of the integrity monitor system 100 through the local bus 115.

The local memory 120 may read and write one or more of data required by the integrity monitor system 100 during operation and data such as integrity verification result values. The local memory 120 may transmit / receive data with other components of the integrity monitor system 100 via the local bus 115.

The local processor 125 may serve as a controller that can control the overall operation of the integrity monitor system 100. The local processor 125 may exchange data with other components of the integrity monitor system 100 through the local bus 115.

The local bridge 130 may transmit / receive data with other components of the integrity monitor system 100 through the local bus 115, and may perform an operation of a connection interface that may transmit / receive signals with an external system. . In an embodiment, the local bridge 130 may be connected to the system bridge 170 of the host system 150 to perform signal transmission and reception.

The host system may include one or more of system memory 155, system processor 160, system bus 165, and system bridge 170.

The system memory 155 may store data necessary for the host system 150 to operate, and may read the stored data under the control of the system processor 160. The system memory 155 may exchange data with other components of the host system 150 through the system bus 165.

The system processor 160 may serve as a controller for controlling overall operations of the host system 150. The system processor 160 may exchange data with other components of the host system 150 through the system bus 165.

The system bridge 170 may transmit / receive data with other components of the host system 150 through the system bus 165 and perform an operation of a connection interface that may transmit / receive a signal with an external system. In an embodiment, the system bridge 170 may be connected to the local bridge 130 of the integrity monitor system 100 to perform signal transmission and reception.

In an embodiment, the integrity monitor system 100 may monitor traffic generated by the host system 150 to monitor the integrity of data included in the traffic. In more detail, the integrity monitor system 100 may monitor the traffic transmitted and received on the system bus 165 of the host system 150 through the snooper 105. Snooper 105 may monitor traffic to and from the system bus through a snooping method.

If the integrity monitor system 100 determines that there is broken data in the traffic, the integrity monitor system 100 may notify the host system 150 that the integrity of the data is broken. More specifically, the integrity monitor system 100 may inform the system processor 160 that the integrity of the corresponding data is broken through the local bridge 130 via the system bridge 170. The system processor 160 may perform an operation such as reprocessing data whose integrity is broken. As described above, the integrity monitor system 100 monitors the integrity of the traffic traveling on the system bus 165 to perform a more reliable operation.

In an embodiment, the local bridge 130 is an optional structure, and the system bridge 170 may be connected to the local bus 115 through a direct connection.

Referring to FIG. 2, the integrity monitor system 200 may be implemented on the same chip as the host system 250 or may be connected to each other through a separate connection structure. In addition, the embodiment disclosed in FIG. 2 shares the system memory 255 area of the host system 250 with the integrity monitor system 200, and may further include a memory controller 220 for such sharing.

Integrity monitoring system 200 of the embodiment may include one or more of the snoop 205, the verification unit 210, the local bus 215, the memory control unit 220 and the local processor 225.

In an embodiment, the host system 250 may include one or more of a system memory 255, a system processor 260, a system bus 265, and a system bridge 270.

The snoop 205 may be connected to the system bus 165 and may monitor data traveling on the system bus 265 through a snooping technique.

The verification unit 210 may verify the traffic snooped by the snoop 205 and determine whether integrity is maintained by an attack such as malicious software. The verification unit 210 may transmit / receive data with other components of the integrity monitor system 200 through the local bus 215.

The memory controller 220 is a module for sharing the system memory 255 of the host system 250 by the integrity monitor system 200 according to an exemplary embodiment. More specifically, the system memory 255 may be accessed according to control signals of the local processor 225 and the system processor 260 to perform a read or write operation. The memory controller 220 may be connected to one or more of the local bus 215, the local processor 225, the system memory 255, and the system bus 265. One or more of the above connections may be selectively performed, and the detailed description and the connection relationship of the memory controller will be described later.

The local processor 225 may serve as a controller for controlling the overall operation of the integrity monitor system 200. The local processor 225 may exchange data with other components of the integrity monitor system 200 through the local bus 215. In addition, the local processor 225 may control the memory controller 220 to read data stored in the system memory 255. More specifically, the memory controller 220 may read data stored in the system memory 255 and transfer the data stored in the system memory 255 to the local processor 225 through the system bus 265, the system bridge 270, and the local bus 215. However, in some embodiments, the system bridge 270 may also be an optional configuration. In another embodiment, a local bus may be additionally provided between the local bus 215 and the system bridge 270.

The host system may include one or more of system memory 255, system processor 260, system bus 265, and system bridge 270.

The system memory 255 may include a security area 257 and a system area 259, and each area may store one or more of a program and data.

In the case of the security area 257, one or more of programs and data related to the integrity monitor system 200 may be stored. The system memory 255 may be accessed through the memory control unit 220. The security area 257 may be accessed only when access is performed according to the operation of the integrity monitor system 200 through the operation of the memory control unit 220. In this case, kernel independence of the integrity monitor system 200 may be guaranteed even in an environment in which the system memory 255 is shared.

In the embodiment of the system area 259, the host system 250 is an area accessible by the memory controller 220. More specifically, one or more of programs and data related to the host system 250 may be stored. When the memory controller 220 accesses the system memory 255 according to the request of the host system 250, the memory controller 220 may not access the security area 257, thereby ensuring kernel independence.

In an embodiment, the security area 257 may be set and changed only by the local processor 255 through the memory controller 220, and the system processor 260 may not perform any operation and access to the security area 257. Can not.

In another embodiment, the snoop 205 may look at the information on the system bus 265. In addition, the verification unit 210 stores the address of the security zone 257, and requests an analysis from the local processor 225 when an attack on the security zone 257 is detected, and the local processor 225 results in the analysis. May be informed to the system processor 260.

In another embodiment, the security zone 257 may be allocated to the integrity monitor system 200 by the system processor 260, and the memory controller 220, the verification unit 210, and the local processor 225 according to the allocation information. May be determined.

The system processor 260 may serve as a controller for controlling the overall operation of the host system 250. The system processor 260 may exchange data with other components of the host system 250 through the system bus 265. In another embodiment, the system processor 260 may control the overall operation of the host system 250 except for the security area 257.

The system bridge 270 may transmit / receive data with other components of the host system 250 through the system bus 265, and may perform an operation of a connection interface that may transmit / receive a signal with an external system. In an embodiment, the system bridge 270 may be connected to the integrity monitor system 200 to perform signal transmission and reception.

In an embodiment, the integrity monitor system 200 may monitor traffic generated by the host system 250 to monitor the integrity of data included in the traffic. In more detail, the integrity monitor system 200 may monitor the traffic transmitted and received on the system bus 265 of the host system 250 through the snooper 205. Snooper 205 may monitor traffic to and from the system bus through a snooping method.

If the integrity monitor system 200 determines that there is broken data in the traffic, the integrity monitor system 200 may notify the host system 250 that the integrity of the data is broken. As described above, the integrity monitor system 200 monitors the integrity of the traffic traveling on the system bus 265 to perform a more reliable operation. The configuration and connection relationship of the memory controller 220 will be described below.

In addition, although the memory controller 220 is configured in a form included in the integrity monitor system 200 in an embodiment, it may be located in the host system 200 according to an embodiment.

In addition, in the embodiment, the integrity monitor system 200 may be connected to and operate on the host system. When the integrity monitor system 200 is connected, the integrity monitor system 200 is connected to the system memory 255 and the system bus 265. The system memory 255 may be controlled to prevent the connection.

Referring to FIG. 3A, the memory controller 305 of the integrity monitor system may include a memory access unit 310 and a setting unit 315.

The memory access unit 310 may be connected to the system memory and the system bus. Based on the control command input to the setting unit, the system memory may be accessed to perform a read or write operation. In addition, one or more programs and data may be received from the system bus to perform a write operation to the system memory, or one or more of programs and data read from the system memory may be transferred to the system bus.

The setting unit 315 may control the operation of the memory access unit 310 based on the received control command. In an embodiment, the setting unit 315 may be connected to a local bus of the integrity monitor system. The control command may also be received from a local processor of the integrity monitor system. In addition, in the present embodiment, the control command may be received through a local bus. More specifically, when a read or write command is received from the system processor of the host system from the system bus, the memory access unit may be controlled to access the system area on the system memory. In addition, when the access command is executed from the local processor of the integrity monitor system, the setting unit 315 may control the memory access unit to access the security area on the system memory based on the command. The message received by the setting unit 315 may be received through a local bus.

Referring to FIG. 3B, the memory controller 305 of the integrity monitor system may include a memory access unit 310 and a setting unit 315.

The setting unit 315 may control the operation of the memory access unit 310 based on the received control command. In an embodiment, the setting unit 315 may be connected to a local processor of the integrity monitor system. In another embodiment, the control command may be received from a local processor of the integrity monitor system. More specifically, when a read or write command is received from the system processor of the host system from the system bus, the memory access unit may be controlled to access the system area on the system memory. In addition, when an access command is received from the local processor of the integrity monitor system, the setting unit 315 may control the memory access unit to access a security area on the system memory based on the command. The message received by the setting unit 315 may be received through a local bus.

Referring to FIG. 3C, the memory controller 305 of the integrity monitor system may include a memory access unit 310 and a setting unit 315.

The setting unit 315 may control the operation of the memory access unit 310 based on the received control command. In an embodiment, the setting unit 315 may be connected to the system bus of the host system. More specifically, the local processor may be connected to the system bus through the local bus and transmit control commands to the setting unit through the system bus. In another embodiment, the control command may be received from a local processor of the integrity monitor system. More specifically, when a read or write command is received from the system processor of the host system from the system bus, the memory access unit may be controlled to access the system area on the system memory. In addition, when an access command is received from the local processor of the integrity monitor system, the setting unit 315 may control the memory access unit to access a security area on the system memory based on the command. The message received by the setting unit 315 may be received through a local bus.

According to an embodiment, the setting unit 315 may control how the memory access unit 310 is connected to the system memory according to a control command of the local processor. According to an exemplary embodiment, the security area of the system memory may allow access to the integrity monitor system only, and the independence of the integrity monitor system may be guaranteed by blocking the access attempts of other devices.

4A to 4C are diagrams illustrating signal flows of respective configuration diagrams according to embodiments of the present specification. In an embodiment, a signal may travel between one or more entities of the local processor 401, the local bus 402, the memory controller 403, the system memory 404, and the system bus 405. Although the embodiment describes the signal flow of the read command, the write command may also be performed in a corresponding structure.

4A is a diagram illustrating a signal transmission and reception method in the system of the structure of FIG. 3A.

Referring to FIG. 4A, in operation 410, the local processor 401 may transmit a memory read command to the local bus 402.

In operation 412, the local bus 402 may transmit the memory read command to the memory controller 403.

In operation 414, the memory controller 403 may transmit a read request to the system memory 404 based on the received memory read command. According to an embodiment of the present disclosure, an area corresponding to the memory read is a security area of the system memory 404 and may be an area accessible by the local processor 401. The area may be accessed according to a read command of the local processor 401 under the control of the memory controller 403.

In operation 416, the system memory 404 may transmit data stored in a corresponding area to the memory controller 403 according to the memory read request.

In operation 418, the memory controller 403 may transfer the received data to the system bus 405.

In operation 420, the system bus 405 may transfer the data received in operation 418 to the local bus 402.

In operation 422, the local bus 402 may transfer the data received in operation 420 to the local processor 401.

Through this process, the local processor 401 may access a corresponding region of the memory of the system 404 shared with the host system, and may be accessed under the control of the memory controller 403. Independence of the system can be ensured.

4B is a diagram illustrating a signal transmission and reception method in the system of the structure of FIG. 3B.

Referring to FIG. 4B, in operation 430, the local processor 401 may transmit a memory read command to the memory controller 403.

In operation 432, the memory controller 403 may transmit a read request to the system memory 404 based on the received memory read command. According to an embodiment of the present disclosure, an area corresponding to the memory read is a security area of the system memory 404 and may be an area accessible by the local processor 401. The area may be accessed according to a read command of the local processor 401 under the control of the memory controller 403.

In operation 434, the system memory 404 may transmit data stored in a corresponding area to the memory controller 403 according to the memory read request.

In operation 436, the memory controller 403 may transfer the received data to the system bus 405.

In operation 438, the system bus 405 may transfer the data received in operation 436 to the local bus 402.

In operation 440, the local bus 402 may transfer the data received in operation 438 to the local processor 401.

Through this process, the local processor 401 may access a corresponding region of the memory of the system 404 shared with the host system, and may be accessed under the control of the memory controller 403. Independence of the system can be ensured. In addition, as the local processor 401 is directly connected to the memory controller 403, a faster operation is possible.

4C is a diagram illustrating a signal transmission and reception method in the system of the structure of FIG. 3C.

Referring to FIG. 4C, in operation 450, the local processor 401 may transmit a memory read command to the local bus 402.

In operation 452, the local bus 402 may transmit the memory read command to the system bus 405.

In operation 454, the system bus 405 may transmit the memory read command to the memory controller 403.

In operation 456, the memory controller 403 may transmit a read request to the system memory 404 based on the received memory read command. According to an embodiment of the present disclosure, an area corresponding to the memory read is a security area of the system memory 404 and may be an area accessible by the local processor 401. The area may be accessed according to a read command of the local processor 401 under the control of the memory controller 403.

In operation 458, the system memory 404 may transmit data stored in a corresponding area to the memory controller 403 according to the memory read request.

In operation 460, the memory controller 403 may transfer the received data to the system bus 405.

In operation 462, the system bus 405 may transfer the data received in operation 460 to the local bus 402.

In operation 464, the local bus 402 may transfer the data received in operation 462 to the local processor 401.

Through this process, the local processor 401 may access a corresponding region of the memory of the system 404 shared with the host system, and may be accessed under the control of the memory controller 403. Independence of the system can be ensured. In addition, in the embodiment, when the memory read command is transmitted to the memory controller 403, the command is transmitted through the system bus 405, so that the direct control command transfer interface is connected between the local processor 401 and the memory controller 403. You can pass a command even if there is no. According to an embodiment, when the memory controller 403 is located on the host system, the memory controller 403 may operate in the same structure as the embodiment of FIG. 4C.

On the other hand, the present specification and the drawings have been described with respect to the preferred embodiments of the present invention, although specific terms are used, it is merely used in a general sense to easily explain the technical details of the present invention and help the understanding of the invention, It is not intended to limit the scope of the invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

Claims

A memory access method in a memory controller of an integrity monitor system that shares memory with a host system,

Receiving a memory access instruction from a local processor of the integrity monitor system;

Accessing system memory of the host system according to the memory access command;

Receiving corresponding data from the host system based on the access command; And

Delivering the received data to the local processor;

And the system memory includes a secure area accessible by the memory controller when a memory access command is received from the local processor.
The method of claim 1,

Delivering the received data to the local processor

Transferring the received data to the local processor via a system bus of the host system and a local bus of the integrity monitor system.
The method of claim 1,

Receiving the memory access command,

Receiving the memory access command via a local bus of the integrity monitor system.
The method of claim 1,

Receiving the memory access command,

And receiving the memory access command through an interface directly connected with the local processor.
The method of claim 1,

Receiving the memory access command,

Receiving the memory access command via a local bus of the integrity monitor system and a system bus of the host system.
The method of claim 1,

The integrity monitor system

And a verification unit that monitors the integrity of data transmitted on a system bus of the host system through snooping.
The method of claim 1,

The system memory

And a system area accessible by the host system.
An integrity monitor system device that shares memory with a host system,

A local processor controlling the operation of the integrity monitor system; And

Receiving a memory access command from the local processor, accessing a system memory of the host system according to the memory access command, receiving corresponding data from the host system based on the access command, and receiving the received data A memory controller for transferring data to the local processor;

And the system memory includes a secure area accessible by the memory controller when a memory access command is received from the local processor.
The method of claim 8,

And the memory controller transfers the received data to the local processor through a system bus of the host system and a local bus of the integrity monitor system.
The method of claim 8,

The memory controller

And receive the memory access command over a local bus of the integrity monitor system.
The method of claim 8,

The memory controller

And receive the memory access command through an interface directly connected to the local processor.
The method of claim 8,

The memory controller

And receive the memory access command through a local bus of the integrity monitor system and a system bus of the host system.
The method of claim 8,

And a verification unit for monitoring the integrity of data transmitted on the system bus of the host system through snooping.
The method of claim 8,

The system memory

And a system area accessible to the host system.