WO2015043379A1

WO2015043379A1 - Memory accessing method and device

Info

Publication number: WO2015043379A1
Application number: PCT/CN2014/086355
Authority: WO
Inventors: 张柳航; 张立新; 侯锐; 江涛
Original assignee: 华为技术有限公司
Priority date: 2013-09-29
Filing date: 2014-09-12
Publication date: 2015-04-02
Also published as: CN104516822A; CN104516822B

Abstract

A memory accessing method and device are applied to the technical field of computer information. In the memory accessing method, when information corresponding to a first virtual address is missed in a TLB, in order to enable a computer system to access memory corresponding to the first virtual address, the computer system converts the first virtual address to obtain a second virtual address, calculates, according to a preset relationship between a first physical address corresponding to the first virtual address and a second physical address corresponding to the second virtual address, the first physical address, and then, accesses the memory according to the first physical address. In this way, when it is found that information corresponding to a virtual address, for example, the first virtual address is missed in the TLB, a conversion relationship between a virtual address and a physical address may not need to be obtained from a page table in memory of the computer system, but the first physical address corresponding to the first virtual address can be directly calculated, so that processing overheads for missing in the TLB are reduced.

Description

Memory access method and device

Technical field

The present invention relates to the field of computer information technology, and in particular, to a memory access method and device.

Background technique

In the process of executing the application, the computer needs to access the program loaded in the memory. When the computer accesses the memory, it is accessed through the physical address of the accessed memory, and the management of the memory in the computer generally adopts paging memory management in the paged memory. Under management conditions, the computer generates virtual addresses for memory for easy management.

Currently, in the computer, a translation look aside buffer (TLB) is used to store a frequently used page table (ie, a subset of the page table), and also stores information of a virtual address corresponding to the physical address. The physical address of the memory is stored, and the computer can convert the virtual address into a physical address through the TLB and complete the memory access. When the TLB in the computer is missing, the computer will obtain information such as the missing page table pointer in the TLB to access the page table, obtain the corresponding physical address from the virtual address under the paging memory management and the corresponding physical address from the page table, and replace the TLB. Corresponding entries make the overhead of TLB deletion processing generally larger.

Summary of the invention

The embodiment of the invention provides a memory access method and device, which reduces the overhead of the TLB deletion processing.

A first aspect of the embodiments of the present invention provides a memory access method, including:

Receiving an access request of the memory, where the access request includes a first virtual address of the memory to be accessed;

If the first virtual address is not stored in the bypass translation buffer TLB, converting the first virtual address to obtain a second virtual address;

Calculating the first physical address according to a preset relationship between a second physical address corresponding to the second virtual address and a first physical address corresponding to the first virtual address;

Accessing the to-be-accessed memory according to the first physical address.

In the first possible implementation method of the first aspect of the present disclosure, the converting the first virtual address to obtain the second virtual address specifically includes: converting the first virtual address into the first virtual address The nth virtual address that increments or decrements the direction as the second virtual address; the n is a positive integer greater than zero.

With reference to the first aspect of the embodiment of the present invention or the first possible implementation method of the first aspect, in a second possible implementation method of the first aspect of the embodiment, the second physical address corresponding to the second virtual address is used. Calculating the first physical address by using a preset relationship between the first physical address corresponding to the first virtual address, specifically:

If the first virtual address and the second virtual address correspond to consecutive physical addresses, calculating a physical address of the second physical address to obtain the first physical address;

If the second physical address and the first physical address are non-contiguous, and the memory unit corresponding to the second physical address and the first physical address is separated by m, if the memory unit corresponding to the first physical address is The second physical address is incremented by the physical unit of the physical address, and the m+1th physical address in the direction of the second physical address is calculated to obtain the first physical address; if the memory corresponding to the first physical address is The unit is a memory unit in which the second physical address decrements the physical address, and the m+1th physical address in the decreasing direction of the second physical address is calculated to obtain the first physical address, where the m is greater than 0. Integer.

In a third possible implementation method of the first aspect of the embodiment of the present invention, before the receiving the memory access request, the method further includes:

Assigning a corresponding physical address to consecutive virtual addresses, the physical addresses being partially or completely continuous;

The corresponding relationship between the virtual address and the physical address is stored in the TLB, and the flag bit corresponding to the physical address is stored, and the flag bit is used to indicate whether the consecutive virtual addresses correspond to physical addresses.

With reference to the third possible implementation manner of the first aspect of the embodiment of the present invention, in a fourth possible implementation manner of the first aspect of the embodiment of the present invention:

The converting the first virtual address to obtain the second virtual address comprises: converting the first virtual address into a second virtual address that is consecutive to the first virtual address;

Calculating the first physical address according to a preset relationship between the second physical address corresponding to the second virtual address and the first physical address corresponding to the first virtual address, specifically: if the The flag of the physical address indicates that the physical addresses corresponding to the consecutive virtual addresses are consecutive, and the physical address of the second physical address is calculated to obtain the first physical address.

With reference to the third possible implementation method of the first aspect of the embodiments of the present invention, in a fifth possible implementation method of the first aspect of the embodiments, the method further includes:

Information of the first virtual address and the first physical address is stored in the TLB.

With reference to the fifth possible implementation method of the first aspect of the embodiments of the present invention, in a sixth possible implementation method of the first aspect of the embodiments, the information storage of the first virtual address and the first physical address is performed. To the TLB, specifically:

Saving a correspondence between the first virtual address and the calculated first physical address to the TLB;

The flag bit corresponding to the first physical address is transferred from the page table of the computer system memory to the TLB.

A second aspect of the embodiments of the present invention provides a memory access device, including:

a request receiving unit, configured to receive an access request of a memory, where the access request includes a first virtual address of the memory to be accessed;

An acquiring unit, configured to: if the first virtual address in the access request received by the request receiving unit is not stored in the bypass conversion buffer TLB, convert the first virtual address to obtain a second virtual address;

An address calculation unit, configured to calculate the first physical address according to a preset relationship between a second physical address corresponding to the second virtual address converted by the conversion unit and a first physical address corresponding to the first virtual address ;

And an access unit, configured to access the to-be-accessed memory according to the first physical address calculated by the address calculation unit.

In a first possible implementation manner of the second aspect of the embodiments of the present disclosure, the acquiring unit is specifically configured to convert the first virtual address into an nth virtual address of the first virtual address increasing direction or decreasing direction As the second virtual address; the n is a positive integer greater than zero.

With reference to the second aspect of the embodiment of the present invention or the first possible implementation method of the second aspect, in the second possible implementation method of the second aspect of the embodiment, the address calculation unit is specifically used if The virtual address and the second virtual address correspond to consecutive physical addresses, and the physical address of the second physical address is calculated to obtain the first physical address;

If the second physical address and the first physical address are non-contiguous, and the memory unit corresponding to the first physical address is separated by m, if the memory unit corresponding to the first physical address is And the second physical address is incremented by the physical unit of the physical address, and the m+1th physical address in the increasing direction of the second physical address is calculated to obtain the first physical address; The memory unit corresponding to the address is the memory unit of the second physical address decrement direction physical address, and the m+1th physical address of the second physical address decrement direction is calculated to obtain the first physical address, where the m Is a positive integer greater than zero.

In a third possible implementation method of the second aspect of the embodiment of the present invention, the method further includes:

An address allocation unit, configured to allocate a corresponding physical address to consecutive virtual addresses, where the physical addresses are partially or completely continuous;

Corresponding storage unit, configured to store a correspondence between the virtual address and the physical address in the TLB, and store a mark bit corresponding to the physical address, where the mark bit is used to indicate whether the physical address corresponding to the consecutive virtual address is continuous .

With reference to the third possible implementation manner of the second aspect of the embodiment of the present invention, in a fourth possible implementation manner of the second aspect of the embodiment of the present invention:

The obtaining unit is specifically configured to convert the first virtual address into a second virtual address that is consecutive to the first virtual address;

The address calculation unit is configured to: if the flag bit of the second physical address indicates that the physical addresses corresponding to the consecutive virtual addresses are consecutive, calculate a physical address of the second physical address to obtain the A physical address.

With reference to the third possible implementation method of the second aspect of the embodiment of the present invention, the fifth possible implementation method of the second aspect of the embodiment of the present invention further includes:

And an information storage unit, configured to store information of the first virtual address and the first physical address into the TLB.

With reference to the fifth possible implementation method of the second aspect of the embodiment of the present invention, in the sixth possible implementation method of the second aspect of the embodiment, the information storage unit specifically includes:

a correspondence relationship storage unit, configured to store a correspondence between the first virtual address and the calculated first physical address to the TLB;

And a transfer unit, configured to transfer the mark bit corresponding to the first physical address from the page table of the computer system memory to the TLB.

In the memory access method of this embodiment, when the information corresponding to the first virtual address is missing in the TLB, in order to enable the computer system to access the memory corresponding to the first virtual address, the computer system converts the first virtual address to obtain the second a virtual address and corresponding to the first virtual address The preset relationship between the physical address and the second physical address corresponding to the second virtual address calculates a first physical address, and then accesses the memory according to the first physical address. When the TLB is found to be missing a virtual address, such as the information corresponding to the first virtual address, the conversion relationship between the virtual address and the physical address may not be obtained from the page table of the computer system memory, but the first virtual may be directly calculated. The first physical address corresponding to the address reduces the overhead of the TLB miss processing.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.

FIG. 1 is a flowchart of a memory access method according to an embodiment of the present invention;

2 is a flowchart of another memory access method according to an embodiment of the present invention;

3 is a flowchart of another memory access method according to an embodiment of the present invention;

4 is a flowchart of another memory access method according to an embodiment of the present invention;

FIG. 5a is a schematic structural diagram of storing a virtual address and a physical address in a TLB according to an embodiment of the present invention; FIG.

FIG. 5b is another schematic structural diagram of storing a virtual address and a physical address in a TLB according to an embodiment of the present invention; FIG.

FIG. 6 is a schematic structural diagram of a memory access device according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of another memory access device according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of another memory access device according to an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of another memory access device according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The present invention provides a memory access method, which is mainly applied to a computer system including a processor, a TLB, and a memory, and is executed by a processor. The flowchart is as shown in FIG. 1 and includes:

Step 101: Receive an access request of a memory, where the access request includes a first virtual address of the memory to be accessed.

Step 102: Determine whether the first virtual address is stored in the bypass conversion buffer TLB. If the storage is missed, the TLB may be missing, and the computer needs to perform step 103.

It can be understood that in the computer system, the paging memory management mode is adopted to manage the memory in the computer system. For the convenience of management, the computer system generates a virtual address for the memory, and stores the physical address of the memory in the memory by the form of a page table. A continuous virtual address may correspond to a contiguous physical address or a non-contiguous physical address. Thus, in the page table, a flag bit indicating whether the physical addresses corresponding to the consecutive virtual addresses are consecutive is stored. Specifically, one physical address corresponds to one flag bit, and the flag bit is used to indicate two consecutive virtual addresses. Whether the physical address corresponds to a backward or forward physical address; and the page table can also store other information of the corresponding memory unit of each physical address, such as the user's usage authority information for the memory unit, where the memory unit refers to The smallest division of data stored in a computer system. The computer system can save the virtual address corresponding to the physical address included in the page table and the page table frequently used in the memory to the TLB, so that when the conversion between the virtual address and the physical address is performed, the content of the search is relatively small, and The efficiency of memory access is greatly accelerated by greatly speeding up the conversion between the virtual address and the physical address. The TLB is a separate device between the memory and the processor, and the access request sent from the processor needs to query the TLB for the physical address before being able to query the physical address of the TLB. It is sent to the memory for reading and writing data.

When the computer system is performing a certain function, it needs to first access the information related to the function loaded in the memory, and when the memory needs to be accessed, the computer system triggers the method of the embodiment. During the running process of the computer system processor, the instruction (the instruction is the code of the application) is continuously executed. When an instruction for accessing the memory to be accessed is encountered, the processor generally executes an instruction by the following process: Instructions, decoding instructions, ie parsing, executing, accessing memory, and writing back. In this process, one of the units in the processor sends an access request for memory to another unit when it encounters an instruction to access the memory to be accessed. When another unit receives the access request, it is included according to the access request. The first virtual address is searched in the TLB to find whether the first virtual address is stored. If the TLB is not stored, the TLB may be deleted. In this embodiment, the computer system may pass the following steps 103 to 105. Obtaining a physical address corresponding to the first virtual address for memory access; it is conceivable that if the first virtual address hits the TLB, the first virtual address has been stored. In the presence of the TLB, the step 106 is performed directly, that is, the first physical address corresponding to the first virtual address is found in the TLB, and the memory to be accessed is accessed according to the first physical address that is found.

Step 103: Convert the first virtual address to obtain a second virtual address.

Specifically, when acquiring the second virtual address, the computer system may convert the first virtual address into the nth virtual address in the first virtual address increment direction or the decrement direction as the second virtual address, where n is a positive integer greater than 0. . For example, the first virtual address is converted into a second virtual address that is continuous with the first virtual address. Generally, the virtual address is represented by a virtual page number (VPN), and is converted into a continuous second virtual address. The computer system may add 1 or minus 1 to the virtual page number of the first virtual address to obtain a virtual page number of the second virtual address, thereby obtaining a second virtual address.

Step 104: Calculate a first physical address according to a preset relationship between a second physical address corresponding to the second virtual address and a first physical address corresponding to the first virtual address. The relationship between the first physical address and the second physical address may be pre-stored in the computer system by the user according to actual needs.

Step 105: Access the memory to be accessed according to the first physical address calculated in step 104.

Specifically, the computer system may first find, according to the virtual page number of the second virtual address, the information corresponding to the second virtual address in the TLB, including the second physical address, the mark bit, and the like; and then determine the second physical address and the first The relationship between the physical addresses, for example, according to the mark bits corresponding to the second physical address, the first physical address and the second physical address are consecutive, and the physical contiguous with the second physical address is directly obtained on the basis of the second physical address. The first physical address is obtained by the address; and if the physical address corresponding to the first virtual address and the second virtual address has a certain calculation rule, the first physical address is calculated according to the calculation rule, such as consecutive virtual addresses. In the corresponding physical address, the interval between the memory units of the adjacent physical addresses is m, and the first physical address is the physical address of the m+1th memory unit in the direction in which the second physical address is incremented or decremented, where m Is a positive integer greater than zero.

Wherein, if the second virtual address is not stored in the TLB, the computer system may convert the second virtual address to obtain another virtual address according to the methods of

steps

103 and 104, and according to the second virtual address and another virtual address. The relationship between the corresponding physical addresses is calculated by the physical address corresponding to the other virtual address, and then calculated according to the method in step 104 above. To the first physical address. In this way, the physical address information missing in the TLB can be calculated one by one according to the methods described in the

above steps

103 and 104, and the first physical address is finally calculated to perform memory access.

It should be noted that, when the first virtual address is deleted in the TLB, the method for calculating the first physical address corresponding to the first virtual address is mainly for consecutive virtual addresses corresponding to consecutive virtual addresses; or for consecutive virtual addresses. Corresponding to the discontinuous physical address, and the non-contiguous physical addresses have a certain calculation law with each other, so that the missing physical address can be calculated according to the information that is not missing in the TLB. And the consecutive physical addresses indicate the physical addresses corresponding to the adjacent memory units.

It can be seen that, in the memory access method of this embodiment, when the information corresponding to the first virtual address is missing in the TLB, in order to enable the computer system to access the memory corresponding to the first virtual address, the computer system converts the first virtual address. Go to the second virtual address, and calculate a first physical address according to a preset relationship between the first physical address corresponding to the first virtual address and the second physical address corresponding to the second virtual address, and then access according to the first physical address. RAM. When the TLB is found to be missing a virtual address, such as the information corresponding to the first virtual address, the conversion relationship between the virtual address and the physical address may not be obtained from the page table stored in the memory of the computer system, but the first calculation may be directly obtained. The first physical address corresponding to a virtual address reduces the overhead of the TLB miss processing.

In a specific embodiment, as shown in FIG. 2, when the computer system performs the above step 104, it may be specifically implemented by the following

steps

1041 and 1042, specifically:

Step 1041: Determine whether the first virtual address and the second virtual address correspond to consecutive physical addresses, and if yes, perform step 1042; if not, and there is no certain rule between the second physical address and the first physical address, The first physical address cannot be directly calculated, and the first physical address corresponding to the first virtual address needs to be obtained by accessing the page table stored in the memory of the computer system.

Step 1042: Calculate a physical address of the second physical address to obtain a first physical address, where the physical address of the second physical address is a physical address of another memory unit adjacent to the memory unit corresponding to the second physical address.

In this embodiment, the computer system can learn whether the second physical address is continuous with the first physical address corresponding to the first virtual address by using a flag bit corresponding to the second virtual address stored in the TLB. The second physical address is calculated to obtain the first physical address, that is, The physical page number (PFN) of the second physical address is incremented or decremented by 1 to obtain a physical page number of the first physical address, thereby obtaining a first physical address.

It should be noted that if the second physical address and the first physical address are discontinuous through the above step 1041, the memory units corresponding to the second physical address and the first physical address are separated by m (m is a positive integer greater than 0) When the memory unit corresponding to the first physical address is the memory unit of the second physical address increment direction physical address, the computer system calculates the m+1th physical address of the second physical address increment direction to obtain the first physical address. If the memory unit corresponding to the first physical address is a memory unit with the physical address of the second physical address decreasing direction, the computer system calculates the m+1 physical address of the second physical address decreasing direction to obtain the first physical address, specifically The physical page number of the first physical address may be obtained by adding m+1 or minus m+1 to the physical page number of the second physical address, thereby obtaining the first physical address.

It should be noted that the above steps 101 to 106 are memory access methods executed by the computer system after the page table that is frequently used has been stored in the TLB. In another specific embodiment, the computer system may further perform the following steps. To implement the storage of the page table in the TLB, the flow chart is shown in Figure 3, including:

Step 201: Assign consecutive physical addresses to consecutive virtual addresses, and these physical addresses are partially or completely continuous.

Step 202: Store the correspondence between the virtual address and the physical address in the TLB according to the allocation in step 201, and store the flag bit corresponding to the physical address, where the flag bit is used to indicate whether the physical address corresponding to the consecutive virtual address is between continuous.

In this manner, the corresponding relationship between the virtual address and the physical address is stored in the TLB through the foregoing

steps

201 and 202, and the tag bit corresponding to the physical address is stored, so that when the TLB is missing, the physical area corresponding to the continuous virtual address is determined according to the tag bit. The relationship between addresses and directly calculate the missing physical address for memory access.

In this case, when the computer system performs the above step 103, the first virtual address is converted into a second virtual address that is continuous with the first virtual address; and when the above step 104 is performed, the computer system is first in the TLB. The flag bit corresponding to the second physical address is found. If the flag bit of the second physical address indicates that the physical addresses corresponding to the consecutive virtual addresses are consecutive, the physical address of the second physical address is calculated to obtain the first physical address.

In addition, it should be noted that, in other specific embodiments, when the computer system can calculate the first physical address through the foregoing steps 101 to 106, the memory access can be realized, but some physical addresses that are missing in the TLB are corresponding. Information still needs to be passed from the in-memory page table to the TLB, such as attribute information such as physical address information and tag bits. The computer system may be configured to store the information of the first virtual address and the first physical address into the TLB by using the following steps. The flowchart is as shown in FIG. 4, and includes:

Step 301: Store the correspondence between the first virtual address and the calculated first physical address to the TLB.

Step 302: The other information corresponding to the first physical address, such as a flag bit, is transferred from the page table of the computer system memory to the TLB, that is, the step of performing a Page Table Walk. The other information corresponding to the first physical address may further include usage permission information of the user for the first physical address, and the like.

There is no absolute order relationship between the

above steps

301 and 302, and there is no absolute order relationship between

steps

301 and 302 and step 105. They can be executed simultaneously or sequentially. The specific one shown in FIG. 4 is only a specific one. Method to realize.

In the following, a memory access method provided by an embodiment of the present invention is described in a specific embodiment. In this embodiment, an example in which consecutive addresses are incremented addresses is used as an example. In other embodiments, consecutive addresses may also be decremented. The address is not described here.

(1) Referring to FIG. 5a, in one case, the computer system maps consecutive

virtual addresses

11000, 12000, 13000, and 14000 in virtual memory to physical addresses in physical memory, respectively. 1000, 2000, 3000, and 5000 map consecutive virtual addresses to 3 consecutive physical addresses and 2 non-contiguous physical addresses.

In this embodiment, the computer system stores the physical address of the memory in the form of a page table in the memory, and records the tag bit corresponding to each physical address. If the value of the tag bit is "1", it indicates a certain physics. The address and its subsequent consecutive physical address respectively correspond to consecutive virtual addresses; if the value of the flag bit is "0", another physical address indicating that a physical address is consecutive backwards is not mapped to the physical entity The address corresponds to another virtual address in which the virtual address is continuous. The computer system stores the partial page table information that is frequently used and the virtual address corresponding to the physical address in the page table in the TLB. A TLB stores all information corresponding to a virtual address, including physical addresses and tag bits, and Each TLB is identified by a register identifier (ASID). And the virtual stored in the TLB The address and the physical address are respectively marked by a virtual page number and a physical page number, for example, the virtual page number of the virtual address 11000 is 11, and the physical page number of the physical address 1000 is 1.

Assume that the physical address of the entire page table in memory is a, given a virtual address b, another physical address c is obtained by a certain calculation method such as a+b, and the virtual address is stored in the memory corresponding to the physical address c. The physical address corresponding to b, this process is called page table index. Through the process of page table indexing, the computer can find the physical address corresponding to the virtual address, and then store the correspondence between the physical address and the virtual address in the TLB.

When the computer system needs to access the memory corresponding to the virtual address 12000, and the information corresponding to the virtual address is missing in the TLB, the computer system converts the virtual address into a virtual address 11000 consecutive to the virtual address; corresponding to the virtual address 11000. When the virtual address 11000 is mapped to the physical address of the virtual address 11000, the virtual address 12000 is mapped to the virtual address 11000. The virtual address 12000 is calculated according to the physical address 1000 corresponding to the converted virtual address 11000. The corresponding physical address is 2000; finally, the computer system accesses the memory according to the physical address 2000.

(2) Referring to FIG. 5b, in another case, the computer system maps consecutive

virtual addresses

11000, 12000, and 13000 and 14000 in virtual memory to

physical addresses

1000, 3000, and 5000 in physical memory, respectively. The consecutive virtual addresses are mapped to non-contiguous physical addresses, but among these non-contiguous physical addresses, the intervals between adjacent physical addresses are the same, and have certain regularity.

In this embodiment, when the computer system needs to access the memory corresponding to the virtual address 12000, and the information corresponding to the virtual address is missing in the TLB, the computer system converts the virtual address into a virtual address 11000 consecutive to the virtual address; According to the correspondence between the physical addresses corresponding to the

virtual addresses

11000 and 12000, that is, the physical addresses corresponding to the consecutive virtual addresses of 11000 to 13000 preset in the system, the memory corresponding to the adjacent physical addresses is separated by a memory. The unit calculates the physical address of the virtual memory address 12000 according to the physical address 1000 corresponding to the virtual address 11000 converted to the physical address, and obtains the physical address corresponding to the virtual address 12000; finally, the computer system according to the physical address 3000 to access the memory.

The embodiment of the present invention further provides a memory access device, that is, the above computer system, and a schematic structural diagram thereof is shown in FIG. 6 and includes:

The request receiving unit 10 is configured to receive an access request of a memory, where the access request includes a first virtual address of the memory to be accessed.

The obtaining unit 11 is configured to: if the first virtual address in the access request received by the request receiving unit 10 is not stored in the bypass translation buffer TLB, convert the first virtual address to obtain a second virtual address. Specifically, the obtaining unit 11 may convert the first virtual address into the nth virtual address of the first virtual address increment direction or the decrement direction as the second virtual address; the n is a positive integer greater than 0, for example, the obtaining unit 11 is The virtual page number of the first virtual address is incremented or decremented by 1 to obtain the virtual page number of the second virtual address, thereby obtaining the second virtual address.

The address calculation unit 12 is configured to calculate the first relationship according to a preset relationship between a second physical address corresponding to the second virtual address converted by the acquiring unit 11 and a first physical address corresponding to the first virtual address. Physical address.

Specifically, the address calculation unit 12 is specifically configured to calculate the physical address of the second physical address to obtain the first physical address if the first virtual address and the second virtual address correspond to consecutive physical addresses. If the physical address corresponding to the first virtual address and the second virtual address have a certain calculation rule, the address calculation unit 12 calculates the first physical address, such as the second physical address and the first physical address, according to the calculation rule. If the memory unit corresponding to the first physical address is a memory unit that is in the direction of the physical address of the second physical address, the address calculation unit is non-contiguous, and the memory unit corresponding to the first physical address is separated by m. The first physical address is obtained by calculating the m+1th physical address in the direction of the second physical address incrementing; if the memory unit corresponding to the first physical address is the memory unit in the physical address of the second physical address decreasing direction, Then, the address calculation unit 12 calculates the m+1th physical address of the second physical address decrement direction to obtain the first physical address, where m is a positive integer greater than 0.

The access unit 13 is configured to access the to-be-accessed memory according to the first physical address calculated by the address calculation unit 12.

In the memory access device of this embodiment, when the information corresponding to the first virtual address is missing in the TLB, in order to enable the memory access device to access the memory corresponding to the first virtual address, the obtaining unit 11 converts the first virtual address. a second virtual address, and the first physical address is calculated by the address calculating unit 12 according to a preset relationship between the first physical address corresponding to the first virtual address and the second physical address corresponding to the second virtual address, and then the access unit 13 Then access the memory according to the first physical address. When the TLB is found to be missing a virtual address, such as the information corresponding to the first virtual address, the conversion relationship between the virtual address and the physical address may not be obtained from the page table stored in the memory of the computer system, but the first calculation may be directly obtained. The first physical address corresponding to a virtual address reduces the overhead of the TLB miss processing.

Referring to FIG. 7, in a specific embodiment, the memory method device may include an address allocation unit 14, a corresponding storage unit 15, and a query access unit 16, in addition to the structure shown in FIG. 6, wherein:

An address allocation unit 14 is configured to allocate a corresponding physical address to consecutive virtual addresses, where the physical addresses are partially or completely continuous;

Corresponding storage unit 15 is configured to store the correspondence between the virtual address and the physical address in the TLB according to the allocation of the address allocation unit 14, and store the label bit corresponding to the physical address, where the flag bit is used to indicate the continuous Whether the physical address corresponding to the virtual address is continuous.

The query access unit 16 is configured to: if the first virtual address hits the bypass translation buffer TLB in the access request received by the request receiving unit 10, query the first physical address corresponding to the first virtual address in the TLB, And accessing the to-be-accessed memory according to the first physical address.

In this embodiment, the correspondence between the virtual address and the physical address may be stored in the TLB through the address allocation unit 14 and the corresponding storage unit 15, and the tag bit corresponding to the physical address may be stored, so that when the TLB is missing, the obtaining unit 11 may The flag bit determines the relationship between physical addresses corresponding to consecutive virtual addresses and directly calculates the missing physical address for memory access. When the TLB is not missing, the memory to be accessed is accessed through the query access unit 16. Specifically, the acquiring unit 11 specifically converts the first virtual address into a second virtual address that is continuous with the first virtual address, and the address calculating unit 12, specifically, the flag bit of the second physical address indicates the The physical addresses corresponding to the consecutive virtual addresses are consecutive, and the physical addresses consecutive to the second physical address are calculated to obtain the first physical address.

Referring to FIG. 8, in a specific embodiment, the memory method device may include, in addition to the structure shown in FIG. 6, an information storage unit 17 for using the first virtual address and the first physics. The information of the address is stored in the TLB. In a specific embodiment, the information storage unit 17 can be implemented by the correspondence relationship storage unit 170 and the delivery unit 171, specifically:

Correspondence relationship storage unit 170, configured to use the first virtual address and the calculated first physical address Corresponding relationship is stored to the TLB;

The delivery unit 171 is configured to transfer other information corresponding to the first physical address, such as a flag bit, from a page table in a computer system memory to the TLB, that is, a process of performing a Page Table Walk. The other information corresponding to the first physical address may further include usage authority information of the user to the first physical address, and the like.

Another embodiment of the present invention further provides a memory access device. The structure is as shown in FIG. 9. The memory 20, the processor 21, the input device 23, and the output device 24 are respectively connected to the bus, where:

The memory 20 is used to store data input from the input device 23, and may also store information such as necessary files for processing the data by the processor 21. In the present embodiment, the memory 21 includes a memory and a TLB; the input device 23 and the output device 24 are memory accesses. The port through which the device communicates with other devices may also include devices external to the memory access device such as a display, a keyboard, a mouse, and a printer.

The processor 21 is configured to receive an access request of the memory, where the access request includes a first virtual address of the memory to be accessed; if the first virtual address is not stored in the bypass translation buffer TLB, the first virtual The address is converted to obtain the second virtual address; the first physical address is calculated according to a preset relationship between the second physical address corresponding to the second virtual address and the first physical address corresponding to the first virtual address; And accessing the to-be-accessed memory according to the first physical address calculated by the address calculation unit. It is conceivable that if the first virtual address is already stored in the bypass translation buffer TLB, the processor 21 is further configured to query the TLB for the first physical address corresponding to the first virtual address, and according to the The first physical address accesses the to-be-accessed memory.

Specifically, when acquiring the second virtual address, the processor 21 converts the first virtual address into an nth virtual address in the first virtual address increment direction or a decrement direction as a second virtual address; A positive integer greater than zero. For example, adding or subtracting 1 from the virtual page number of the first virtual address to obtain a virtual page number of the second virtual address, thereby obtaining a second virtual address. When the processor 21 calculates the first physical address, if the first virtual address and the second virtual address correspond to consecutive physical addresses, the processor 21 calculates a continuous physical address of the second physical address to obtain the first physical address. If the physical address corresponding to the first virtual address and the second virtual address have a certain calculation rule, the processor 21 calculates the first physical address according to the calculation rule, for example, if the second physical address and the first If the physical address is not continuous, and the memory unit corresponding to the first physical address is separated by m, if the memory unit corresponding to the first physical address is the If the physical unit of the physical address is incremented by the physical address, the m+1 physical address in the direction of the second physical address is calculated to obtain the first physical address; if the memory unit corresponding to the first physical address is The memory unit of the second physical address decrement direction physical address calculates the m+1th physical address of the second physical address decrement direction to obtain the first physical address, where m is a positive integer greater than 0.

Further, the processor 21 may be further configured to allocate a corresponding physical address to the consecutive virtual addresses, where the physical addresses are partially or completely continuous; and store the correspondence between the virtual address and the physical address in the TLB, and store the physical A flag bit corresponding to the address, the flag bit is used to indicate whether the physical addresses corresponding to the consecutive virtual addresses are consecutive. In this way, the correspondence between the virtual address and the physical address is stored in the TLB, and the tag bit corresponding to the physical address is stored, so that when the TLB is missing, the converting unit 11 determines the physical address corresponding to the consecutive virtual addresses according to the flag bit. Relationships and directly calculate missing physical addresses for memory access.

Further, after the processor 21 calculates the first physical address, the processor 21 may further be configured to store information of the first virtual address and the first physical address into the TLB. Specifically, storing a correspondence between the first virtual address and the calculated first physical address to the TLB; and transmitting other information corresponding to the first physical address, such as a flag bit, from a page table in a computer system memory To the TLB, the process of performing a Page Table Walk. The other information corresponding to the first physical address may further include usage authority information of the user to the first physical address, and the like.

A person skilled in the art may understand that all or part of the various steps of the foregoing embodiments may be performed by a program to instruct related hardware. The program may be stored in a computer readable storage medium, and the storage medium may include: Read only memory (ROM), random access memory (RAM), magnetic or optical disk, and the like.

The memory access method and device provided by the embodiments of the present invention are described in detail above. The principles and implementation manners of the present invention are described in the specific examples. The description of the above embodiments is only used to help understand the method of the present invention. And the core idea of the present invention; at the same time, those skilled in the art, according to the idea of the present invention, there will be changes in the specific embodiments and application scope. In summary, the content of the present specification should not be construed as the present invention. limits.

Claims

A memory access method, comprising:

Receiving an access request of the memory, where the access request includes a first virtual address of the memory to be accessed;

If the first virtual address is not stored in the bypass translation buffer TLB, converting the first virtual address to obtain a second virtual address;

Calculating the first physical address according to a preset relationship between a second physical address corresponding to the second virtual address and a first physical address corresponding to the first virtual address;

Accessing the to-be-accessed memory according to the first physical address.
The method of claim 1, wherein the converting the first virtual address to obtain the second virtual address comprises: converting the first virtual address into the first virtual address increment direction or The nth virtual address in the decrement direction is taken as the second virtual address; the n is a positive integer greater than 0.
The method according to claim 1 or 2, wherein the calculation is performed according to a preset relationship between the second physical address corresponding to the second virtual address and the first physical address corresponding to the first virtual address. The first physical address includes:

If the first virtual address and the second virtual address correspond to consecutive physical addresses, calculating a physical address of the second physical address to obtain the first physical address;

If the second physical address and the first physical address are non-contiguous, and the memory unit corresponding to the first physical address is separated by m, if the memory unit corresponding to the first physical address is The second physical address is incremented by the physical unit of the physical address, and the m+1th physical address in the direction of the second physical address is calculated to obtain the first physical address; if the memory corresponding to the first physical address is The unit is a memory unit in which the second physical address decrements the physical address, and the m+1th physical address in the decreasing direction of the second physical address is calculated to obtain the first physical address, where the m is greater than 0. Integer.
The method of claim 1, wherein before receiving the access request for the memory, the method further comprises:

Assigning a corresponding physical address to consecutive virtual addresses, the physical addresses being partially or completely continuous;

Storing the correspondence between the virtual address and the physical address in the TLB, and storing the physical address pair A flag bit that is used to indicate whether the physical addresses corresponding to the consecutive virtual addresses are consecutive.
The method of claim 4, wherein the converting the first virtual address to obtain the second virtual address comprises: converting the first virtual address to be continuous with the first virtual address Second virtual address;

Calculating the first physical address according to a preset relationship between the second physical address corresponding to the second virtual address and the first physical address corresponding to the first virtual address, specifically: if the The flag of the physical address indicates that the physical addresses corresponding to the consecutive virtual addresses are consecutive, and the physical address of the second physical address is calculated to obtain the first physical address.
The method of claim 4, wherein the method further comprises:

Information of the first virtual address and the first physical address is stored in the TLB.
The method of claim 6, wherein the storing the information of the first virtual address and the first physical address into the TLB comprises:

Saving a correspondence between the first virtual address and the calculated first physical address to the TLB;

The flag bit corresponding to the first physical address is transferred from the page table of the computer system memory to the TLB.
A memory access device, comprising:

a request receiving unit, configured to receive an access request of a memory, where the access request includes a first virtual address of the memory to be accessed;

An acquiring unit, configured to: if the first virtual address in the access request received by the request receiving unit is not stored in the bypass conversion buffer TLB, convert the first virtual address to obtain a second virtual address;

An address calculation unit, configured to calculate the first physical address according to a preset relationship between a second physical address corresponding to the second virtual address converted by the conversion unit and a first physical address corresponding to the first virtual address ;

And an access unit, configured to access the to-be-accessed memory according to the first physical address calculated by the address calculation unit.
The device according to claim 8, wherein the obtaining unit is specifically configured to convert the first virtual address into an nth virtual state in which the first virtual address is incremented or decremented The intended address is the second virtual address; the n is a positive integer greater than zero.
The device according to claim 8 or 9, wherein the address calculation unit is configured to calculate the second physical address continuously if the first virtual address and the second virtual address correspond to consecutive physical addresses. Physical address of the first physical address;

If the second physical address and the first physical address are non-contiguous, and the memory unit corresponding to the first physical address is separated by m, if the memory unit corresponding to the first physical address is The second physical address is incremented by the physical unit of the physical address, and the m+1th physical address in the direction of the second physical address is calculated to obtain the first physical address; if the memory corresponding to the first physical address is The unit is a memory unit in which the second physical address decrements the physical address, and the m+1th physical address in the decreasing direction of the second physical address is calculated to obtain the first physical address, where the m is greater than 0. Integer.
The device of claim 7 further comprising:

An address allocation unit, configured to allocate a corresponding physical address to consecutive virtual addresses, where the physical addresses are partially or completely continuous;

Corresponding storage unit, configured to store a correspondence between the virtual address and the physical address in the TLB, and store a mark bit corresponding to the physical address, where the mark bit is used to indicate whether the physical address corresponding to the consecutive virtual address is continuous .
The device according to claim 11, wherein the obtaining unit is specifically configured to convert the first virtual address into a second virtual address that is continuous with the first virtual address;

The address calculation unit is configured to: if the flag bit of the second physical address indicates that the physical addresses corresponding to the consecutive virtual addresses are consecutive, calculate a physical address of the second physical address to obtain the A physical address.
The device of claim 11 further comprising:

And an information storage unit, configured to store information of the first virtual address and the first physical address into the TLB.
The device of claim 13, wherein the information storage unit comprises:

a correspondence relationship storage unit, configured to store a correspondence between the first virtual address and the calculated first physical address to the TLB;

And a transfer unit, configured to transfer the mark bit corresponding to the first physical address from the page table of the computer system memory to the TLB.