WO2015052616A1

WO2015052616A1 - Monolithic led arrays for uniform and high-brightness light sources

Info

Publication number: WO2015052616A1
Application number: PCT/IB2014/064941
Authority: WO
Inventors: Frederic Stephane Diana; Arun Sundaram SUBBANARAYANAN; Ryan WELLMAN; Gregory GUTH
Original assignee: Koninklijke Philips N.V.
Priority date: 2013-10-09
Filing date: 2014-09-30
Publication date: 2015-04-16
Also published as: TW201528475A

Abstract

A wafer of light emitting elements is sliced/diced to create monolithic arrays of individual light emitting elements. To increase the light output intensity, more light emitting elements are included within the monolithic array. Accordingly, the light output intensity is determined by the number of light emitting elements that are included in the array. Because each light emitting element is the same, regardless of the number of elements in the array, the differently sized arrays need not be individually characterized. In like manner, because the light emitting elements in each array are fabricated on the same wafer, under the same environmental conditions, all of the light emitting elements in the array will exhibit common light output characteristics.

Description

MONOLITHIC LED ARRAYS FOR UNIFORM AND HIGH-BRIGHTNESS LIGHT SOURCES

FIELD OF THE INVENTION

This invention relates to the field of light emitting devices, and in particular to a light source comprising a monolithic array of light emitting elements. BACKGROUND OF THE INVENTION

The ever expanding use of semiconductor light emitting devices has produced a highly competitive market for these devices. In this market, performance and price are often significant for providing product distinction among vendors.

Light emitting elements are typically grown on a wafer ('growth substrate') and include an active light emitting material sandwiched between an N-type semiconductor and a P-type semiconductor. Hundreds or thousands of light emitting elements may be grown simultaneously on the growth substrate, with 'lanes' or 'streets' separating each of the light emitting elements. The light emitting elements are singulated into individual light emitting 'chips' by slicing/dicing along these dividing streets and removing the growth substrate. One or more of these singulated chips may be mounted on a submount that provides structural support to the light emitting chips and provides a means for connecting the chip to an external source of power.

The light output intensity is dependent upon the current that flows through the light emitting element; however, the heat produced within the light emitting element is also dependent upon this current, and thus the maximum current, and therefore light output, is limited by the allowable junction temperature (typically 125°C). In addition, the LED efficacy drops with increased junction temperature and with increased current density due to the "droop" effect. In order to address these issues one way is to increase the surface area of the LED. This allows to decrease the current density of the LED and improve its efficacy, and at the same time decrease its thermal resistance and lower the junction temperature. This comes at the expense of cost, reliability (larger size LEDs are usually more fragile) footprint, and source size (etendue). Larger LED source size impacts the secondary optics size which are usually needed in LED lamps. This in turn leads to additional cost increases and to larger lamp volume and weight. Additionally, to prevent, for example, localized bright regions and dim regions across larger surface areas, more sophisticated fabrication techniques may be required. Each different fabrication technique will generally require different layout techniques, perhaps different processing techniques, and so on. In addition to the design and testing overhead associated with each differently sized design, the more sophisticated processes required for larger surface area light emitting elements increase the per-unit-area fabrication costs. That is, convention fabrication techniques for light emitting elements are not directly 'scalable' for increasing light output intensity by increasing surface area, per se.

Another technique for improving the performance of a light emitting device is to increase the light output intensity from the device, often by packaging multiple light emitting chips within the device. A plurality of the aforementioned submounted chips may be placed on a larger mount, such as a printed circuit board, suitable for packaging as a single light emitting device. Wavelength conversion material, such as phosphor may be added, to either each individual chip on a submount, or to a plurality of the chips on the larger mount.

The larger mount may include circuit traces that serve to interconnect the chips on the submounts in a desired manner, often as a series connection of light emitting chips of the same color. The circuit traces may also include contact pads or other structures for providing external power to the light emitting device.

The light emitting device may also include an optical element, such as a collimating lens, that serves to provide a desired light output pattern. The optical element may include features that serve to direct the light from each submount chip in a desired orientation relative to the light from the other submounted chips. Recent advances have allowed for eliminating the submount by providing self- supporting light emitting elements. As disclosed in copending U.S. patent application 61/568,297, "FORMING THICK METAL LAYERS ON A SEMICONDUCTOR LIGHT EMITTING DEVICE", filed 8 December 2011 for Alexander Nickel, Jim Lei, Anneli Munkholm, Grigoriy Basin, Sal Akram, and Stefano Schiaffino (Attorney Docket

2011P00972), and incorporated by reference herein, thick metal layers are added to each of the N-layer and P-layer contacts, separated by an insulating material. These metal layers provide the structural support to the light emitting element, and form contact pads for the light emitting element when used in a 'flip-chip' configuration.

Copending U.S. patent application 61/656,691, "CHIP SCALE LIGHT EMITTING

DEVICE WITH METAL PILLARS IN A MOLDING COMPOUND FORMED AT WAFER LEVEL", filed 7 June 2012, for Jipu Lei, Stefano Schiaffino, Alexander Nickel, Mooi Guan Ng, Grigoriy Basin, and Sal Akram, (Attorney docket 2012PF00450) and incorporated by reference herein, discloses providing a multiple pillars upon the N-type and P-type contacts pads and embedding these pillars in a molding compound. The pillars provide the mechanical support and conductivity, while the molding compound prevents distortions in the pillar structure.

In like manner, techniques have been developed that allow the light emitting element to remain on the growth substrate, the growth substrate providing the structural support for the singulated light emitting elements. In such an embodiment, after singulation, the light emitting element emits light into the remaining (transparent) substrate, and the light is emitted from the opposite surface, or the sides, of the substrate. A Patterned Sapphire Substrate (PSS) may be used as the growth substrate, the pattern on the substrate serving to enhance light extraction into the substrate by reducing the likelihood of total internal reflection at the interface between the light emitting element and the sapphire substrate.

By providing a self-supporting light emitting chip, conventional 'pick and place' manufacturing techniques may be used to place these self-supporting chips directly upon the aforementioned larger mount, such as a printed circuit board.

A disadvantage of placing multiple light emitting elements within a light emitting device, however, is that different light emitting elements, and particularly light emitting elements from different fabrication wafers may exhibit different light output characteristics, and this variance may render some of the devices unsuitable for their intended purpose. SUMMARY OF THE INVENTION

It would be advantageous to provide a technique for increasing light output intensity that is easily scalable. It would also be advantageous to provide a scalable increase in light output intensity that does not necessarily impose a need to re-characterize differently scaled light emitting elements. It would also be advantageous to provide a scalable increase in light output intensity that provides a uniformity in light output characteristics.

To better address one or more of these concerns, in an embodiment of this invention, a wafer of light emitting elements is sliced/diced to create monolithic arrays of individual light emitting elements, with minimal gaps between the light emitting elements. To increase the light output intensity, more light emitting elements are included within the monolithic array. Accordingly, the light output intensity is determined by the number of light emitting elements that are included in the array. Because each light emitting element is the same, regardless of the number of elements in the array, the differently sized arrays need not be individually characterized. In like manner, because the light emitting elements in each array are fabricated on the same wafer, under the same environmental conditions, all of the light emitting elements in the array will exhibit common light output characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein:

FIGs. 1A-1C illustrate an example fabrication and singulation of prior art light emitting elements.

FIGs. 2A-2B illustrate an example fabrication and singulation of an array of light emitting elements.

FIGs. 3A-3B illustrate an example mounting of an array of light emitting elements upon a printed circuit board mount.

FIG. 4 illustrates an example printed circuit board that provides a plurality of printed circuit board mounts.

FIGS. 5A-5C illustrate an example fabrication of a light emitting device with an array of light emitting elements on a printed circuit board mount.

Throughout the drawings, the same reference numerals indicate similar or

corresponding features or functions. The drawings are included for illustrative purposes and are not intended to limit the scope of the invention. DETAILED DESCRIPTION

In the following description, for purposes of explanation rather than limitation, specific details are set forth such as the particular architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the concepts of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments, which depart from these specific details. In like manner, the text of this description is directed to the example embodiments as illustrated in the Figures, and is not intended to limit the claimed invention beyond the limits expressly included in the claims. For purposes of simplicity and clarity, detailed descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

FIGs. 1A-1C illustrate an example fabrication and singulation of prior art light emitting devices 100, which is a portion of a wafer. FIG. 1 A illustrates a side view of the wafer and FIG. IB illustrates a top view of a wafer including a substrate 110 upon which many semiconductor light emitting elements 120 are formed. FIG. 1C illustrates an individual light emitting device 100 which includes a portion of substrate 110, a single light emitting element 120 and two contacts 130A, 130B. The substrate 110 may be a transparent material, such as sapphire, through which the light from the light emitting elements 120 is transmitted. The light emitting elements 120 typically includes multiple layers in including an active light emitting region sandwiched between an N-type and P-type semiconductors. Contact pads 130 (130A-130B in FIG. IB) allow for coupling of external power to each of the N-type and P-type semiconductors.

Hundreds, or thousands, of light emitting elements 120 may be formed on the substrate 110. Upon completion of the fabrication of these elements 120 on the substrate 110, the substrate 110 is sliced/diced as illustrated by the cutting lines 150, to 'singulate' each light emitting device 100, as illustrated in FIG. 1C.

FIGs. 2A-2B illustrate an example fabrication and singulation of an array 200 of light emitting elements 120. In this example embodiment, the individual light emitting elements 120 may be formed on the substrate 110 using conventional fabrication techniques. To form an array 200 of light emitting elements 120, the substrate 110 is sliced/diced along cutting lines 250, leaving multiple light emitting elements 120 physically connected to each other. The individual light emitting elements 120 are delineated in FIG. 2 A by the dashed lines, although there may not be a visible delineation between these elements. For example, a layer of the light emitting elements 120 closest to the contact pads 230 may be a dielectric layer that extends into the unused regions ('streets') between the light emitting devices 200.

In this example embodiment, the cutting lines 250 result in four light emitting elements 120 within each array 200. Of particular note, each array 200 is monolithic, in that all of the elements 120 within each array 200 are produced concurrently using the same process and are integrally connected, physically. Electrically, however, each of these light emitting elements 120 is independent of the other light emitting elements, and operates as an individual light emitting element 120. Accordingly, each of the light emitting elements 120 can be expected to exhibit the same performance and reliability characteristics as the light emitting element 120 in the conventional light emitting device 100 of FIG. 1C.

Each array 200 of light emitting elements 120 includes the two contact pads for coupling to each of the N-type and P-type semiconductors of each light emitting element 120, illustrated as contacts 23 OA through 23 OH in FIG. 2 A. That is, contact pads 230A-230B are coupled to one light emitting element 120; contact pads 230C-230D are coupled to another; and so on. The illumination of the array 200 may be controlled by providing a selective control of each light emitting element 120, or by providing a single source of power to all of the light emitting elements 120 in the array 200. For example, each of the light emitting elements 120 may subsequently be connected in series, allowing for a single pair of contacts for external control of the array 200 of light emitting elements 120.

In the example of FIGs. 2A-2B, all of the light emitting elements 120 are uniformly disposed on the substrate 110, and differently arranged arrays may be formed by slicing along the appropriate streets between the arrays. For example, a 4x2 array of light emitting elements may be provided by eliminating the cuts 250A, 250C. In this manner, the choice of the number and shape of light emitting elements 120 within a particular array can be made as a last step in the process, and the wafer that provides these uniformly disposed light emitting elements can be fabricated without regard to the eventually slicing to provide a particularly sized or shaped array. One of skill in the art will recognize, however, that if the size and shape of the array is known a priori, the light emitting elements 120 may be laid out on the substrate 110 to optimize the production of the particular array. For example, the width of select streets between the light emitting elements 120 may be reduced if that street is not included in the pattern of cutting lines for the array. That is, in FIG. 2A, the streets identified by dotted lines can be narrower than the streets identified but cutting lines 250 if it is known a priori that the arrays will be 2x2 arrays (or multiples thereof), because the narrower streets do not need to accommodate the width of the kerf of the slicing process at cutting lines 250.

One of skill in the art will also recognize that custom layouts based on an a priori definition of the size and shape of the array may also allow for the use of predefined connections between the light emitting elements. For example, if the wafer of FIG. 2 A, which includes many 2x2 arrays 200, is expected to have the light emitting elements 120 within the array 200 connected in a particular fashion (series, parallel, series-parallel, etc.), the layout of this a priori defined array configuration on the substrate 110 may include the appropriate interconnections among the light emitting elements to effect the intended connection pattern.

Alternatively, the interconnection of the light emitting elements within the array may be effected via the submount upon which the array is mounted.

FIGs. 3A-3B illustrate an example mounting of an array 300 of light emitting elements 120 upon a printed circuit board mount 370. In this example embodiment, the array 300 is a 3x2 array of light emitting elements 120, with six pair of contacts, 330A through 330L. As illustrated in FIG. 3B, the array 300 is 'flip-chip' mounted on the mount 370, such that the contacts 330A-330L are on the 'lower' surface of the array 300, and the substrate 110 through which light is emitted is the 'upper' surface of the array 300.

The printed circuit board mount 370 includes a pattern of circuit traces 360A-360L that are arranged to couple the six light emitting elements 120 in series with each other. A first trace 360 A provides for an external coupling to contact 33 OA of a first light emitting element of the array 300. A second trace 360BC provides for an external coupling from contact 330B of the first light emitting element to contact 330C of a second light emitting element in the array 300, placing the second light emitting element in series with the first light emitting element. In like manner, 360DE provides coupling from contact 330D of the second light emitting element to contact 330E of a third light emitting element, and so on. Circuit trace 360L provides for an external coupling to contact 330L of the last light emitting element. Providing power to circuit traces 360A and 360L will provide a current to each of the six light emitting elements 120 in the array 300 in series.

One of skill in the art will recognize that although a series connection is illustrated, the circuit traces 360 may be arranged to provide alternative interconnections between the contacts 330A-330L as desired.

The mount 370 may also include other components 390, such as ESD protection devices, temperature sensing devices, driving circuits, and the like. Although illustrated as a single component 390 (in FIG. 4) that is coupled in parallel with the series arrangement of the array 300 of light emitting elements 120, one of skill in the art will recognize that additional components may be included on each mount, with circuit traces to provide the desired circuit arrangement.

In like manner, one of skill in the art will recognize that the mount 370 is not limited to a printed circuit board, per se. The circuit traces 360, and optional components 390 may be situated within a lamp structure, on a flexible circuit substrate, and so on, as the situation warrants, each of which may be referred to as a 'mount' for the purposes of this disclosure and claims.

One of skill in the art will also recognize that although the circuit traces 360 that serve to couple the individual light emitting elements 120 are situated on a separate mount 370, the interconnecting circuitry may be applied as a final metal layer upon the light emitting elements 120, interconnecting the contact pads of one light emitting element 120 to another light emitting element 120 in the array 300. Because such interconnections may be provided as a final step in the fabrication process, the basic characteristics of the light emitting elements 120 are unchanged, and only the final mask layers need be customized to form each array 300 of interconnected light emitting elements 120.

In an example embodiment, the printed circuit mount 370 may be a larger printed circuit board that includes a plurality of sets of traces 360, as illustrated in FIG. 4. In this embodiment, a plurality of arrays 300 of light emitting elements 120 are mounted on the larger mount 370, using, for example, a pick and place process, then coupled/soldered to the traces 360 in a single process. In like manner, additional processing of multiple arrays 300 may be performed on the larger mount 370, such as the addition of wavelength conversion material or optical lenses to each array before the larger mount 370 is sliced/diced to provide singulated light emitting devices, each device comprising an array 300 of well matched light emitting elements 120. FIGS. 5A-5C illustrate an example fabrication of a light emitting device with an array 500 of light emitting elements 120 on a printed circuit board mount 570. In this example embodiment, the array 500 is a 6x6 array of light emitting elements 120 on a substrate 110, as illustrated in FIG. 5A.

FIG. 5B illustrates a printed circuit mount 570 that provides traces 560A, 560Z for external coupling to the array 500, and a pattern of traces 560 that arrange the 6x6 array of light emitting elements 120 in series between these traces 560A, 560Z. The printed circuit mount 570 may include other traces for interconnecting other devices, such as one or more ESD protection devices, temperature sensing devices, driver circuits, and the like.

FIG. 5C illustrates a completed light emitting device that includes an array 500 of light emitting elements 120, a mount 570 with traces 560A, 560Z that provide for external coupling to the array 500, and a lens 550 that protects the array 500. The lens 550 may be shaped to provide a desired light output pattern, and a wavelength conversion material may be included within the lens 550.

A wavelength conversion material (not illustrated), such as one or more phosphors, may also be applied to the array of light emitting elements 120, before the application of the lens 550, or in lieu of this lens 550. The wavelength conversion material may include a wavelength conversion film that is laminated to the array of light emitting elements 120. In one embodiment, a thermally efficient transfer tape is used to laminate the wavelength conversion film to the array of light emitting elements 120 before the mounting of the array on the submount 510. Alternatively, the wavelength conversion material may be applied to the light emitting elements 120 as a silicone, or other coating that is subsequently cured, or as a material that is sprayed or printed upon the array 500 of the light emitting elements 120 before application of the lens 550. The application of this material may include the use of a "dam and fill" process, common in the art. It is significant to note that each of the example arrays 200, 300, 500 use the same basic light emitting element 120. Accordingly, these arrays 200, 300, 500 can be assumed to have the same basic characteristics of this light emitting element 120, and further

characterization tests are not required. However, even though these arrays may have the same basic characteristics, array 200 can be expected to provide four times the light output intensity as the single light emitting device 100 of FIG. 1C; array 300 can be expected to provide six times the light output intensity; and array 500 can be expected to provide thirty- six times the light output intensity.

Additionally, each of these arrays 200, 300, 500 were formed by selectively slicing/dicing the substrate 110 to form the arrays, and the additional design time for these different arrays is merely the layout time for forming the appropriate circuit traces on the circuit board mounts. Some additional design time may be required to provide sufficient heat dissipation, particularly for the larger arrays, but the basic design of the light emitting element 120 is unchanged, regardless of the size of the array.

Although the example embodiments of this disclosure include an array of light emitting elements 120 on a substrate 110, one of skill in the art will recognize that the substrate 110 may be removed from the light emitting element 120. If the light emitting element 120 is self-supporting without the substrate 110, the substrate 110 may be removed before singulating the arrays; otherwise, the substrate 110 may be removed after mounting the array on the circuit board mount.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS:

1. A light emitting device comprising:

a monolithic array of light emitting elements, each light emitting element being adjacent to at least one other light emitting element that is concurrently and integrally formed on a common substrate.

2. The device of claim 1, wherein each of the light emitting elements in the array is substantially identical to the other light emitting elements.

3. The device of claim 1, including a mount upon which the array is situated, the mount providing circuit traces that facilitate coupling the array to an external power source.

4. The device of claim 3, wherein the mount includes other circuit traces that electrically couple the light emitting elements in the array together.

5. The device of claim 4, wherein the other circuit traces couple the light emitting elements in the array in a series connection.

6. The device of claim 3, including an optical element for transmitting light from the array of light emitting elements.

7. The device of claim 3, wherein the array is situated on the mount in a 'flip-chip' configuration.

8. The device of claim 3, including one or more other, non-light-emitting components situated on the submount and coupled to one or more of the circuit traces.

9. The device of claim 1, wherein the array includes at least four light emitting elements.

10. The device of claim 1, including the common substrate, wherein the common substrate is substantially transparent to the light emitted by the light emitting element.

11. The device of claim 1, including a wavelength conversion material that receives light of a first wavelength from the array of light emitting elements and emits light of a second wavelength.

12. A printed circuit board comprising:

a plurality of sets of circuit traces, each set of circuit traces being situated on the board to receive a monolithic array of light emitting elements and to provide for coupling the array of light emitting elements to a source of external power.

13. The printed circuit board of claim 12, wherein each set of circuit traces include circuit traces that interconnect the light emitting elements of each array when the array is coupled to the set of circuit traces.

14. The printed circuit board of claim 13, including each array of light emitting elements coupled to a corresponding set of circuit traces.

15. The printed circuit board of claim 14, including an optical element that is coupled to a light emitting surface of the array of light emitting elements.

16. The printed circuit board of claim 14, including a wavelength conversion material that receives light of a first wavelength from the array of light emitting elements and emits light of a second wavelength.

17. The printed circuit board of claim 14, including a plurality of sets of one or more other non-light-emitting components that are correspondingly coupled to the each array of light emitting elements.

18. A method comprising:

providing a plurality of light emitting elements upon a common growth substrate, and slicing the substrate to form monolithic arrays of light emitting elements, each array including adjacent light emitting elements that are formed on the common growth substrate.

19. The method of claim 17, including mounting the formed monolithic arrays of light emitting elements on a corresponding plurality of sets of circuit traces on a mount, and slicing the mount to form a plurality of submounts, each submount including one of the monolithic arrays.

20. The method of claim 18, including covering a light emitting surface of each of the monolithic arrays with at least one of: an optical element and a wavelength conversion material.