WO2015171680A1

WO2015171680A1 - Dram cells storing volatile and nonvolatile data

Info

Publication number: WO2015171680A1
Application number: PCT/US2015/029348
Authority: WO
Inventors: John Yit FONG
Original assignee: Fong John Yit
Priority date: 2014-05-07
Filing date: 2015-05-06
Publication date: 2015-11-12
Also published as: WO2015171683A1; WO2015171684A1; WO2015171811A3; WO2015171811A2

Abstract

A memory circuitry comprising at least two plate potential lines, L, at least one dynamic random access memory (DRAM) cell, N, for simultaneously storing volatile and single and/or multi-bit non-volatile data wherein each DRAM cell comprises a capacitor for separating the data including a storage node electrode for storing the volatile data and a plate electrode, such that said plate electrode is selectively coupled to one of said L plate potential lines to encode and store said nonvolatile data.

Description

DRAM CELLS STORING VOLATILE AND NONVOLATILE DATA

FIELD OF THE INVENTION

The present invention relates to dynamic random-access memory cells that can store at least 1 bit of volatile data on its DRAM capacitor storage node electrode simultaneously with 1 to 3 bits of nonvolatile data encoded on its plate electrode.

BACKGROUND OF THE INVENTION

Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or relatively discharged. These two states are taken to represent the two values of a bit, conventionally called 0 and 1 . Since "off' transistors always leak a small amount, the capacitors will slowly discharge, and the information eventually fades, unless the capacitor is refreshed periodically. This refresh requirement is referred to dynamic memory as opposed to static random access memory (SRAM) and other static types of memory.

Currently, the main memory (RAM) in personal computers is dynamic RAM (DRAM). It is the RAM in desktops, laptops and workstation computers as well as some of the RAM of video game consoles.

The advantage of DRAM is its structural simplicity: one transistor and a capacitor required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities. Unlike flash memory, DRAM is volatile memory (vs. non-volatile memory), since it loses its data quickly when power is removed. The transistors and capacitors used are extremely small; billions can fit on a single memory chip.

Due to the nature of its memory cells, DRAM consumes relatively large amounts of power, with different ways for managing power consumption.

FIG. 1A & B is representative of the state of the technology four decades ago. In particular it illustrates U.S. Patent No. 3,387,286 to R.H. Dennard entitled "Field-Effect Transistor Memory" (1968 IBM), which discloses a memory array of one transistor one capacitor (1 T1 C), dynamic random access memory (DRAM), cells with a bit line data bus. Each DRAM cell capacitor like, CO, has an independent storage node electrode like, Q0, and a "shared array plate electrode", PL0, where the shared or common plate is coupled to a "fixed value, voltage supply", in this case, Ground. Include in its entirety by reference, R. H. Dennard, "Field-Effect Transistor Memory", 1968 U.S. Patent 3,387,286, assigned to IBM.

FIG. 2 is representative of the state of the technology three decades ago. In particular it illustrates U.S. Patent No. 4,081 ,701 to L. White et al. entitled "High Speed Sense Amplifier for MOS Random Access Memory" (1978 Texas Instruments), which discloses a memory array like FIG. 1 of one transistor one capacitor (1 T1 C), dynamic random access memory (DRAM), cells with a bit line data bus, too. Each DRAM cell capacitor has an independent storage node electrode and continuing an industry trend or practice, a "shared array plate electrode", where the shared or common plate is, again, coupled to a "fixed value, voltage supply" in this case, VDD.

FIG. 3 is representative of the state of the technology two decades ago. In particular it illustrates, U.S. Patent No. 4,688,064 to Ogura et al., entitled "Dynamic Memory Cell and Method for Manufacturing the Same", (1987 Toshiba) which discloses a cross-sectional drawing of a memory array of 1 T1 C, DRAM cells as well. As in the previous 2 decades, these DRAM cells have a "shared array plate electrode", 53, where the shared or common plate is identified by its unique, North-West, to, South-East, hash marking, as seen in CELL3, CELL 1 and at the drawings right edge CELL2.

This 2 decade old trend from 1968 to 1987 shows that with a universal common plate electrode spanning memory arrays, extremely low plate resistance is maintained. This keeps voltage stability of stored electrical data like "1 "s and "0"s within these DRAM capacitors stable and free of noise coupling.

However, to continue shrinking, or scaling, these DRAM cells further, and yet maintain each DRAM capacitor 's capacity to store electric charge, the capacitors were next manufactured 3 dimensionally (3D) down into a memory chip's substrate, trench style, where the capacitor's depth was much greater than its diameter or width. These trench style DRAM cells are seen in FIG. 3.

3D DRAM capacitors above a chips substrate have been developed as well. FIG. 4 shows an example of the prior art from one decade ago. In particular it illustrates U.S. Patent No. 5,597,756 to Fazan et al. entitled, "Process For Fabricating a Cup-Shaped DRAM Capacitor Using a Multi-Layer Partly-Sacrificial Stack", (1997, Micron) which illustrates a cross-sectional drawing of a memory array of 1 T1 C, DRAM cells as well. Like in the previous 3 decades, these DRAM cells continued the industry practice of a "shared array plate electrodes", 82 which were "low plate resistance" and stored data "voltage stable", where the shared or common plate can be seen by its unique, diagonal hash marking, going from South-West to North-East in FIG. 4. Like FIG. 3 in order to keep each DRAM capacitor's "capacity" or, ability to store charge, the same, yet with reduced area, the capacitor's cell height is made greater than its length or width ("tall capacitor"). But now this DRAM 3D "cylindrical, cup-shaped" capacitor is manufactured above the memory cell's bit line, for example, a capacitor over bit line (COB) DRAM.

FIG. 5 shows a prior art collaboration of where DRAM arrays with 3D capacitors under bit lines (CUB) as in the previous 4 decades continue to short together DRAM capacitor plate electrodes to reduce DRAM capacitor plate resistance thereby boosting cell voltage stability and hence memory cell data integrity. See, Berthelot, A., et. al, "Highly Reliable TiN/Zr02/TiN 3D Stacked Capacitors for 45 nm Embedded DRAM Technologies", 2006 ESSDERC, European Solid-State Device Research Conference, pp. 343 - 346 (2006, STMicroelectronics, Philips, & Freescale ).

FIG. 6 shows U.S. Patent 7,449,383 to Kwang-Sub Yoon, et al., entitled "Method of Manufacturing a Capacitor and Method of Manufacturing Dynamic Random Access Memory Device Using the Same" (2008, Samsung), which discloses a DRAM array. To further scale or miniaturize the DRAM capacitor as before, yet maintain its capacity to store electric charge the same from previous generations, the capacitor plate electrodes, 128, are now made "several times higher than their base width" (see FIG. 6 of Kiyoo Itoh, etal. "Limitations and Challenges of Multi-Gigabit DRAM Circuits", 1996 Symposium VLSI) of their storage capacitor and are projected to continue to increase, and, in addition, are physically merged with adjacent cell plate electrodes into, truely, 3D single array plate electrodes covering entire cell blocks. Here in FIG. 6 pass transistors, T5, and, T6, allow bit line 5, BL5, data to be transferred into capacitors-over-bit lines (COB), C5, and, C6. Again, notice in the Samsung patent that the that the "Upper Electrode" of array cells are manufactured in one merged or integrated plate deposition (see prior art FIG. 6 upper electrode 128) forming a continuous 3D plate across the array block of memory cells.

More recently, FIG. 7 illustrates a reference to , Hyunwoo Chung, et al, "Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)", 201 1 European Solid-State Device Research Conference (ESSDERC) assigned to Samsung which discloses an array of vertical channel array transistors (VCAT), 3 dimensional, capacitor-over-bit line (COB), DRAM cells. Like examples before, the plate electrodes of the Samsung DRAM capacitors are all connected and merged together into a solid plate electrode that covers all the array cells. A single fixed voltage like, Vp, shown in the Samsung illustration, or PL in the Yamada et al. patent (Fig. 58) drives the plate electrodes of all the DRAM cells in unison Finally, in FIG. 58, U.S. Patent No. 7,804,700 to Yamada et al.(2010, Elpida), a 4F2 capacitor-over-bit line (COB) DRAM array is also shown where the access transistors are vertical channel as well. It is noted that again across a matrix of tall capacitor (TC) DRAM cells there is one single DRAM capacitor plate electrode continuous at least across a matrix line of cells. The tall capacitors (TC) referred to in this patent application refer to COB, CUB, and trench capacitor structures, or equivalent, or like with aspect ratios to be defined in ranges.

As illustrated in the representative prior art over the past decades the following forms of DRAM are known: planar plate DRAM; trench capacitor DRAM; capacitor-under -bit-line (CUB) DRAM; cup-shaped or cylindrical, capacitor-over-bit line (COB) DRAM and 3 dimensional, vertical channel array transistor (VCAT), CO DRAM, manufacturing or "depositing a continuous plate electrode across a matrix line of DRAM cells is an industry standard practice." Further, driving these single, universal DRAM capacitor plate electrodes with a single fixed voltage is also a decades old industry practice.

The benefits, of course, are the ease of manufacturing a continuous large layer or plate of metal, polysilicon, or the like, and the low noise characteristic of a low resistance, large capacitance, voltage plane, which also acts as a stable, fixed, voltage supply, whether for maintaining a fixed voltage such as 0V, VDD/2, VDD, etc.

Creating and manufacturing memory chips with a mix of DRAM memory arrays and Phase Change Memory (PCM) memory arrays is seen in U.S. Patent No. 7,554,147 to Asano et al. entitled "Memory Device and Manufacturing Method" (2009, Elpida). See specifically FIG. 16 with phase change memory film, 39, which is manufactured above the DRAM COB capacitor plate electrode, 36, insulation, 35, and lower storage node electrode, 34c, layers. In the Asano et al. patent, the phase change memory cells are kept separate from the DRAM cells. The invention provides a combination of these two types of memories.

In view of the underlying prior art previously described, today's computing needs are trending towards eye glass and wearable computers. In order for such computers to be commercially successful a dramatic drop in current computer system power is needed. Additionally battery size has to be slashed while phone and PC "in time" ("charged time" or "battery life") needs to be extended.

None of the prior art teaches or suggests the invention which provides a way to make a computer, smart phone system, or any device utilizing a chip, not only dramatically faster but also drops its power requirements.

The nonvolatile computer instructions and data normally needed for processing is typically far away external nonvolatile memory. In contrast the invention encodes and merges the nonvolatile computer data within a multi-core processor's DRAM cache memory itself.

In order to increase speeds the invention provides that the nonvolatile DRAM chip is flipped upside down and coupled to a processor chip right side up, capacitor side to transistor side, each chip facing each other. This power structure significantly utilizes less power and needs less time to communicate data between such a processor and its volatile DRAM memory, and also the nonvolatile memory.

For example, relatively short vias, simpler optical means even, etc. between chips could more simply communicate data chip to chip verses substantially larger resistance, substantially larger capacitance, using through silicon vias (TSV)s that chip manufacturers are currently experimenting with to transmit and receive data through chips verses between chips.

The invention provides a merger of far away nonvolatile data and instruction memory storage traditionally found in slow flash memory solid state drives and merges them into a significantly faster DRAM cache memory chip.

A general objective of the invention is to provide a "direct injection drive" dynamic random access memory to dramatically shorten the distance between (1 ) off chip nonvolatile mass storage memory i.e. Flash memory, for storing computer operating systems, programs, and data to (2) on chip Dynamic RAM main memory cells, measured on the order of centimeters like 2x10^"2 meters; to instead be slashed to as short as:(1 ) from within a DRAM cell's own internal capacitor plate electrode, to (2) a DRAM cell's own internal capacitor storage node electrode, measured on the order of 10s of nanometers like 20x10^"9 meters or approximately about 1 million times closer.

A resulting objective of the invention, due to the nanometer short distances used therein, is to provide mobile battery operated computing systems for cell phones, tablets, laptops, and the internet of things (IOT) such as Google glasses, iWatches and the like, with a tremendous drop in power by greatly reducing to potentially eliminating the need to access off chip Flash memory. The off chip Flash memory operates at generally 1 usec delay and 1 usec electric charging period. In contrast, the invention process of storing or embedding nonvolatile computer instructions and data directly within each DRAM cell's own internal plate electrode power structure itself, provides potentially a 10ns delay so 10ns electric charging period resulting in roughly 100 times less power in loading operating systems like Windows for PCs, Android or iOS for smart phones, as well as computer programs, and data while simultaneously almost erasing the bottleneck in narrow bus widths for computer data and instructions from Flash storage to DRAM. Furthermore, the invention allows for 1000s of DRAM banks of cells to be further loaded in parallel, making 100 times faster computer response times for instant on programs, instant on operating systems.

Another resulting object of the invention in combination with the simultaneously filed PCT application entitled "SRAM With 1 to 10 bits of Single Ended, Nonvolatile Latch Memory" which claims priority of provisional applications 61 /992,741 and 61/992,773 both filed May 13, 2014 (referred to herein as the "SRAM Application"), is to provide instant on, instant respond programs and operating systems to break down the Flash memory speed barrier thereby creating instant on, instant respond, human like artificial intelligence applications and computing devices and programs.

Another object of the invention is to provide a dynamic random access memory (DRAM) nonvolatile encoding via plate power structure, nonvolatile data, thereby, eliminating the need for about 60% to 70% power expenditure in computer main memory due specifically to DRAM refresh, where a lot of the program and data requirements will come not from volatile data, but from nonvolatile programs, operating systems, and fixed data.

Another object of the invention is to leverage the Dynamic RAM nonvolatile data encoding via plate power structure to allow for entire banks of DRAM to be shut down till needed to slash leakage power of DRAM cells.

A resulting, therefore, object of the invention is to extend mobile battery life for cell phones, tablets, laptops, etc. from one day at max to approximately a week or longer.

Still another object of the invention in concert with the SRAM Applications is to provide such a drop in power so that the thermal energy of a stack of direct injection drive Dynamic RAM chips in a Hyper Memory Cube can feasibly and thermally be directly coupled to a multi- core processor SoC (system on a chip) with "direct injection drive Static RAM memory" that a finger nail sized, super computer, die stack can be thermally feasible so that instant on, instant respond computing can instantly load and compute billions of direct injection drive nonvolatile instructions at 1 GHz to 3GHz speeds or 1000s of times faster than loading at 1 MHz speeds in conventional computing systems loading from Flash memory storage.

SUMMARY OF THE INVENTION

In the present invention, these purposes, as well as others are provided by a one dynamic random access memory (DRAM) cell innovation, preferably a two DRAM cell innovation, and an M + N = 4 or greater series of DRAM cell innovations.

The Dynamic RAM main memory of computing systems is made roughly 100 times faster in loading and so responding (ie. DRAM verses Flash speeds) while simultaneously slashing its power needs by roughly up to 10 times (ie. nonvolatile operation significantly eliminating Flash loading, DRAM refresh, and DRAM leakage). The invention accomplishes these contradictory goals by taking nonvolatile memory, normally Flash data, and bringing it about a million times literally closer in distance by nonvolatile encoding operating systems, programs, or data directly into each DRAM cell's own internal plate electrode power structure.

To direct inject these nonvolatile programs and data from each DRAM cell's capacitor's back side or plate electrode, power side, to its front side or storage node electrode or volatile data side, these DRAM cells are unusually operated backwards than standard DRAM industry practice ie. control of DRAM cells normally is done going forward from the pass transistor ie. the door to the cell, then into the storage node electrode where data is stored and then retrieved back out. However, the invention uses a new concept by making the plate electrode or power supply side of the DRAM cell serve not just for supplying power to the cell but also unusually function as a nonvolatile data entry into the cell ie. if the DRAM cell is a house and the transistor is the front door, the invention, unlike the current DRAM industry, creates a back door for nonvolatile data to enter through on the plate electrode or capacitor back side. The two methods of operating the DRAM cell from its back door, the plate electrode, to retrieve nonvolatile data at its front door, the bit line or data line we define later as either "Active Plate Pulsing" or "Passive Plate Pulsing".

The nonvolatile data is unusually transferred across the DRAM capacitor from back side to front side. The invention counts on the nonvolatile electrically encoded data that is stored on the plate or back side to create an invisible electric field to affect charge that will later be stored on the storage node electrode side. If that storage node charge is opposed or repelled by an electric field emanating from the back side or plate electrode, then data is encoded on the plate electrode or back side ie. like charges repel and unlike charges will attract. In fact, electrons could be repelled out the door or transistor onto the street or bit line making the data line a logic "0". Otherwise, electrons may be attracted or absorbed from the street, the bit line, through the door, the transistor, into the storage node electrode, because the plate electrode is highly charged positive.

Structurally, the invention can be used in the context of a bit lines (BL), word lines (WL), matrix or array of DRAM cells, at least a DRAM cell whose capacitor storage node electrode stores at least 1 volatile data bit can also have encoded simultaneously on its capacitor plate electrode 1 to 3 NONVOLATILE bits of data.

This nonvolatile data is purposely limited to be encoded on the DRAM capacitor plate electrode rather than any DRAM electrode, because the narrowing of invention scope allows the DRAM capacitor to be leveraged as an internal DRAM cell protection device or means of electrical and/or physical separation for one example as a substantial direct current (DC) isolation and so protect the storage node VOLATILE data AND the plate electrode NONVOLATILE data so they can coexist simultaneously without substantial short circuiting although some leakage current can be expected. Leveraging the DRAM capacitor both as a separation means as well as data storage means on both its electrodes accomplishes multiple functions with just one device. Also the capacitor usages as a separation means relieves any need to add and so enlarge the DRAM cell with extra transistors or worse severely slow the DRAM cell down by adding a floating gate device both alternative approaches with very negative consequences.

The NONVOLATILE data encoded on the DRAM capacitor plate electrode is via a "selectively supplied structure" or selectively coupled 1 of preferably at least L=2, 4, or 8 potential lines. Mathematically B = [[ LOG₂(L) ]]

where if L=2, then B=1 nonvolatile data bit stored, where if L=4, then B=2 nonvolatile data bits are stored,

where if L=8, then B=3 nonvolatile data bits are stored.

For example, along a series of at least, N = 2, 4, or 8, DRAM cells whose plates are selectively coupled or program encoded to a different 1 of L = 2, 4, or 8 potential lines respectively, each DRAM cell can be either hard or soft encoded with a unique, nonvolatile, binary coding preferably counting upwards from 0 to L. These series of DRAM cells and their L potential lines preferably follow the path of a word line (WL), or bit line (BL), or some other line of cells. For selective connections using metal lines alone, from above a DRAM memory array, these selective metal programmed connections can make the L potential lines look like substantially zig zag or serpentine patterns. For soft encoding or programmable couplings, resistive memories like phase change memory (PCM), conductive bridge RAM (CBRAM) elements, solid electrolytes, memristors, resistive RAM (ReRAM) or the like may be used.

For the 1 cell invention, this "selectively supplied structure" is substantially different in structure than the normal, predominantly used main memory DRAM storage cell because 1 is asymmetrically constructed verses symmetrically relative to the DRAM cell's plate electrode. The normal main memory cell has its plate electrode with simply a symmetrically constructed "supplied structure" to a universal plate or a a shared potential line.

For the 2 and 4 cell inventions, the "selectively supplied structure are substantially different than 1 another as well i.e.. they could be mirror images, different distances, etc.

An alternate embodiment to 1 b and 2b inventions above is that these "potential lines" are allowed to connect to the DRAM capacitor plate electrodes rather than to said DRAM cells' storage node electrodes. This limitation surprisingly adds a new feature to the volatile and nonvolatile DRAM inventions just described. Now, these volatile and nonvolatile DRAM cells are internally protected from short circuits that could occur if bit line writing of volatile data of 1 logic value and supplying of nonvolatile data of an opposite logic value to the same DRAM cells were ever to overlap in time. This is not an external memory cell scheduling solution to prevent conflict which can fail with signal skew, temperature fluctuation, and chip to chip manufacturing variations.

Another alternate embodiment to both the DRAM 1 b and 2b nonvolatile inventions above is as follows. The potential lines described above are furthermore connected or supplied through a variable resistance memory element such as a phase change memory (PCM) element. A further dependent embodiment to this phase change memory invention is that each said PCM element is coupled between a soft programming line (SPL) in a 1 ^st direction & a said potential line in a 2^nd direction. This structure can then be used to operate these DRAM cells with electrically rewriteable plate electrode to potential line combination nonvolatile data rather than simply mask programmed data.

In one embodiment the invention provides a dynamic random access memory (DRAM) cell for simultaneously storing volatile and non-volatile data comprising at least two plate potential lines, L a capacitor including a storage node electrode and a plate electrode. The plate electrode has access to each of said plate potential lines L and dynamically selectively couples to one of the plate potential lines L to allow encoding and storing of nonvolatile data. The capacitor separates the nonvolatile and volatile data such that the memory cell encodes and stores both nonvolatile data and volatile data simultaneously. The term dynamically is meant to mean that there is a selective choice to couple to one of the plate potential lines that can be programmed or dynamic.

In the DRAM cell the capacitor stores said volatile data on the storage node and the nonvolatile data is stored on one of said plate potential lines L.

The DRAM cell further includes bit lines (BL) and word lines (WL); and a transistor which is selected from the group consisting of a quantum field effect transistor and a field effect transistor utilizing lll-IV periodic table elements.

The DRAM cell selectively couples using a programmable memory element programmed to have a high or low resistance to be a logic "1 " or "0". The programmable memory element is selected from the group consisting of a phase change memory element (PCM), a memristor, a resistive random access memory a conductive bridge random access memory (CBRAM) and a solid electrolyte.

The capacitor is selected from the group consisting of a stacked capacitor, a tall capacitor (where the height is greater than its length or width), a capacitor over bit line (COB), a trench capacitor, and a capacitor under bit line (CUB).

In an alternate embodiment, the plate electrode maybe selectively coupled to one of the L plate potential lines by a metal connection.

In an alternate embodiment of the invention, a memory circuitry is provided comprising at least two plate potential lines, L, at least one dynamic random access memory (DRAM) cell, N, for simultaneously storing volatile and single and/or multi-bit non-volatile data. Each DRAM cell comprises a capacitor for separating the data including a storage node electrode for storing the volatile data and a plate electrode, such that the plate electrode is selectively coupled to one of the L plate potential lines to encode and store the nonvolatile data.

In each DRAM cell in the memory circuitry B = [[Log₂(L)]] + 1 wherein B = data bits or binary digits encoded and stored in each of said DRAM, N cell. Further when L=2, each DRAM cell encodes and stores B = 2 data bits/binary digits. When L=4, where said DRAM cell encodes and stores B = 3 data bits/binary digits. When L=8, where said DRAM cell encodes and stores B = 4 data bits/binary digits. Up to 4 data bits/binary digits of nonvolatile data and at least 1 data bit/binary digit of volatile data is stored simultaneously on each DRAM cell.

In the memory circuitry the DRAM, N cells are within bit lines (BL) and word lines (WL) array of memory cells. In a preferred embodiment the DRAM N cells are within the same WL and same BL.

The memory circuitry may further comprise multiple DRAM N cells arranged adjacent to each other, in rows of cells or in columns of cells wherein said potential lines are shared between said adjacent cells, rows of cells or columns of cells.

In a preferred embodiment each DRAM cell further include a single transistor. The transistor is selected from the group consisting of quantum field effect transistors and field effect transistors utilizing ll-IV periodic table elements for better transistor channels.

The DRAM cell in the memory circuitry selectively couples using a programmable memory element programmed to have a high or low resistance to be a logic "1 " or "0". The programmable memory element is selected from the group consisting of a phase change memory element (PCM), a memristor, a resistive random access memory a conductive bridge random access memory (CBRAM) and a solid electrolyte.

The capacitor used is selected from the group consisting of a tall capacitor, stacked capacitor, capacitor over bit line (COB), a trench capacitor, and a capacitor under bit line (CUB).

The plate potential lines of at least L=2 are substantially manufactured nonlinear which maybe serpentine or zigzag in construction..

Each DRAM cell in the memory circuitry may further include multiple transistors strictly for multi-port DRAM operation rather than encoding of nonvolatile data.

The invention also provides a method to simultaneously encode and store volatile and nonvolatile data bits within a dynamic random access memory (DRAM) cell comprising the steps of providing a DRAM cell comprised of a capacitor including a storage node electrode and a plate electrode; and at least two plate potential lines L. Creating an electric field on the inside of the capacitor by running power in reverse through the DRAM cell. Selectively coupling the plate electrode to one of the plate potential lines L, wherein the electric field permits the encoding and storing of the non-volatile data and running power forward through the DRAM cell so that the outside of the capacitor is electrified and can store volatile data.

Other objects, features and advantages of the present invention will be apparent when the detailed description of the preferred embodiments of the invention are considered with reference to the drawings, which should be construed in an illustrative and not limiting sense. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A and 1 B is a prior art illustration of U.S. Patent No. 3,387,286 to Dennard (1968 IBM patent) showing a memory array schematic of one transistor one capacitor (1 T1 C), dynamic random access memory (DRAM) cells each with plate capacitor electrodes electrically shorted together across an entire DRAM array and fixed at 1 supply voltage, ground.

FIG. 2 is a prior art illustration of U.S. Patent No. 4,081 ,701 to White et al. (1978 Texas Instruments patent) showing a memory array schematic of 1 T1 C DRAM cells with single plate capacitor electrode shorted across entire array and fixed at 1 supply voltage, VDD; shows open bit line sense amplifiers & core memory array rows and columns.

FIG. 3 is a prior art illustration of U.S. Patent No. 4,688,064 to Ogura et al. (1987 Toshiba patent) showing a cross-sectional drawing of a plurality of next store neighbor, 1 T1 C trench capacitor DRAM cells with capacitor plate electrodes shorted together across the DRAM

array.

FIG. 4 is a prior art illustration of U.S. Patent no. 5,597,756 to Fazan et al. (1997 Micron patent) showing a cross-sectional drawing of a plurality of next store neighbor, trench capacitor, DRAM cells where, again, the plate capacitor electrodes are electrical shorted together across an array.

FIG. 5 is a prior art illustration of cross-sectional drawing of a plurality of next store neighbor, metal-lnsulator-metal (M IM), capacitor under bit line (CUB), DRAM cells where the plate capacitor electrode is, again, electrical shorted together across an array as found in the article by Berthelot A. et al. entitled "Highly Reliable... 3D Stacked Capacitors for 45nm Embedded DRAM Technologies", 2006 ESSDERC (ST Microelectronics), European Solid-State Device Research Conference, pp.343-346, ( Freescale, STM, Phillips, see FIG. 2 and 3 therein).

FIG. 6 is a prior art illustration of U.S. Patent No. 7,449,383 to Yoon et al of a cross- sectional view of a plurality of 6F² capacitor-over-bit line (COB), DRAM cells where a single array "upper electrode" or "plate electrode" both physically covers and shorts all array cells.

FIG. 7 is a prior art illustration of an array of, 4F², COB, DRAM cells with vertical access transistor (VCAT), where a single array "plate electrode", again, both physically covers and electrically shorts together all memory cell plates, plus this plate is held at a fixed supply voltage, Vp as found in the article by Hyunwoo Chung, et al. "Novel 4F2 DRAM Cell with Vertical Pillar Transistor (VPT)", 2011 ESSDERC, European Solid-State Device Research Conference, by Samsung, pp.211 -214.

FIG. 8A is a programming table for storing 1 , 2, or 3 nonvolatile data bits into a DRAM cell by supplying a said DRAM capacitor electrode, preferably, the plate electrode, optionally, the storage node electrode, with 1 of a plurality of potential lines each said line spanning at least a plurality of said DRAM cells and, preferably, across some Matrix line of cells; and FIG. 8B is a flowchart for reading out, 1 bit at a time, each nonvolatile digit of a nonvolatile binary number stored within a single or multi-bit, nonvolatile, DRAM cell or cells.

FIG. 9 a generalized example schematic of a 1 b, 2b, 3b, or more nonvolatile DRAM cell with a reference DRAM cell to create a differential signal for a sense amp to amplify and optionally write back full signal to the originating cells. Nonvolatile data is shown stored within the nv DRAM by selective coupling the DRAM capacitor's, preferably, plate electrode to various supply lines like: V₀ to VN-L For example, the # of nv bits, B, stored can be calculated as: B = [[ LOG₂(N) ]], where, [[ ]] , is the greatest integer function and, N, is an integer 2 or greater. Folded bit line as well as open bit line DRAM cell & matrix layouts may be used.

FIG. 10 is an invention embodiment illustrating a 1 bit nonvolatile DRAM cell, storing the nv data, NVD = 1₂ or 1₁₀.

FIG. 11 is a timing diagram to read each binary digit or bit stored in the 1 bit nv DRAM cell of FIG. 10.

FIG. 12 is a timing diagram showing the various plate signals, V₀ to \Λ, that may be selectively driving the DRAM cell plate electrode of FIG. 10 to store a 1 bit nv #. In the case of FIG. 12, Vi is selectively driving causing a 1 or binary, 1₂, to be stored.

FIG. 13 is an invention embodiment illustrating a 2 bit nv DRAM cell, storing the nv data, NVD[1 :0] = 10₂ = 2₁₀.

FIG. 14 is a timing diagram to read each binary digit or bit stored in the 2 bit nv DRAM cell of FIG. 13.

FIG. 15 is a timing diagram showing the various plate signals, Vo to V3, that may be selectively driving the DRAM cell plate electrode of FIG. 13 to store & read out a 2 bit nv #. In the case of FIG. 15, V₂ is selectively driving causing a 2 or binary, 10₂, to be stored.

FIG. 16 is an invention embodiment illustrating a 3 bit nv DRAM cell, storing the nv data,

FIG. 17 is a timing diagram to read each binary digit stored in the 3 bit nv DRAM cell of FIG. 16.

FIG. 18 is a timing diagram showing the various plate signals, V₀ to V_7, that may be selectively driving the DRAM cell plate electrode of FIG. 16 to store a 3 bit nv #. In the case of FIG. 18, V₆ is selectively driving causing a 6 = binary, 1102, to be stored.

FIG. 19 is an invention embodiment illustrating a 1 , 2, 3, bit or more differential nv DRAM cell pair with a complement DRAM cell to create a larger differential signal for a sense amp to amplify and optionally write back full signal to the originating cells, nv data is shown stored within the nv DRAM by selective coupling the DRAM capacitor's plate electrode to various supply lines like: V₀ to V_N-i . Where, the # of nv bits, B, stored is calculated as: B = [[LOG₂(N) ]], where, [[ ]] , is the greatest integer function and, N, is an integer 2 or greater. Folded and open bit line cell and matrix array layouts may be utilized.

FIG. 20 is a timing diagram to read each binary bit stored in a 3 bit differential nv DRAM pair FIG. 19 hypothetical^ storing NVD[2:0] = 010₂.

FIG. 21 is a timing diagram showing the various plate signals, V₀ to V₇, that may be selectively driving the DRAM cell pair plate electrodes of FIG. 19 to store a 3 bit differential nv #. In the case of FIG. 21 , V₂ , & its complement, V₅, are selectively driving the DRAM cell pair plate electrodes causing a 2 = binary, 010₂, to be stored.

FIG. 22 are 1 b or more nonvolatile, 6F², capacitor over bit line (COB) DRAM cells, M0 and M1 , where the insulator between the DRAM cells is removed or not manufactured so that "individual plate electrodes", are unusually created & made available for being independently hard or soft programmed by "selectively driving" these plates, PL0, &, PL1 , via connections, C, and interconnect, i, to supply/programming lines P0₂ to P111₂.

FIG. 23 are 1 b or more, nonvolatile (nv), 4F², COB, DRAM cells, M1 , M2, and M3, where these DRAM cells are, unusually, made with "individual plate electrodes" covering only 1 DRAM cell each, in this embodiment, within a larger group of next store neighbor DRAM cells, so that each can be independently hard or soft programmed by "selectively driving" plate electrode, PL1 , to one supply/nv programming line of bus V[1 :0] to store 1 nv data bit; and, PL2, to one supply/nv programming line of bus V[3:0] to store 2 nv data bits; &, PL3, to one supply/programming line of bus V[7:0] to store 3 nv data bits. These V bus lines are shared between neighboring cells to reduce line resistance and increase nv programming speed. FIG. 24A and 24B represent a personal computer on 2 semiconductor chips with nonvolatile data sandwiched between; FIG. 24C and 24D represent a personal computer on 1 semiconductor chip with a SRAM and/or DRAM block selectively driven to store nonvolatile data as well as volatile data.

FIG. 25A is an example of Passive Plate Read, nv DRAM programming table while FIG. 25B shows one example flowchart for reading out each nonvolatile data bit stored 1 bit at a time.

FIG. 26A and 26B show a 1 bit nv DRAM schematic with passive plate pulsing used in the timing diagram to read out the nv stored data.

FIG. 27A, 27B and 28 show a 2 bit nv DRAM schematic with passive plate pulsing used in the timing diagram to read out the nv stored data.

FIG. 29 is the schematic of a 3 bit nv DRAM.

FIG. 30„ FIG. 31 and FIG. 32 show the timing diagrams to read the 0^th, 1 ^st , and 2^nd nonvolatile data bits of the 3b nv DRAM of FIG. 29 using passive plate pulsing to read out each nv bit 1 bit a time.

FIG. 33 shows a prior art illustration of a 4F2 DRAM cell in U.S. Patent No. 7,804,700 (Elpida) showing that a shared DRAM plate electrode is the common practice unlike the independent plate electrodes seen in the invention FIG. 22 and FIG. 23 .

FIG. 34 shows a 1 b to 3b nonvolatile, differentially coupled, DRAM memory cell pair, M1 and M2. With a supply/nv programming bus of V[1 :0] this cell pair is able to store 1 differential nv data bit. With a bus of V[3:0] this cell pair is able to store 2 differential nv data bits. With a bus of V[7:0] this cell pair is able to store 3 differential nv data bits.

FIG. 35 shows, M=2, one transistor (1 T), capacitor over bit line (COB) DRAM cells, M2 and M3, both using a same "individual plate electrode", PL23, but shared across 2 DRAM cells. Hence, both 1 T DRAM cells, M2 & M3, both store the same nonvolatile data (NVD) = 102 since selectively driven to P bus line, P102. However, both can store different volatile charge data.

FIG. 36A to 36I illustrate the invention single DRAM cell schematics and symbols depicting some of the invention variations within a "Matrix line of cells" some cells storing DRAM volatile and 1 bit of nonvolatile data i.e. DRAM capacitor electrode, potential line combination, nonvolatile data.

FIG. 37A, 37B and 37C show a matrix line of at least 4 Cells with DRAM capacitor electrodes supplied at least, M=2 and N=2, times by each 1 b potential line in a "random- like" and a "structured-like" nv data pattern.

FIG. 38A and 38B show a matrix line of at least 6 Cells with DRAM capacitor electrodes supplied at least, M=3 and N=3, times by each 1 b potential line in a "random-like" and a "structured-like" nv data pattern.

FIG. 39A and 39B show a matrix line of at least 8 Cells with DRAM capacitor electrodes supplied at least, M=4 and N=4, times by each 1 b potential line in a "random-like" and a "structured-like" nv data pattern.

FIG. 40 is a simplified 3D schematic of a negative slope of a matrix lines of 4, 6, and 8, Cells with DRAM capacitor plate electrodes supplied at least N=4, N=6, and N=8 times by each nonvolatile data encoding, 1 b potential line.

FIG. 41 is a simplified 3D schematic of a positive slope of matrix lines of 4, 6, and 8, Cells with DRAM capacitor plate electrodes supplied at least N=4, N=6, and N=8 times by each nonvolatile data encoding, 1 b potential line.

FIG. 42, FIG. 43 and FIG. 44 are simplified 3D schematic of hybrid DRAM cells, volatile and nonvolatile encoded data showing matrix lines of at least 4, 6, and 8 cells, respectively, whose DRAM capacitor electrodes are supplied at least by, M=2 and N=2; or M=3 and N=3, or M=4 and N=4 1 b potential lines that are criss-crossing.

FIG. 45A to 45G illustrates the invention single DRAM cell schematics and symbols depicting some of the invention variations within a "Matrix line of cells" some cells storing DRAM volatile and 2 bits of nonvolatile data i.e. DRAM capacitor electrode, potential line combination, multi-bit nonvolatile data.

FIG. 46 is a matrix line of 8 Cells with DRAM capacitor plate electrodes supplied at least, N=2, times by each 2b potential line in a "random-like" and "structured-like" nonvolatile data patterns.

FIG. 47 is a negative slope of matrix line of 8 Cells with DRAM capacitor plate electrodes supplied at least, N=2, times by each 2b potential line storing "random-like" and "structured-like" nonvolatile data patterns.

FIG. 48 is a positive slope of Matrix lines of 8 Cells with DRAM capacitor plate electrodes supplied at least, N=2, times by each 2b potential line storing "random-like" and "structured- like" nonvola tile data patterns.

FIG. 49 is a matrix lines of 12 cells with DRAM capacitor plate electrodes supplied at least, N=3, times by each 2b potential line storing "random-like" and "structured-like" nonvolatile data patterns. FIG. 50 and FIG. 51 are matrix lines of 16 cells with DRAM capacitor plate electrodes supplied at least, N=4, times by each 2b potential line storing "random-like" and "structured- like" nonvolatile data patterns.

FIG. 52A and 52B are matrix lines of at least 4, 6, and 8 cells whose DRAM capacitor electrodes are supplied at least, N=2, times by each criss-crossing 2b potential lines storing "random-like" and "structured-like" nonvolatile data patterns.

FIG. 53 shows a schematic of a DRAM cell with its tall capacitor plate electrode supplied by 1 of 2 potential lines V[0] or V[1 ] through a programmed resistive memory element.

FIG. 54A , 54B. and FIG 55. show different ways to build a DRAM cell with soft program line, 1 bit or multi-bit, plate electrode to potential line combination, rewriteable, nonvolatile data.

FIG. 56 and FIG. 57 illustrate 1 b or greater RW-NV DRAM programming showing how to connect the DRAM cell's plate electrode to 1 of the bus potential lines using a soft program line and phase change memory (PCM) elements.

FIG. 58 illustrates a prior art 1 , 2, 3 bit 4F^A2 Vertical Transistor, COB, Nonvolatile DRAM cells.

FIGS. 59A and B show a cross section and top view, respectively, of 1 b Read Writeable- Nonvolatile DRAM, 1 Layer PCM and ReRAM using a Soft Programming Line to Program and Disconnect.

FIG. 60 illustrates prior art 3D models or Read Only and Read/Writeable Models.

FIG. 61 illustrates a prior art model of prior art 4F^A2 DRAM Cell, Version 1 .

FIG. 62A, 62B and 62C illustrates a model of prior art 4F2 DRAM Cell Array with Shared Plate Power Plane, Version 1 , 2 and 3, respectively.

FIG.. 63A shows the invention embodiment of a 1 b DRAM Cell "selectively supplied structure to 1 of L=2 potential lines, and FIG . 63B shows the invention embodiment of a DRAM Cell which stores B=1 b of plate electrode to 1 of L=2 potential lines.

FIG. 64 shows the invention 2b DRAM Cells encoded with 00, 01 , 10, 11 NV Data bits.

FIG. 65 shows the invention cell stores B=2b of Plate Electrode to 1 of L=4 Potential Lines, NV Data.

FIG. 66 illustrates the invention 3b DRAM cells storing 000, 001 ,010, 011 , 100, 101 , 111 Data.

FIG. 67 illustrates the invention rewriteable DRAM-PCM Cell using Soft Programming Line. FIG. 68 illustrates the invention DRAM - PCM Cell Array.

DETAILED DESCRIPTION OF THE INVENTION

The specification, examples and figures used in this detailed description of the invention are to be considered only sample implementations of many possible invention embodiments and are not to be construed as invention limitations or limiting the invention's scope except as defined by the attached claims.

This application claims the benefit of U.S. provisional application no. 61/989,766 filed May 7, 2014 and U.S. provisional application no. 61/994,254 filed May 16, 2014 which are incorporated herein in its entirety by reference.

The Applicants PCT application entitled "4 BIT Nonvolatile Embedded DRAM" which claims priority of provisional application no. 61/994,254 filed May 16, 2014; and PCT application entitled "SRAM With 1 to 10 bits of Single Ended, Nonvolatile Latch Memory" which claims priority of provisional applications 61/992,741 and 61 /992,773 both filed May 13, 2014; and PCT application entitled "1 to 3 Bit Storage Node Rectifier or 2 to 3 Bit NV like VR or FG to Potential Line Combination NV Memory Cells and Systems (4 BIT NV Flash or VR Memory)" which claims priority of provisional application 61/994,254 filed May 16, 2014; are all being filed simultaneously with the present application and all three applications are hereby incorporated herein by reference in their entirety.

The following terms and phrases are used throughout the specification and have the meanings assigned thereto, unless otherwise specified.

1 . [[ ]] is the greatest integer math function. For example, [[ 1 .75 ]] = 2 , [[ 2.25 ]] = 3, etc.

2. DRAM = dynamic random access memory.

3. tall capacitor (TC) = a capacitor over bit line (COB), or capacitor under bit line

(CUB), or trench capacitor with acceptable aspect ratio of height to width at least 1 or higher like those other values defined herein.

4. mat transistor = as disclosed in U.S. Patent 5,377,142 to Matsumura et al. uses a means ... for "supplying a predetermined data signal to said capacitor" which can be seen in FIG. 4, 5, 7, 9, 10, 11 , 12, and 14 as: (a) 1 or more transistors, (b) these transistors each have 3 terminals, (c) these transistors each have 3 mask programmed connections, (d) these transistors are supplied by potential lines that are unidirectional, meaning they can be mask programmed to either (1 ) pull up a DRAM capacitor in voltage or float that connection or else (2) pull down a DRAM capacitor in voltage or float that connection so a "mat transistor" is the Matsumura 1 or more transistors, or equivalent, or like devices and also for anything as well with more of the above features such as more device terminals, more mask programmed connections, but still only each potential line driving these "mat transistor(s)" are limited to only unidirectional driving a DRAM capacitor.

5. nv = nonvolatile

6. BL = bit line

7. WL = word line

8. PCM = phase change memory typically some form of GST

9. matrix line of cells - This phrase doesn't mean a strict line per se but a series of DRAM cells forming either a line of or somewhat like a line of cells within at least a matrix of DRAM cells i.e. can have other memory cells between, and that series of DRAM cells can be straight, bowed, or curved, and not necessarily consistently consecutive i.e..can have other types of cells interspersed between, but will follow one of the following different embodiments or examples here described: (a) a word line with DRAM cells containing at least the, M+N, or, M+N+P+Q, etc. tall capacitor (TC) DRAM cells required included within ie. sometimes called a row of cells, (b) a bit line with DRAM cells containing at least the, M+N, or, M+N+P+Q, etc. tall capacitor (TC) DRAM cells included within i.e. sometimes called a column of cells, (c) a series of DRAM cells forming a consistently positive slope but not required to be constantly the same (+) slope throughout ie. the (+) slope can vary; note a 0 slope or (-) slope section of cells inbetween would be skipped or not included in this series of (+) slope DRAM cells, (d) a series of DRAM cells forming a consistently negative slope but not required to be constantly the same (-) slope throughout ie. the (-) slope can vary; note a 0 slope or (+) slope section of cells in between would be skipped or not included in this series of (-) slope DRAM cells, (e) although a zig zag series of DRAM cells is not included in this definition of a Matrix line, if a subset of those cells, even a nonconsecutive subset series of said zig zag cells follow a word line, follow bit line, follow a consistently (+) slope of tall capacitor DRAM cells, or follow a consistently (-) slope of tall capacitor DRAM cells, then those series of cells is within this invention's scope.

10. "at least a matrix of DRAM cells" - This phrase means that a matrix of DRAM cells can have other non-DRAM types of cells interspersed between, they would not deter from the tall capacitor DRAM cells from being within the invention's protection.

11 . LOG2(N) is the base 2 logarithmic function. 12. i.e.. = for example, 1 possible embodiment, also means other not included embodiments can exist.

13. pass transistor - Is a transistor controlled by a word line that allows charge transfer between a DRAM cell storage node and a bit line or input/output line.

14. 1T DRAM = a 1 pass transistor only dynamic random access memory (DRAM) cell. 15. 1 T1 C = a 1 pass transistor = 1 T, and 1 DRAM capacitor = 1 C, DRAM cell.

16. 2T1 C = a 2 pass transistor = 2T, 1 DRAM capacitor = 1 C, DRAM cell. One example is a dual port DRAM cell having 2 pass transistors.

17. Nonvolatile Data (NVD) with data bits [n:m], be written herein as NVD[ n:m ] , so for example, NVD[1 :0] = 102 , means the Non-Volatile Data digits or bits 1 to 0 equals 102■

18. 3D = three dimensional, while 2D = two dimensional.

19. H = typical DRAM 3 dimensional COB or CUB capacitor height depicted in the figures.

20. W = typical width of the 3D DRAM capacitor.

21 . "M, N" is an abbreviated form of the invention description phrase "said M and said N".

22. "M, N, P, Q" is an abbreviated form of the invention description phrase "said M, said N, said P, and said Q" but is not the abbreviated invention description phrase for (said M + said N + said P + said Q)

23. "allowed" - means prior art or this invention description might allow both or only 1 capacitor electrode to be substantially supplied or charged.

24 "potential line" - is an electrical conductor for carrying at least an electric potential or voltage from one point to another .

25. "different" - unless further specified, "different" in reference to a "potential line" is not referring to a potential line is physically wider, or electrically lower in resistance. This reference is not a difference in size or electrical performance. It refers to a "selection or choice" of another electrical conductor path or another potential line.

26. switch- at least a 2 terminal device that, in a first case, allows electric current to substantially flow between its 2 terminals or, in a 2^nd case, can substantially prevent electric current to flow. There must be a mechanism to control whether the switch allows substantial current flow or substantially restricts current flow. One example of a switch with such a mechanism is a diode. A diode is well known for having an abrupt voltage threshold where current can substantially flow through the device if this voltage threshold is first met or exceeded. If the voltage, however, across the diode is substantially below this voltage threshold, then the diode acts substantially like an open circuit. A second example of a switch is a transistor like a field effect transistor (FET) or like a bipolar junction transistor (BJT). However, unlike the diode the mechanism to allow the switch to allow substantial current flow requires a 3^rd terminal on the switch, a control terminal, that if again a voltage threshold is met or exceeded, the transistor can allow substantial current flow. If substantially below this threshold voltage the transistor is considered "off' and the transistor acts substantially like an open circuit.

27. DRAM cell capacitor- is a DRAM capacitor comprising: a storage node electrode for storing said DRAM's volatile, electric charge, data; a dielectric material; a plate electrode. It is constructed without using a transistor, ie. this is not referring to a 3 transistor DRAM cell where a transistor's gate is used as the DRAM's storage node electrode.

28. DRAM pass transistor - is a DRAM cell transistor comprising: a 1 ^st terminal for receiving electrical charge data from said DRAM cell capacitor's storage node electrode; a 2^nd terminal for transmitting said electrical charge data to a bit line; a control terminal for receiving a word line signal;

29. pass transistor only, DRAM cell- means a DRAM cell must have at least 1 pass transistor. Additional DRAM cell transistors are allowed but are optional. However, as stated "pass transistor only" means all DRAM cell transistors must all be pass transistors according to the definition of DRAM pass transistor above.

30. storage node electrode and electrical charge data - for example, in simplified terms, a DRAM cell capacitor's storage node electrode that a DRAM access transistor or pass transistor stores & accumulates electrical charge data upon ( ie. DRAM writing) and reads that electrical charge data charge back from and onto a bit line, this DRAM storage node capacitor electric charge can be volatile data that might require being refreshed due to charge leakage or to cosmic ray radiation.

31 . plate electrode - Continuing the example above, the opposite side DRAM cell capacitor electrode is specifically in this patent referred to as the plate electrode. This plate electrode, looking at prior art practice the last few decades, is typically found supplied a fixed, single, reference potential like the (-) negative, ground (GND) supply ie. 0 Volts; or VDD the (+) positive digital supply; or VDD/2 a midpoint voltage between the positive and negative digital power supply levels; etc. The typical purpose of this fixed electric potential on the plate electrode is to create a DRAM capacitor electric field, that attracts and holds onto any different polarity charge written to the storage node electrode. Furthermore, looking at prior art practice the last few decades, the DRAM memory array capactor plates are typically made as 1 electrically common, plate electrode for that array or sub array.

32. "physically separate" "selectively supplied" - This phrase is in reference to at least one DRAM capacitor plate electrode that it is manufactured as a capacitor plate electrode structure with electrical current insulation surrounding it like for 1 example, ie. silicon dioxide, the like or equivalent, etc. for electrically and physically isolating it from other capacitor plate electrodes on a specific same semiconductor chip layer or layers. This isolation allows these "physically separate" DRAM capacitor plate electrodes to be, for example, independently, "selectively supplied" or personally programmed to whatever, N, bus potential line needed to code them with the manufacturer's, vendor's, or personal user's own computer instructions, data, and the like. Again, these plate electrodes are then free to be electrically connected to any different or same, N, bus lines as desired. This freedom could be restricted to pre-manufacture in case of "mask programming" at the factory or vendor's site, or, in the case of plate electrodes selectively supplied through variable resistance memory elements ie. like phase change memory ie. like GST ie. like ReRAM or RRAM like a transition metal oxide that changes resistance significantly at a particular voltage, the like, or equivalent.

33. COB - a capacitor over bit line - This term specifically refers to a DRAM capacitor with its: (1 ) storage node electrode, (2) dielectric, and (3) plate electrode, manufactured in its entirety mostly or substantially above that specific DRAM cell's own bit line required for data transfer that is within that DRAM cell's own memory cell borders. It is constructed without using a transistor. Capacitor Over Bit Line (COB) designs became popular to actually solve a big problem. As the demand for DRAM chips with more and more data grew BUT the ability of capacitor technology specifically the capacitor dielectric to keep pace with storing ever denser and denser required electric fields for data storage, the only other recourse to keep shrinking memory chips was to shrink the memory cell's area but increase the DRAM capacitor's height while trying at best to make incremental improvements in the dielectric material to store the capacitor's electric field. COB DRAM capacitors provide the freedom to be made very tall in height yet small in width so to create great data storage density, YET by being manufactured substantially above the bit line they do not interfere with the manufacturing of and critical path speed of word line control and bit line data signals crucial to DRAM performance which are handled on a lower layer unaffected by these COB capacitors.

34. CUB - a capacitor under bit line - This term is used specifically for a capacitor with its storage node electrode, dielectric, and plate electrode, manufactured below a DRAM's bit line or data line layer. It is constructed without using a transistor.

35. 4F2 is defined in the article by Ki-Whan Song, et al. entitled "A 31 ns Random Cycle VCAT-Based 4F2 DRAM (Samsung Inc.), in the IEEE Journal of Solid-State Circuits, Vol. 45, No. 4, April 2010, pp. 880-886, see specifically figure 1 b a 3 dimensional drawing of a 2F x 2F or 4F2 DRAM cell.

36. 6F2 is defined in the article by Tsugio Takahashi, Kiyoo Itoh, et al. entitled "A Multigigabit DRAM Technology with 6F2 Open-Bitline Cell ..."IEEE Journal of Solid-State

Circuits, Vol. 36, No. 1 1 , Nov. 2001 , pp. 1721 -1726 see Figure. 2 for a 6F2 DRAM cell foot print drawing. To see an example cross-section of a 6F2 DRAM cell see U.S. Patent 7,592,219 to Tsung-De Lin Figure 1 1 .

37. selective" - a DRAM cell capacitor's plate electrode must have 2 or more different potential lines to be selectively supplied by in order to encode or store nonvolatile data.

38. soft programming line (SPL) a conductor stretching across at least 3 different variable resistance memory cells.

39. Vreset - stands for a variable resistance memory material a phase change memory (PCM) material ie. like a GST alloy, a relatively high voltage we are calling Vreset is applied to a phase change memory material that over a relatively short period of time will rapidly melt and make the PCM material amorphous ie. the atoms are substantially unlinked, and so relatively high resistance to electrical current. In the 2008 ISSCC conference reference [see Biblio 10] this high resistance can be in the millions of ohms region. This Vreset voltage pulse is quickly ended to freeze the now unlinked atoms in this relatively unlinked high resistance state typically called a RESET STATE.

40. Vcrystallize - stands for a variable resistance memory material, a phase change memory (PCM) material ie. like a GST alloy, [as disclosed in an Elpida, Febrary 10, 2011 , press release "Elpida and Rexchip R&D Center Achieve 4F2 Memory Cell 1 -Gigabit DDR3

SDRAM Prototype: Vertical Transistor Used to Develop 4F² Cell DRAM"] a relatively low voltage we are calling Vcrystallize is applied to a phase change memory material that over a relatively long period of time will slowly heat and substantially crystallize or link together the PCM atoms to create a relatively low resistance to electrical current flow. In the 2008 ISSCC conference this low resistance can be in the 10Kohm or less region. This low voltage Vcrystallize pulse is held for a long period to allow time for a substantial number of the PCM atoms to link together.

In view of the four decades of DRAM prior art described earlier, the present invention provides advantages by its novel structural approach to single or multi-port, 1 capacitor, DRAM design that is not taught or suggested by the prior art.

First, unlike the current practice of depositing a continuous DRAM capacitor plate electrode covering an entire DRAM memory block, the invention utilizes individual capacitor plate electrodes over single or small groups of DRAM cells.

Second, is the surprising advantage that each individual DRAM capacitor "plate electrode" or group of is free to be "selectively supplied by" or "programmed to" 1 of, preferably, N, newly created, binary coded plate electrode lines where N is an integer greater than 1 . These, newly introduced, binary coded, supply/programming lines are, preferably, binary coded sequentially from, 0, to, N - 1 . These "selective combinations" or, hard or soft encodings, for each DRAM cell or, group of cells to "different" binary coded, supply/programming lines, results in the storage of at least: B = [[ LOG2(N) ]], "different" nonvolatile bit(s) of data, respectively, per DRAM cell or group of cells. With proper binary operation of these, N, potential lines, each newly created, nonvolatile data bit stored can be selected and read out of each DRAM cell.

Preferably powers of 2 buses of, N, potential lines are considered best mode, but non- powers of 2 values of, N, are possible as long as program instructions and data accept the limitation that not all binary values of, B, bits are provided.

Third, unlike prior art DRAM arrays described with a storage capacitor's plate electrode only driven by a 1 voltage supply like, 0V, VDD/2, VDD, etc. for memory reading and writing, this invention operates plate bus programming or potential lines at one 1 voltage for DRAM mode but a set of pulsed voltages to access nonvolatile data made possible by electrically driving at least, N - 1 , said bus potential lines with at least 2 voltage supply drivers.

A 1 st plate pulsed method or embodiment is when plate pulses are from logic "0" to logic "1 " to logic "0", are performed during word line "on" DRAM cell accesses. This patent calls this type of plate pulsing an "Active Plate Read" and, preferably, the polarity of the nv data read out matches that of the binary encoded data. In other words, nonvolatile encoded or programmed data is read out non-inverted. A 2nd plate pulse method or embodiment uses either:

(A) a passive plate of a "1 " to a DRAM capacitor followed by the writing of a volatile "1 " that results in a zero net charge stored; or

(B) a passive plate of a "0" to a DRAM capacitor followed by the writing of a volatile "1 " that results in a net charge of a logic "1 " stored.

In this case, preferably, binary encoded nonvolatile data is read out inverted. This patent calls this a "passive plate read" since a data "1 " is read out when the plate is held passively at zero volts.

PROGRAMMING TABLE AND FLOW CHART (FIG. 8A and 8B)

FIG 8A and 8B illustrates the programming table and flow chart according to the invention. FIGS. 54A and B show a cross section and top view, respectively, of 1 b Read Writeable-Nonvolatile DRAM, 1 Layer PCM and ReRAM using a Soft Programming Line to Program and Disconnect

Specifically, FIG. 8A illustrates a nonvolatile DRAM programming table defining one example of how selectively supplied DRAM plate electrodes by a programming line, V[*], can store single to multiple bits of "Nonvolatile Data". The plate pulsing method shown in this FIG. 8A table follows the "Active Plate Read" method, where binary encoded or programmed nv data is non-inverted from what is actually read out of the DRAM cell or cells. Further, the plate or V[*] bus potential lines are "actively pulsed" when reading out DRAM nonvolatile (nv) data. The subsequent flow chart and timing diagrams follow the "actively pulsed" method. FIG. 25A and 25B herein describe an alternate method, "Passive Plate Read" nv DRAM data flow chart and timing diagrams. "Passive plate reads" read out binary encoded or programmed nv data in an inverted fashion.

FIG. 25B shows a flowchart of steps to read out each nonvolatile digit or bit of data stored using the "active plate method". The numbers (1 ) to (6) assigned to these steps are also shown in the timing diagrams at the bottom. The steps or items marked with a double astericks, **, indicate steps or parts of steps that are optional. They can either be performed during each read cycle of nonvolatile data or they can be done at other times ie. as part of DRAM refresh intervals, in other background processes, or solved through circuits or manufacturing of cells that allow leakage or discharge from the DRAM cells to remove any residual buildup of positive or negative charge thus removing any need for these optional steps at all.

This programming table and flow chart are explained in more detail in the next, B = 1 , 2, and 3 bit, N bus, selectively supplied - plate electrode, nonvolatile DRAM, programming and timing diagram examples that follow.

B Bit, Nonvolatile, DRAM System Overview (FIG. 9)

In a preferred embodiment a DRAM system implementation to read data from or write data to an N bit, nonvolatile, 1 transistor 1 capacitor (1 T1 C) DRAM cell is found in FIG. 9:

1 . MO, an N bit, nonvolatile, 1 T1 C DRAM,

2. Mref, a reference DRAM cell,

3. P1 & N 1 , a bit line driver circuit for writing, MO, the DRAM cell or reading from it, and P1 ' & N1 ' a bit line driver for writing, Mref, the reference DRAM cell or reading it, 4. E0 & E1 a bit line equalization circuit to initialize differential bit lines to the same voltages before the read data comparison process is begun.

5. P3, P2, P2', N2, N2\ & N3, a differential sense amplifier to compare & amplify the

DRAM signal to be read & the reference signal being compared against.

First, MO, the one transistor, one capacitor (1 T1 C) DRAM cell in top of the drawing like prior art comprises a pass transistor, NO, activated by a word line, WL, signal to allow volatile data from bit line, BL, to be written into it, or for volatile data to read out of it. Volatile data like a logic "1 " = "high" or a logic "0" = "low" is temporarily stored on DRAM capacitor, Cq's "storage node electrode" where Q is identified as the storage node.

Unlike the current art DRAM cells, this one has its DRAM capacitor's "plate electrode" "physically separate" from all others & so can be independently, "selectively supplied" by any 1 of, N, supply/ nv programming bus potential lines labeled, V₀ to V_N-i . This numerical combination of a "capacitor plate electrode, selectively supplied by 1 of N different bus lines" allows the encoding of, N, bit nonvolatile numbers within DRAM cell M0. This data is nonvolatile meaning even if power is lost to the system, the nonvolatile data is not lost. It is noted that soft encoding is made possible using a programmable coupling element between each, N, bus potential line and a nv DRAM capacitor's plate electrode using ie. phase change memory (PCM) elements.

Mathematically, the number of nonvolatile bits stored in such a DRAM cell is calculated in the equation as: B = [[ LOG₂N ]] where N = # of supply/programming lines that could selectively drive, MO's, DRAM capacitor plate electrode.

The DRAM cell, M0, in FIG. 10, FIG. 13 and FIG. 68 is referred to as Non-Volatile Data (NVD) of different binary bits = 1₂, 10₂ , and 110₂ be notated as:

NVD = 12 , NVD[1 :0] = 10₂ , NVD[2:0] = 110₂ Second, the nonvolatile DRAM data read out system, employs, Mref, a "Reference DRAM cell" with a capacitor that is either: (A) a fraction of the, MO, DRAM capacitor, like 12.5fF or half of 25fF as seen FIG. 9, where the plate pulsing signals to both reference & evaluated cells are equivalent, or (B) a same or similar value of the, MO, DRAM capacitor like 25fF ; however, the plate pulsing voltage is made a fraction of the voltage pulse used for, MO.

Both methods generate a mid point reference signal for a semi-differential signal comparison purpose allowing a "sense amplifier" labeled in FIG. 60 to discern an intended logic "1 " or logic "0" value coming from an, MO, DRAM cell being read out.

The example value for Cq = 25fF, and Cref = 12.5fF, as a possible mid point voltage creating reference capacitor, are simply, industry typical values as found like in the, 2006 I EDM Short Course by Howard Kirsch of Micron Inc. titled "Memory Technologies for 45nm and Beyond". Different values for Cref & Cq other than 25fF, 12.5fF, can be used and are definitely within the scope of this invention and claims.

Third, P1 & N1 , the bit line driver at the drawing top can write data into the, M0, 1 T1 C DRAM cell at the top through bit line, BL. Simultaneously, the same data is written into Mref, the reference cell at the drawing bottom through bit line, VREF, using its bit line driver transistors, PV and NT.

Fourth, a voltage equalization circuit formed by transistors, E0 and E1 are pass transistors for temporarily shorting bit line, BL, to be read and the reference signal bit line, VREF. Signals, EQL and EQH, will receive an "on" or "0" and a "1 " respectively when equalization of the bit lines is done then DRAM data can be read out onto bit lines.

Fifth, the sense amplifier labeled, SENSE AMP, can be used to amplify the small voltage difference between the DRAM cell MO's data read out onto bit line, BL, and the reference cell Mrefs signal read out onto the other bit line, VREF. Signals SAZ and SA turn on the differential SENSE AMP which would typically transmit data out of the DRAM memory array as well as write back a full voltage swing signal back into the DRAM cells for later volatile memory reads.

Sixth, a 2nd possible embodiment of a nonvolatile DRAM read out system uses an actual complementary nonvolatile DRAM reference cell matched for each regular nonvolatile DRAM cell so as to generate a full complementary logic swing differential signal for a differential sense amplifier to easily amplify and fully write back into DRAM cells to restore them to full strength logic levels. Although this circuit implementation requires 2 DRAM cells per pair of stored complementary or opposite logic values, the differential signal is about twice as large and so data read out by a differential sense amplifier can be much faster.

1 Bit Nonvolatile DRAM Cell Schematic (FIG. 10)

FIG. 10 shows an example schematic of a 1 bit, nonvolatile, 1 T1 C DRAM cell in top of the drawing. DRAM cell, MO, is "selectively supplied" by at least 1 of N=2 bus supply/ nonvolatile programming lines or potential lines labeled, V0 and V1 . This bus line, selectively supplied, plate electrode coupling combination encodes cell, MO, with 1 or 2 different nonvolatile (nv) binary values of, B, bits: B = [[ LOG2 N ]]

The programming of 1 nonvolatile bit is reflected in the FIG. 8A DRAM Nonvolatile Programming Table, lines 1 and 2, where plate electrodes, V[*] selectively supplied by programming lines, V1 , or, V0, are listed as storing the values of a nonvolatile I ₂ or O₂. In our example, potential line, V1 , is coupled to, so line 2 of the table applies. Hence, a nonvolatile, I ₂ is stored within DRAM cell, M0 or NVD = I ₂ (note: using Active Plate Pulsing method).

1 Bit Nonvolatile DRAM Cell Read Operation (using Active Plate Pulsing method)

Timing diagrams, FIG. 11 and FIG. 12, describe, an embodiment, to read out the 1 nv bit stored in DRAM cell, M0, in the schematic of FIG. 10 following the flowchart of FIG. 8B.

Step1 : Word Line, WL, is turned "on" = "1 " while Bit Line Driver signal, bit line high activated by a low, BLH(L) is also turned "on" = "0" to precharge DRAM, M0, with a BL="1 " to first remove any (-) or negative charge buildup on the data storage node, Q. Simultaneously, the equalization circuit with EQL- 'O" & EQH="1 " is turned "on" equalizing both bit lines, BL, and, VREF, to the same voltage. Step 1 is optional here and could be done outside this loop like during refresh or some other interval or even omitted ie. low leakage circuitry.

Step 2: Bit Line Driver with signal, bit line low activated by a high, BLL(H) is turned "on", driving bit line, BL = "0" while discharging, MO's, data storage node, Q, to "0" removing any (+) positive charge build up on the data storage node. This discharging of the data storage node to 0 is optional here and could be done outside this loop like during refresh or some other interval or ie. even omitted with low leakage circuitry; however the driving of the bit line, BL, here to 0V is needed to prep for the sense amplifier operation. Equalization is still on.

Step 3: The bit lines, BL and VREF, are floated by equalization circuit being shut off, EQL=1 =off and EQH=0=off.

Step 4: while the word line, WL, is turned "on", the plate signal, PL, is pulsed "on" = "1 ", (active plate pulsing) since the plate is selectively supplied to supply/programming line, V1₂, which is in timing diagram, FIG. 12.

Step 5: In FIG. 11 he sense amplifier is turned on by SAZ=0=on and SA=1 =on. This amplifies the small "1 " differential signal to a full supply voltage swing which is driven out the memory array for data transfer.

Step 6: The sense amplifier further writes back into the nonvolatile DRAM cell the data being read but at full supply voltage swing so as to store the nonvolatile data as volatile data within that cell for future memory cell reads.

2 Bit Nonvolatile DRAM Cell Schematic, (FIG. 13)

FIG. 13 shows an example schematic of a 2 bit, nonvolatile, 1 T1 C DRAM cell in top of the drawing. At address or word line, 5, memory cell, MO, here is "selectively supplied" by one of N = 22 = 4 plate supply/ programming lines or potential lines labeled, V0 to V3 = VOO2 to V11₂. This coupling encodes cell, MO, with N = 1 of 4 different binary values, or a 2b binary #:B = [[ LOG₂ N ]]

The programming of 2 nonvolatile bits is reflected in the FIG. 8A DRAM Nonvolatile Programming Table, lines 3 to 6, where plate electrodes, V[*] selectively supplied by programming lines, V00₂ to V11₂, are listed as storing nonvolatile values, 00₂ to 11₂, respectively. In our example, potential line, V₂, is coupled to cell MO's plate electrode so line 5 of the table applies. Hence, a binary, 10₂, is stored within DRAM cell, MO. NVD[1 :0]=

2 Bit nv DRAM Cell - Read MSB. Bit 1 . (FIG. 13 to 15)

To read out the most significant bit (MSB) or bit 1 of the nv number stored in MO, NVD[1 ] = 12, one must follow at least the required steps in flow chart FIG. 8B. Each plate programming line with its bit 1 coded as a "0" is cleared to "0" and each plate programming line with its bit 1 coded as a "1 " is set to a "1 " (Active Plate Pulsing).

In step 4, plate lines are pulsed "1 " if "1 " or stay "0" if "0" or non-inverted as follows: V00₂= "0", V01₂,= "0", V10₂,= "1 ", and V11₂= "1 ".

But since nv programming line, V10₂, above is selectively supplied by in the schematic, a nv data, 12, is AC plate electrode pulsed out onto bit line, BL, first.

2 Bit nv DRAM Cell - Read Out Bit 0, (See FIG. 13 to 15)

To read out the least significant bit (LSB) or bit 0 of the nv number stored in M0 a NVD[0] = 02, one must follow at least the required steps in flow chart FIG. 8B. Each plate programming line with its, LSB, bit 0 coded as a "0" is cleared to "0" and each plate programming line with its bit 0 coded as a "1 " is set to a "1 " (Active Plate Pulsing). V00₂= "0", V01₂,= \ V10₂,= "0", and V11₂= "1 ".

Since nv programming line, VOI 2, above is selectively supplied by in the schematic, a nv least significant bit of, 0₂, is read as a "0" on bit line, BL, which was already cleared to zero before reading.

3 Bit Nonvolatile DRAM Cell. (FIG. 16 to 18)

FIG. 16 shows an example schematic of a 3 bit, nonvolatile, 1 T1 C DRAM cell in top of the drawing. Memory cell, M0, here is "selectively supplied" by one of N = 23 = 8 plate supply/ programming lines or potential lines labeled, V0 to V7 = VOOO2 to V111₂,

This selective or personalized combination encodes cell, M0, with N = 1 of 8 different binary values, or a 3b binary #: B = [[ LOG₂ N ]]

The programming of 3 nv bits is reflected in the FIG. 8A DRAM nv Programming Table, lines 7 to 14, where plate electrodes, V[*] selectively supplied by programming lines, VOOO2 to V111₂, are listed as storing nv values, OOO2 to 11 ₂, respectively. In our example, potential line, V6, is coupled to cell MO's plate electrode so line 13 of the table applies.

Hence, a binary, 110₂ , is stored within DRAM cell, M0. NVD[2:0] = 610 = 110₂

3 Bit nv DRAM Cell - Read Out Bit 2 (FIG 16 to 18)

In the 3b nv DRAM schematic of FIG. 16 to read out the most significant bit (MSB) of the nv number stored in M0 or NVD[2] = 1₂, we , again follow at least the numbered steps in flow chart FIG. 8B. Each plate programming line with its bit 2 coded as a "0" is cleared to

"0" and each plate programming line with its bit 2 coded as a "1 " is pulsed with a "1 " (Active

Plate Pulsing).

So in, step 4, plate lines are pulsed "1 " if bit 2 =1 or stay "0" if bit 2 =0 as follows:

V000₂= "0", V001₂,= "0", V010₂,= "0", V011₂= "0";

V100₂= ', V101₂,= "1 ", V110₂,= "1 ", V111₂= "1 ",

But since nv programming line, V1102, above is selectively supplied by in the schematic, a nv data, 12, is AC plate electrode pulsed out onto bit line, BL.

3 Bit nv DRAM Cell - Read Out Bit 1 . (FIG. 16 to 18)

In the 3b nv DRAM schematic of FIG. 16 to read out bit 1 of the nv number stored in M0 at word line or address 2, NVD[1 ] = 1₂, we , again follow at least the required steps in flow chart FIG. 8B. Each plate programming line with its bit 1 coded as a "0" is cleared to "0" and each plate programming line with its bit 1 coded as a "1 " is set to a "1 " (Active Plate Non-inverted Pulsing).

So in, step 4, plate lines are pulsed "1 " if bit 1 =1 or stay "0" if bit 1 =0 as follows:

V000₂= "0", V001₂,= "0", V010₂,= "1 ", V011₂= "1 ",

V100₂= "0", V101₂,= "0", V110₂,= "1 ", V111₂= "1 ",

But since nv programming line, V110₂, above is selectively supplied by in the schematic, a nv data, 1₂, is AC plate electrode pulsed out onto bit line, BL.

3 Bit nv DRAM Cell - Read Out Bit 0, (FIG. 16 to 18)

In the 3b nv DRAM schematic of FIG. 16 to read out bit 0 of the nv number stored in M0 at word line or address 2, NVD[0] = 0₂, we , again follow at least the numbered steps in flow chart FIG. 8B. Each plate programming line with its bit 0 coded as a "0" is cleared to "0" and each plate programming line with its bit 0 coded as a "1 " is set to a "1 " (Active Plate Non-inverted Pulsing).

So in, step 4, plate lines are pulsed "1 " if bit 0 =1 or stay "0" if bit 0 =0 as follows:

V000₂= "0", V001₂,= "1 ", V010₂,= "0", V011₂= "1 ",

V100₂= "0", V101₂,= "1 ", V110₂,= "0", V111₂= "1 ",

But since nv programming line, V110₂, above is selectively supplied by in the schematic, a nv data, 0₂, is read out onto bit line, BL.

N Bit nv Differential DRAM Cells, (FIG. 19 to 21 )

Instead of using a semi-differential reference signal whether generated from a reference plate pulse the fraction of the voltage pulse sent to regular DRAM plate electrodes, or by using reference capacitors that are a fraction of the capacitance of regular DRAM capacitors, it is possible to create a completely differential reference signal resulting in approximately double the differential signal output and thus is faster to detect and process.

FIG. 19 uses an actual complementary nonvolatile DRAM reference cell matched for each regular nonvolatile DRAM cell so as to generate a full complementary logic swing differential signal for a differential sense amplifier to easily amplify and fully write back into DRAM cells to restore them to full strength logic levels. Although this circuit implementation requires 2 DRAM cells per pair of stored complementary or opposite logic values, the differential signal is about twice as large and so data read out by a differential sense amplifier should be much faster. Looking at FIG. 19 we see that as a 1 st example, DRAM cell, M0, is programmed to the supply/nv programming line, V_N-i , so the reference DRAM cell, ΜΌ, is selectively supplied by the binary complement or, V0₂. For a 2nd example, a 3 bit nv DRAM system with complementary nv DRAM reference cells is provided. There is a DRAM memory cell, MO, selectively supplied by a supply/nv programming line, V010₂ thus storing the Non-Volatile Data (NVD): NVD[2:0] = 210 = 010₂ So the DRAM reference cell, ΜΌ, will store the complementary nv binary value of: NVD[2:0]

This is what is read back, bit by bit, in the differential timing diagrams of FIG. 20 and 21 . Using again, "active plate pulsing", the nv data read back on bit line, BL, is non-inverted or 010₂. Notice for "active plate pulsing" the non-inversion. So, that in FIG. 20 the DRAM plate signal, PL, is 0 when the nv data read back is BL = "0" and the DRAM plate sgnal, PL, is 1 when the nv data read back is BL = "1 ". Notice as well that when the BL generates an output of "0" that the complementary plate signal, PLC, is "1 ". Notice conversely that when BL generates an output of "1 " that the complementary plate signal, PLC, is "0".

The actual construction of 4F² sized, capacitor over bit line (COB) differential DRAM cell pairs or sets of cells is shown in FIG. 23.

Cross-Section of Manufactured, Gigabit Class, 3D Capacitor, COB, 1 T1 C,

NONVOLATILE DRAM Cells

FIG. 22 shows a prior art cross sectional drawing of 3 dimensional, capacitor-over-bit line, (COB) one transistor 1 capacitor (1 T1 C) DRAM cells. As discussed earlier, the top plate electrode is a deposited plate layer that covers entire sections of the COB 1 T1 C DRAM memory arrays. However, this invention, unusually, manufactures apart or separates this unified array plate electrode into individual plate electrodes as seen in FIG. 22 like, PL0, to, PL1 . This is for the newly created purpose of program encoding & so storing "different" nonvolatile data bit(s) within these DRAM cells.

For example, in FIG. 22 capacitor over bit line (COB), one transistor one capacitor (1 T1 C) DRAM cells M0 and M1 each comprise a pass transistor, TO, & T1 for allowing data from bit line, BL, to be transferred to and from DRAM storage nodes, Q0, &, Q1 , for reading & writing of volatile data while, first, each DRAM capacitor serves as a direct current (DC) blocker to keep separate any & all volatile data on the DRAM capacitor "storage node electrode" side away from the nv data stored on the opposite DRAM capacitor "plate electrode" side. Second, each DRAM cell capacitor also serves as an AC bypass capacitor where DRAM cell plate electrodes, PL0, and, PL1 , are "selectively supplied by" or "programmed to" a choice of supply/plate programming lines chosen from a bus of: P0₂ to P1₂ if 1 nonvolatile data bit is to be stored, or P00₂ to P11₂ if 2 nonvolatile data bits are to be stored, or P000₂ to P111₂ if 3 nonvolatile data bits are to be stored. The selectively supplied by encoded, nv programming line programmed to can now be actively pulsed or activated so that selected nv data can be transmitted through the DRAM storage capacitors now serving as alternating current (AC) bypass capacitors to read out nv data through the pass transistors, TO & T1 , and onto bit line, BL.

To read out nonvolatile data bits or digits stored within these 3D capacitor DRAM cells, MO and M1 , follow flow chart, FIG. 8B if, for example, "Active Plate Pulsing" is employed. Then because DRAM cell, MO, is selectively supplied by supply/nv programming line, P0₂, i.e., a nonvolatile data NVD=0₂, or NVD[1 :0]=00₂, or NVD[2:0]=000₂, would be read out of MO. Then because DRAM cell, M1 , is selectively supplied to supply/nv programming line, P102, ie., a nonvolatile data NVD[1 :0]=10₂, or NVD[2:0]=010₂, would be read out of MO.

The binary inverse or complement for the nonvolatile data stored would be true if, instead, "passive plate pulsing", as described in flow chart, FIG. 25B, were employed ie. MO would store instead: NVD=1₂, or NVD[1 :0]=11₂, or NVD[2:0]=111₂, while M1 would store instead: NVD[1 :0]=01₂, or NVD[2:0]=101₂.

The programmed or selective "Couplings or selective Tnterconnects represented by CO to C7 or 10 to 17 etc. in FIG. 2 could be metal or via mask programmed, or they could be soft programmed using fuses, programmable elements like: memristors, phase change memory elements, solid electrolytes, or similar.

4F², Capacitor Over Bit line (COB) Nonvolatile DRAM Cells

FIG. 7 shows a 3 dimensional drawing of prior art [Song (2010) and Chung (2011 ) - Samsung], 3 dimensional, capacitor-over-bit line, COB 1 T1 C DRAM array with minimum area of 4F² per cell, or measuring 2 minimum features by 2 minimum features and each cell "radically using" a vertical channel array transistor" (VCAT) as a DRAM pass transistor. Please see also the prior art Japanese DRAM manufacturer, Elpida, in FIG. 33 from U.S. Patent 7,804,700 as well showing another embodiment of a 4F² vertical channel transistor DRAM memory array.

These 4F² DRAM cells both in the Samsung and Elpida, patents, have a top plate electrode that is, like the conventional industry practice including, a deposited plate layer that covers the entire top section of the DRAM array (see prior art FIG. 7). However, to integrate nonvolatile capability as described before, this invention, departs from industry practice and, unusually, breaks ie. the metal plates apart into individual plate electrodes like, PL1 to PL3 shown in FIG. 23. Selective coupling or independent programming of these "physically separate" or "individual plate electrodes", for example, can be to "plate supply/programming lines", or "potential lines" like: V0₂ to V1₂ for encoding 1 nv data bit, NVD = 1₂ , in DRAM cell, M3, or V002 to V112 for encoding 2 nv data bits, NVD[1 :0] = 112 , in DRAM cell, M2, or V000₂ to V111₂ for encoding 3 nv data bits, NVD[2:0] = 110₂, in DRAM cell, M1 , etc.

These encoded or stored binary values are based on "Active Plate Pulsing" seen in FIG. 8.

Encoded or stored binary values based on "Passive Plate Pulsing" are binary inverted values that follow the flow chart of FIG. 25.

The 3 dimensional, vertical channel access transistors (VCAT) have control gates encircling the vertical pillar shaped silicon channels allowing charge into and out of the roller pin shaped, 3D COB, storage capacitors as shown.

3D PC on 1 or 2 Chips

FIG. 24A shows a preferred multi-bit DRAM cache chip utilizing the 1 to 3 bit or more nv COB DRAM cells claimed in this patent combined with a single or multi-core processor chip. Optionally, the processor chip can employ the "1 to 6 bit or 3 to 10 bit Nonvolatile Latch Memory" patent cells. A DRAM block or cache is, therefore, tightly coupled with a processor or processor SRAM cache avoiding slow, high power consuming, through silicon vias (TSVs). This basic personal computer (PC) combined essentially with a WIFI transmit/receiver chip shown in FIG. 24B can create an internet connected postage stamp PC.

FIG. 24 C and D are a reduced version of FIG. 24 A and B.

As used herein H refers to COB or CUB capacitor height while W their greatest width and T is a multiplier to determine the scale height verses the width, W. Values of, T , can include but are not limited to: 0.5, 1 , 2, 3, 4, 5, 10, or more.

DRAM cells are being prototyped and researched using vertical channel transistors like: vertical channel access transistor (VCAT), FinFET, Tri-Gate, or the like or equivalent.

Passive Plate Pulsing Schematics and Timing Diagrams

Active plate pulsing and passive plate pulsing for reading out DRAM capacitor over bit line (COB), plate electrode, selectively supplied, nonvolatile data are illustrated in FIGS 25 to 32. The passive plate pulsing, programming table of FIG. 25A plus flow chart of FIG. 25B as well as 1 -3 bit schematics and timing diagrams in FIG. 26 to FIG. 32.

Differential, selectively supplied, NV DRAM Cells, (FIG. 34)

The actual construction of 4F² sized, capacitor over bit line (COB) differential DRAM cell pairs or sets of cells is shown in FIG. 34.

In FIG. 34 4F², COB, 1 T DRAM cell pair, M1 and M2, are selectively supplied by V bus supply/nv programming lines that are complementary to each other. The wonderful result is that the nv data read out of this cell pair are differential ie. these outputs are differential sense amplified to result in a full logic "1 " and logic "0" values.

For example, when, M 1 and M2, are differentially, selectively supplied by, V1₂, and, VO₂, of bus, V[1 :0], this differential cell pair stores a nonvolatile data, NVD = 1₂.

Also, when, M1 and M2, are differentially, selectively supplied by, VOI ₂, and, VI O₂, of bus, V[3:0], this differential cell pair stores a nonvolatile data, NVD[1 :0] = 01₂.

Finally, when, M1 and M2, are differentially, selectively supplied by, V001₂, and, V1 10₂, of bus, V[7:0], this differential cell pair stores a nonvolatile data, NVD[2:0] = 001₂, etc.

"Physically Separate" Plate Electrode Covering More Than 1 DRAM Cell, (FIG. 35)

If lower resistance, higher performance, supply/nv plate programming lines are desired, it is possible to have multiple DRAM cells like, M2 and M3, in FIG. 23 with separate storage nodes, with separate storage node capacitor electrodes for storing multiple volatile data bits; however, instead, their DRAM capacitor plate electrodes would be combined together like in FIG. 35 or shared across more limited number of cells. Although their encoded nonvolatile data would be spread across a few DRAM cells rather than just programmed for

1 cell, the advantage gained is seen in FIG. 35 by the physical wider or larger plate electrode, PL23 and supply/nv programming lines, P[1 :0], for lower resistance and hence faster RC time constant response time. In FIG. 35 although both, M2 and M3, store the same nonvolatile data, NVD[1 :0] = 10₂, they both can store different volatile charge data.

A Matrix Line of Cells, whose Tall Capacitor (TO DRAM cells Have Their Plate Electrodes Supplied by a 1 b, 2b, or More Potential Line Bus, So as to Encode said Tall Capacitor (TO DRAM cells each with 1 b, 2b, or More Nonvolatile (NV) Data

In the 1968 U.S. Patent 3,387,286 to Dennard (IBM) established a practice followed today, some 40 years later, by taking a DRAM cell with its "single capacitor", more specifically its "integrated circuit capacitor" and to drive (see Fig. 1 ) specifically the DRAM capacitor plate electrode (14) with a single "reference potential" (40) which in this case is the ground of the memory array or 0 volts (see Fig. 1 ground schematic symbol & Fig. 2 see

14D for physical ground metal line). To minimize DRAM cell area each DRAM array cell on a same memory matrix line of DRAM cells like a word line (24), or bit line (26), share 1 same potential line connected to 1 same reference potential source (40).

This reference potential source sharing by at least 1 matrix line of many DRAM cells of 1 potential conductor line driven by 1 reference potential source is what is considered an obvious common industry practice to save DRAM cell and DRAM memory array area.

The invention and its embodiments are a departure from the Dennard patent, in that not 1 but a plurality of potential lines and plurality of reference potential sources are utilized on a single matrix line of at least DRAM cells opposite to the industry trend to share and consolidate. The unexpected advantage gained is that Tall Capacitor (TC) DRAM cell plate electrodes, on a matrix line of cells, selectively supplied by either a 0^th or 1 ^st potential line encodes these tall capacitor DRAM cell plate electrodes with: B = LOG₂(P=2 potential lines) = 1 bit of DRAM capacitor, plate electrode, potential line combination, nonvolatile (nv) data.

DRAM cell plate electrodes on a matrix line of cells being selectively supplied by either a 0^th , 1 ^st , 2^nd, or 3^rd potential line encode these TC DRAM cell plate electrodes with: B = LOG₂(P=4 potential lines) = 2 bits of DRAM capacitor, plate electrode, potential line combination, nonvolatile (nv) data.

And as the # of potential lines, P, utilized per matrix line of cells increase in powers of 2, ie. 2^Λ3=8 potential lines, 2M=16 potential lines, then the # of potential line combination nv data increases as well. For example, B = LOG₂(P = # of potential lines).

The DRAM cell schematics showing each TC DRAM capacitor plate electrode being supplied by either a 0^th or 1 ^st potential line ie. V0 or V1 as shown in FIG. 36.

In FIG. 36A a 1 T1 C or 1 transistor 1 capacitor DRAM cell has its plate electrode connected to the 0th or V0 potential line rather than the 1 st or V1 potential line. So, this tall capacitor DRAM cell can not only store 1 bit of volatile data on its storage node, SN, but also has encoded a nonvolatile ie. "0" data bit connected to its plate electrode. The symbol for this FIG. 36A schematic is shown in FIG. 36B. Furthermore, this 1 b nonvolatile data can be read out by unusually first writing volatile data into this DRAM cell. Please consult the DRAM schematic and 1 b timing diagrams of FIG.10-12 to understand that this is an indirect read ie. we write data into the storage node side in order to detect through electric field reaction, rather than normal obvious direct wire transfer, what data exists on the opposite side or plate side & then read out the indirectly detected nonvolatile data bit stored.

In FIG. 36C the 1 transistor 1 capacitor DRAM cell has its plate electrode, instead, connected to the 1 ^st or V1 potential line rather than the 0^th or V0 potential line. So, this tall capacitor DRAM cell can not only store a volatile bit of data on its storage node, SN, but also has encoded a nonvolatile ie. "1 " data bit connected to its plate electrode. The symbol for this FIG. 36C schematic is in FIG. 36D. Again, this 1 b nonvolatile data can be read out by unusually first writing volatile data into this DRAM cell. See the DRAM schematic and 1 b timing diagrams of FIG.10-12.

In FIG. 36E and 36G, and 36I the 1 T1 C DRAM cells have their plate electrodes connected to 1 of 2 criss-crossing potential lines ie. V0 & V1 . In FIG. 36G, the DRAM cell has its plate electrode encoded with ie. a "0" while in FIG. 36I, the DRAM cell has its plate electrode encoded with ie. a "1 ". Again, please consult the DRAM schematic and 1 b timing diagrams of FIG.10-12.

For FIG. 37 to 41 , the matrix lines of 4, 6, and 8 DRAM cells are depicted storing 1 b potential line combination nonvolatile data bits each, where M is the # of times a 0^th potential line is connected to a tall capacitor DRAM plate electrode while N is the # of times a 1 ^st potential line is connected to a tall capacitor DRAM plate electrode. Note that these matrix line of cells can in one embodiment be consecutive DRAM cells or in other embodiments may be spaced apart. Random-like or alternating data depicted is not limited to just 1010₂, 1010102, or 101010102 but can as well be 0101₂, 010101₂, or 01010101₂. Similarly, structured-like nonvolatile data depicted is not limited to just 1 100₂, 1 1 1000₂, or 1 1 1 I OOOO₂ but can as well be 001 1₂, 0001 1 1₂, or 00001 1 1 1₂. A matrix line of at least DRAM cells include: a word line, a bit line, a positive slope where such a slope can vary as long as from cell to cell the slope stays positive, a negative slope where such a slope can vary as long as from cell to cell the slope stays negative, a subset or portion of a zig-zag line of cells if that subset of cells forms one of the previous described lines of cells like WL, BL, (+) slope, and (-) slope, and specific forms of criss-crossing potential lines as seen in FIG. 42 to FIG. 44.

For FIG. 45 to 51 these drawings depict DRAM plate electrode, potential line combination, 2b nonvolatile data cells. These matrix lines of 8, 12, and 16 DRAM cells are depicted storing 2b potential line combination nonvolatile data bits respectively, where M is the # of times a 0th potential line is connected to a tall capacitor DRAM plate electrode while N is the # of times a 1 st potential line is connected to a tall capacitor DRAM plate electrode, P is the # of times a 2nd potential line is connected to a tall capacitor DRAM plate electrode while Q is the # of times a 3rd potential line is connected to a tall capacitor DRAM plate electrode. Note that these matrix line of cells can in one embodiment be consecutive DRAM cells or in other embodiments may be spaced apart.

For FIG. 52 specific forms of 2b criss-crossing potential lines are shown. For example, bus potential lines V[1 ] and V[0] criss-cross with bus potential lines V[3:2]a, V[3:2]b, etc. to store a plurality of DRAM tall capacitor, plate electrode, potential line combination, nonvolatile data. Note that V[3:2]a, V[3:2]b, etc. plus V[1 ] & V[0], will obey the 2b nonvolatile DRAM schematic timing diagrams of FIG. 13-15.

A DRAM Cell with Plate Electrode Supplied

Through a Programmable Resistive Memory Element

In FIG. 53A a schematic of a DRAM cell with its tall capacitor plate electrode is supplied by 1 of 2 potential lines, V[0] or V[1 ], through a programmed resistive memory element. In this example embodiment, the plate electrode, PL, is manufactured with a phase change memory (PCM) element ie. manufactured in low resistance ie. crystalline form connecting it to potential line, V[0], for ie. encoding or storing a logic "0" into the DRAM cell, in addition, to the normal 1 bit DRAM cell volatile memory storage capability. In FIG. 53B and C an example embodiment of how to make this DRAM cell showing a top and side view are shown.

Constructing and Soft Program Matrix lines of Cells with 1 b, 2b, or More Potential Line Buses Supplying DRAM Cell Plate Electrodeswith Variable Resistance Memory Elements like PCM, ReRAM, etc in between

As shown in U.S. Patent 7,554,147 to Asano et al. (Fig. 16 therein) discloses phase change memory film, 39, manufactured above the DRAM COB capacitor plate electrode,

36, insulation, 35, and lower storage node electrode, 34c, layers.

Matrix lines of cells with DRAM cell tall capacitor plate electrodes supplied by 1 b, 2b, or more potential line buses are rewriteable with the insertion, for example, of variable resistance memory elements. FIG. 53 show one of the ways a bus of 2 potential lines like

V[0] and V[1 ] or else like V[1 ] and V[2] can selectively supply DRAM cell plate electrodes,

Platel , or else, Plate2, through resistive memory elements like (PCM) or phase change memory elements like GST. FIG. 53A and B show the side view and top down view of these structures for 2 adjacent DRAM cells with plate electrodes supplied by 1 b potential line buses ie. V[0] and V[1 ] for the DRAM cell on the left and 1 b potential line bus V[1 ] and V[2] for the DRAM cell on the right. The rest of the DRAM cell below the plate electrode layer is not shown and can be any of the embodiments previous shown like in FIG. 33, 34, and, 35, for 4F² DRAM cell designs, FIG. 22 or for 6F² DRAM cell designs, or other prior art, etc.

The form of the electrode or heater element, h, to supply electrical current to rapidly heat up the variable resistance material ie. GST shown here can vary and is not the subject of this application. Any of the prior art devices can be utilized in the invention method, for example

U.S. Patent 8,243,506, to Liu and U.S. Patent No. 7,915,602 to Sato. What is unexpected in the invention process is the use of what this invention refers to as a "soft programming line", SPL, whose physical slope or shape can vary like a positive slope, negative slope, and even zig-zag line, etc. These soft programming lines like SPL shown in FIG. 54 and FIG. 55 when used in on the DRAM matrices or memory arrays can transform the ie. mask programmed 1 b, 2b, or more DRAM plate electrode to potential line combination, nonvolatile data into rewriteable, nonvolatile data. The front and side view of these soft programming line structures to program these DRAM cells for rewriteable nonvolatile data are seen again in FIG. 54 and FIG. 55.

The steps to program connect these DRAM cells to the potential line buses via phase change memory elements interposed is illustrated in FIG. 56 and FIG. 57. (Step 1 ) - program connects at least a single DRAM capacitor's plate electrode, not storage node, to 1 of a plurality of potential lines like V[0] and V[1 ] for the purpose of encoding & so storing within that specific DRAM cell, "plate electrode to potential line combination, nonvolatile data". This connection is established by creating a Vcrystallize voltage such that a variable resistance memory element, like a GST phase change memory element, is transformed into a low resistance, crystalline state or connecting state. (Step 2) The programming voltages are returned to a non-reactive state less than the Vcrystallize and Vreset voltages for the phase change memory elements. (Step 3) Now that DRAM cell Platel is supplied by 1 of the 1 b nonvolatile potential lines, V[1 ] or V[0], we can disconnect the soft programming line, SPL, with the Vreset voltage applied across both it and the unprogrammed, potential lines for that DRAM cell. This renders these GST phase change memory element connections, amorphous or a high resistance disconnect state.

This soft programming line structure can also be applied to connect other device power terminals to a potential line bus for encoding & storing nonvolatile data like a SRAM's latch driver or latch load power terminal; a one transistor one resistor (1 T1 R) phase change memory (PCM) cell's power terminal, a set reset SR NAND or SR NOR flip-flop's power terminals, etc.

While the invention is described as being preferably used in nonvolatile, stacked capacitor Dynamic RAM cells, it may also be used in embedded DRAM as well.

The foregoing description of various and preferred embodiments of the present invention has been provided for purposes of illustration only, and it is understood that numerous modifications, variations and alterations may be made without departing from the scope and spirit of the invention as set forth in the following claims.

Claims

1 . Dynamic random access memory (DRAM) cell for simultaneously storing volatile and non-volatile data comprising:

at least two plate potential lines, L;

a capacitor including a storage node electrode and a plate electrode;

wherein said plate electrode has access to each of said plate potential lines L and dynamically selectively couples to one of said plate potential lines L to allow encoding and storing of nonvolatile data;

wherein said capacitor separates the nonvolatile and volatile data such that the memory cell encodes and stores both nonvolatile data and volatile data simultaneously.

2. The DRAM cell according to Claim 1 , wherein said capacitor stores said volatile data on said storage node and said nonvolatile data is stored on one of said plate potential lines L.

3. The DRAM cell according to Claim 1 , further including bit lines (BL) and word lines (WL).

4. The DRAM cell according to Claim 1 , further including a transistor which is selected from the group consisting of a quantum field effect transistor and a field effect transistor utilizing lll-IV periodic table elements.

5. The DRAM cell according to Claim 1 , wherein selectively couples comprises a programmable memory element programmed to have a high or low resistance to be a logic "1 " or "0".

6. The DRAM cell according to Claim 6, wherein said programmable memory element is selected from the group consisting of a phase change memory element (PCM), a memristor, a resistive random access memory a conductive bridge random access memory (CBRAM) and a solid electrolyte.

7. The DRAM cell according to claim 1 , wherein said capacitor is selected from the group consisting of a stacked capacitor, a tall capacitor, a capacitor over bit line (COB), a trench capacitor, and a capacitor under bit line (CUB).

8. The DRAM cell according to claim 1 , wherein selectively couples comprises a metal connection.

9. A memory circuitry comprising:

at least two plate potential lines, L,

at least one dynamic random access memory (DRAM) cell, N, for simultaneously storing volatile and single and/or multi-bit non-volatile data wherein each said cell comprises a capacitor for separating said data including a storage node electrode for storing said volatile data and a plate electrode, such that said plate electrode is selectively coupled to one of said L plate potential lines to encode and store said nonvolatile data.

10. The memory circuitry according to Claim 9, wherein each DRAM, N, cell

B = [[Log₂(L)]] + 1

wherein B = data bits or binary digits encoded and stored in each of said DRAM, N cell.

1 1. The memory circuitry according to Claim 10, wherein said DRAM, N cells are within bit lines (BL) and word lines (WL) array of memory cells.

12. The memory circuitry according to Claim 10, further comprising L=2, where said DRAM cell encodes and stores B = 2 data bits/binary digits.

13. The memory circuitry according to Claim 10, further comprising L=4, where said DRAM cell encodes and stores B = 3 data bits/binary digits.

14. The memory circuitry according to Claim 10, further comprising L=8, where said DRAM cell encodes and stores B = 4 data bits/binary digits.

15. The memory circuitry according to Claim 9, wherein up to 4 data bits/binary digits of nonvolatile data and at least 1 data bit/binary digit of volatile data is stored simultaneously on each DRAM cell.

16. The memory circuitry according to Claim 1 1 , wherein said DRAM N cells are within the same WL.

17. The memory circuitry according to Claim 1 1 , wherein said DRAM N cells are within the same BL.

18. The memory circuitry according to Claim 9, further comprising multiple DRAM N cells arranged adjacent to each other, in rows of cells or in columns of cells wherein said potential lines are shared between said adjacent cells, rows of cells or columns of cells.

19. The memory circuitry according to Claim 9, wherein each DRAM cell further includes a single transistor.

20. The memory circuitry according to Claim 19, wherein said transistor is selected from the group consisting of quantum field effect transistors and field effect transistors utilizing ll-IV periodic table elements for better transistor channels.

21. The memory circuitry according to Claim 9, wherein selectively coupling comprises a programmable memory element programmed to have a high or low resistance to be a logic "1 " or "0".

22. The memory circuitry according to Claim 21 , wherein said programmable memory element is selected from the group consisting of a phase change memory element (PCM), a memristor, a resistive random access memory a conductive bridge random access memory (CBRAM) and a solid electrolyte.

23. The memory circuitry according to Claim 9, wherein said capacitor is selected from the group consisting of a tall capacitor, stacked capacitor, capacitor over bit line (COB), a trench capacitor, and a capacitor under bit line (CUB).

24. The memory circuitry according to Claim 9, wherein selectively coupled comprises a metal connection.

25. The memory circuitry according to Claim 12, wherein said plate potential lines at least L=2 are substantially manufactured nonlinear.

26. The memory circuitry according to Claim 25, wherein said nonlinear is substantially serpentine or zigzag in construction.

27. The memory circuitry according to Claim 9, wherein each DRAM cell further includes multiple transistors only for multi-port DRAM operation.

28. A method to simultaneously encode and store volatile and nonvolatile data bits within a dynamic random access memory (DRAM) cell comprising the steps of:

providing a DRAM cell comprised of a capacitor including a storage node electrode and a plate electrode; and at least two plate potential lines L;

creating an electric field on the inside of said capacitor by running power in reverse through the DRAM cell;

selectively coupling said plate electrode to one of said plate potential lines L, wherein said electric field permits said encoding and storing of said non-volatile data;

running power forward through the DRAM cell so that the outside of the capacitor is electrified and can store volatile data.