WO2015176621A1

WO2015176621A1 - Interface detection circuit, apparatus and method

Info

Publication number: WO2015176621A1
Application number: PCT/CN2015/078879
Authority: WO
Inventors: 安云霖; 李军; 程乔乔; 徐旭伟
Original assignee: 华为技术有限公司
Priority date: 2014-05-19
Filing date: 2015-05-13
Publication date: 2015-11-26
Also published as: CN105092998A

Abstract

An interface detection circuit, apparatus and method, which relate to the field of electronic devices and can realize a universal interface state detection solution, thereby improving the practicability of the interface detection of electronic devices. The method comprises: opening, by a decision module (001), a detection module (002); detecting and acquiring, by the detection module (002), a load signal corresponding to a load impedance; and then, determining, by the decision module (001), an interface state of a device interface according to the load signal.

Description

Interface detection circuit, device and method

The present application claims priority to Chinese Patent Application No. 201410210915.5, entitled "An Interface Detection Circuit, Apparatus and Method", filed on May 19, 2014, the entire contents of which is incorporated herein by reference. In the application.

Technical field

Embodiments of the present invention relate to the field of computers, and in particular, to an interface detection circuit, apparatus, and method.

Background technique

Nowadays, electronic devices are showing a diversified development trend, and different types of devices (such as smart phones, tablets, smart TVs, etc.) have gradually increased the application requirements for general-purpose interfaces in system design; A common interface, on the one hand, provides versatility and compatibility of the device products, and on the other hand provides users with common interfaces, which are convenient and easy to use, thereby improving the user experience. Among them, common common interfaces include: Universal Serial Bus (USB) interface, 3.5mm headphone jack, High Definition Multimedia Interface (HDMI) interface, network port RJ45 and RJ9 headphone jack.

With the increase of users' requirements for various smart devices, the insertion state recognition design of the universal interface has become a common design requirement; at present, different detection schemes are adopted for different types of interfaces, such as by judging the closing and breaking of the elastic shrapnel. The status of the interface is determined by detecting and detecting the level change of a pin on the interface and detecting the change in power consumption after the device is inserted. Therefore, the interface detection method provided by the prior art has poor versatility, and the partially targeted solution can only be applied to a specific type of interface, and has low practicability.

Summary of the invention

The embodiment of the invention provides an interface detection circuit, device and method, which can implement a universal interface state detection scheme, and is portable and practical based on a universal module structure. Higher sex.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In a first aspect, an interface detection circuit is provided, where the interface detection circuit includes: a decision module and a detection module, where:

The decision module is connected to the detection module, and configured to send an open signal to the detection module, where the open signal is used to open the detection module;

The detecting module is configured to connect a device interface, detect a load impedance on the device interface, and generate a load signal corresponding to the load impedance;

The determining module is further configured to: when the load signal meets a preset state condition, determine that an interface state of the device interface is an inserted state, or when the load signal does not satisfy the preset state condition, It is determined that the interface state is an unplugged state.

In conjunction with the first aspect, in a first possible implementation, the decision module is further configured to:

After determining that the interface state is the inserted state, sending a shutdown signal to the detection module, the shutdown signal being used to close the detection module.

In conjunction with the first possible implementation of the first aspect, in a second possible implementation, the decision module is further configured to:

After the closing signal is sent to the detecting module, the opening signal is sent to the detecting module at intervals of a first preset time, and the load signal is acquired again from the detecting module, and is determined according to the load signal. The interface status.

In combination with the first aspect, in a third possible implementation, the decision module is further configured to:

After determining that the interface state is the uninserted state, the second predetermined time interval is sent, the opening signal is sent to the detecting module, and the load signal is acquired again from the detecting module, according to the load signal. Determine the interface status.

With reference to the third aspect, the third possible implementation manner of the first aspect, in a fourth possible implementation, the determining module includes a central processing unit CPU;

The detecting module includes: a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor, the first transistor and the first The two transistors are bipolar transistors, and the third transistor is a field effect transistor;

The first interface of the CPU is connected to the first end of the first resistor and the first end of the second resistor, and the second interface is connected to the drain of the third transistor;

a base of the first transistor is connected to a second end of the first resistor, a collector is connected to a gate of the third transistor, a first end of the third resistor, and an emitter is connected to the device Connected to the first end;

The base of the second transistor is connected to the second end of the second resistor, the collector is connected to the second end of the device interface, and the emitter is connected to the first voltage end;

The second end of the third resistor is connected to the second voltage end;

a source of the third transistor is connected to the first voltage end, and a drain is further connected to a first end of the fourth resistor;

The second end of the fourth resistor is connected to the second voltage end;

The first voltage terminal is at a low level, and the second voltage terminal is at a high level;

The CPU in the decision module sends the open signal to the detecting module, and the open signal includes a signal for setting a first terminal voltage of the first resistor to a high level, so that the first resistor The second terminal voltage and the second terminal voltage of the second resistor are both high, and the first transistor is electrically connected to the second transistor;

The detecting module acquires a corresponding load signal according to a connection situation between the first end and the second end of the device interface, where the load signal is a drain voltage of the third transistor; when the device interface is first When the terminal and the second terminal are already connected, the collector voltage of the first transistor is a low level, the third transistor is turned on, and the drain voltage of the third transistor is a low level; or When the first end and the second end of the device interface are not connected, the collector voltage of the first transistor is a low level, the third transistor is turned off, and the drain voltage of the third transistor is a high level ;

The CPU in the decision module determines that the interface state is an inserted state when the drain voltage of the third transistor is a low level, or when the drain voltage of the third transistor is a high level And determining that the interface state is an uninserted state.

In a second aspect, an interface detecting apparatus is provided, the interface detecting apparatus comprising a device interface, the first aspect to any one of the fourth possible implementation manners of the first aspect Port detection circuit.

In a third aspect, an interface detection method is provided, and the method includes:

Initialization phase: the decision module sends an open signal to the detection module, the open signal is used to open the detection module;

a detection phase: the detection module detects a load impedance on a device interface, and generates a load signal corresponding to the load impedance;

a decision stage: when the load signal meets a preset state condition, the decision module determines that an interface state of the device interface is an inserted state, or when the load signal does not satisfy the preset state condition, The decision module determines that the interface state is an uninserted state.

With reference to the third aspect, in a first possible implementation, after the determining, by the determining module, that the interface state of the device interface is an inserted state, the method further includes:

The decision module sends a shutdown signal to the detection module, the shutdown signal is used to close the detection module and stop detecting.

With the first possible implementation of the third aspect, in a second possible implementation, after the determining module sends a shutdown signal to the detection module, the method further includes:

After the first predetermined time interval, the initialization phase is re-executed to the decision phase.

With reference to the third aspect, in a third possible implementation, after the determining, by the determining module, that the interface state is an uninserted state, the method further includes:

After the second predetermined time interval, the initialization phase is re-executed to the decision phase.

The interface detection circuit, device and method provided by the embodiment of the invention, based on the coordination between the decision module and the detection module, determine the interface state by determining the load impedance of the device interface; for different types of device interfaces, On the basis of not changing the circuit design structure, the universal interface state detection scheme can be realized only by partial adjustment, which has strong portability and improves the practicability of the interface detection circuit.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a schematic structural diagram 1 of an interface detection circuit according to an embodiment of the present invention;

2 is a schematic structural diagram 2 of an interface detection circuit according to an embodiment of the present invention;

3 is a schematic structural diagram of a circuit of an interface detection circuit according to an embodiment of the present invention;

FIG. 4 is a schematic flowchart 1 of an interface detection method according to an embodiment of the present disclosure;

FIG. 5 is a schematic flowchart 2 of an interface detection method according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

An embodiment of the present invention provides an interface detection circuit 00. As shown in FIG. 1, the interface detection circuit 00 includes:

Decision module 001, detection module 002.

Specifically, the decision module 001 is connected to the detection module 002 and configured to send an open signal to the detection module 002.

The open signal is used to open the detection module 002.

The detecting module 002 is configured to connect to the device interface 003, detect the load impedance on the device interface 003, and generate a load signal corresponding to the load impedance.

The device interface 003 may be a connection interface of the device itself for connecting various external devices. For example, taking the phone RJ9 earphone interface as an example, when detecting the insertion of the RJ9 earphone, the load on the device interface 003 is For the headset receiver.

As shown in FIG. 2, the structure of the interface detection circuit 00 and the device interface 003 is connected. intention.

The decision module 001 is further configured to determine that the interface state of the device interface 003 is the inserted state when the load signal meets the preset state condition, or determine that the interface state is the unplugged state when the load signal does not satisfy the preset state condition.

The preset state condition may be a default setting of the system, or may be given by an external input. The specific setting is different according to the circuit structure, and is not limited herein.

In an implementation manner, the decision module 001 is further configured to send a shutdown signal to the detection module 002 after determining that the interface state of the device interface 003 is the inserted state.

The shutdown signal is used to turn off the detection module 002.

Optionally, the determining module 001 is further configured to: after sending the shutdown signal to the detecting module 002, send an open signal to the detecting module 002 at intervals of a first preset time, and obtain a load signal from the detecting module 002 again, and determine the device according to the load signal. Interface status of interface 003.

The first preset time is determined by the decision module 001 after the interface state of the device interface 003 is the inserted state, and the interval time of the interface state detection may be the default value of the system or the external input reference value. , here is not limited.

In another implementation manner, the determining module 001 is further configured to: after determining that the interface state of the device interface 003 is an uninserted state, send an open signal to the detecting module 002 at intervals of a second preset time, and obtain again from the detecting module 002. The load signal determines the interface state of the device interface 003 according to the load signal.

The first preset time is determined by the decision module 001, and the interval time of the interface state detection after the interface state of the device interface 003 is not inserted, which may be a system default setting value or an external input setting value. , here is not limited.

The interface detection circuit provided by the embodiment of the invention opens the detection module by the decision module, and the detection module detects the load signal corresponding to the load impedance, and the decision module determines the interface state of the device interface according to the load signal; thus, for different types The device interface can realize the universal interface state detection scheme only by partial adjustment without changing the circuit design structure, has strong portability, and improves the practicability of the interface detection circuit.

Specifically, as shown in FIG. 3, in the interface detection circuit 00 provided by the embodiment of the present invention, The decision module 001 can include a central processing unit CPU.

Among them, the CPU connects and interacts with other modules through a General Purpose Input Output (GPIO) interface.

It should be noted that the decision module 001 may provide a part of the corresponding function in the CPU of the device where the interface detection circuit 00 is located, or may also be an accessory module under the control of the CPU; in the process of actual application, according to design requirements Make selections and adjustments.

Further, as shown in FIG. 3, the detecting module 002 may include:

a first transistor Q1, a second transistor Q2, a third transistor Q3, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; wherein the first transistor Q1 and the second transistor Q2 can be bipolar Type transistor, the third transistor Q3 can be a field effect transistor;

It is to be noted that, in the embodiment of the present invention, the first transistor Q1 and the second transistor Q2 are all described by using a bipolar transistor, that is, a semiconductor transistor, and the third transistor Q3 is a P-channel enhancement type. The field effect transistor is taken as an example. It is conceivable that when other devices with the same characteristics are used, such as the third transistor Q3 adopting an N-channel enhancement type field effect transistor, those skilled in the art can do no creative work. It is easily conceivable under the premise and is therefore also within the scope of the embodiments of the present invention.

Exemplarily, as shown in FIG. 3, the CPU is connected to the first end of the first resistor R1, the first end of the second resistor R2 through the first interface on the GPIO, and the second interface is connected to the drain of the third transistor Q3. ;

The base of the first transistor Q1 is connected to the second end of the first resistor R1, the collector is connected to the gate of the third transistor Q3, the first end of the third resistor R3, and the emitter is connected to the first end of the device interface 003. ;

The base of the second transistor Q2 is connected to the second end of the second resistor R2, the collector is connected to the second end of the device interface 003, and the emitter is connected to the first voltage terminal V1;

The second end of the third resistor R3 is connected to the second voltage terminal V2;

The source of the third transistor Q3 is connected to the first voltage terminal V1, and the drain is also connected to the first terminal of the fourth resistor R4;

The second end of the fourth resistor R4 is connected to the second voltage terminal V2;

The first voltage terminal V1 may be an input low level GND, and the second voltage terminal V2 may be an input high level VCC.

Exemplarily, based on the interface detection circuit 00 shown in FIG. 3, in an implementation manner, the CPU in the decision module 001 sends an open signal to the detection module 002, the open signal including the first end of the first resistor R1 The voltage is set to a high level signal, so that the voltage of the second terminal of the first resistor R1 and the voltage of the second terminal of the second resistor R2 are both high, and the first transistor Q1 and the second transistor Q2 are turned on;

The detecting module 002 obtains a corresponding load signal according to the connection between the first end and the second end of the device interface 003, and the load signal is the drain voltage of the third transistor Q3; when the first end and the second end of the device interface 003 already exist When connected, the collector voltage of the first transistor Q1 is at a low level, the third transistor Q3 is turned on, and the drain voltage of the third transistor Q3 is at a low level; or, when the first end and the second end of the device interface 003 are When not connected, the collector voltage of the first transistor Q1 is at a low level, the third transistor Q3 is turned off, and the drain voltage of the third transistor Q3 is at a high level;

When the drain voltage of the third transistor Q3 is low, the CPU in the decision module 001 determines that the interface state is the inserted state, or when the drain voltage of the third transistor is high, determines that the interface state is uninserted. .

Optionally, after determining that the interface state of the device interface 003 is the inserted state, the CPU in the decision module 001 sends a shutdown signal to the detection module 002, where the shutdown signal includes setting the first terminal voltage of the first resistor R1 to be low. The flat signal is such that the voltage of the second terminal of the first resistor R1 and the voltage of the second terminal of the second resistor R2 are both low, the first transistor Q1 and the second transistor Q2 are turned off, and the detecting module 002 stops detecting; thus, avoiding The interface detection circuit 00 causes interference to the original circuit of the device.

Further, the CPU in the decision module 001 may further send an open signal to the detecting module 002 after the first signal is sent to the detecting module 002, and obtain a load signal from the detecting module 002 again, and determine the load signal according to the load signal. The interface status of the device interface 003 determines whether the device inserted on the device interface 003 is unplugged during the first preset time interval.

Optionally, after determining that the interface state of the device interface 003 is an uninserted state, the CPU in the decision module 001 sends an open signal to the detecting module 002 at a second preset time interval. The load signal is obtained from the detection module 002 again, and the interface state of the device interface 003 is determined according to the load signal, so that when the interface state of the device interface 003 is detected as being uninserted, the interface state is periodically detected.

According to the interface detection circuit provided by the embodiment of the present invention, based on the coordination between the decision module and the detection module, the interface state is detected by determining the load impedance of the device interface, and the interface state is further determined to be inserted. The detection is stopped after the state; for different types of device interfaces, the general interface state detection scheme can be realized only by partial adjustment without changing the circuit design structure, which has strong portability and avoids introduction of the original circuit of the device. Additional interference improves the usability of the interface detection circuit.

The embodiment of the invention further provides an interface detecting device, which is applied to any type of electronic device having a device interface, such as a smart phone, a tablet computer or a smart TV; the interface detecting device includes the interface detection as described above Circuit.

Specifically, the interface detecting apparatus provided by the embodiment of the present invention may be an electronic device including a device interface and an interface detecting circuit.

The interface detecting apparatus provided by the embodiment of the invention includes an interface detecting circuit, based on the coordination between the decision module and the detecting module in the interface detecting circuit, and determining the interface state by determining the load impedance of the device interface; for different types of devices The interface can realize the universal interface state detection scheme only by partial adjustment without changing the circuit design structure, has strong portability, and improves the practicability of the interface detection circuit.

The embodiment of the present invention provides an interface detection method, which can be applied to the interface detection circuit provided in the foregoing embodiment. As shown in FIG. 4, the method includes:

S101. The decision module sends an open signal to the detection module.

The open signal is used to open the detection module.

S102. The detection module detects a load impedance on the interface of the device, and generates a load signal corresponding to the load impedance.

S103. When the load signal meets the preset state condition, the decision module determines that the interface state of the device interface is the inserted state, or when the load signal does not satisfy the preset state condition, the decision module determines that the interface state is the uninserted state.

In an implementation manner, the decision module determines that the interface state of the device interface is inserted. After the state is entered, the method further includes: the decision module sends a shutdown signal to the detection module, and the shutdown signal is used to close the detection module and stop the detection.

Optionally, after the decision module sends the shutdown signal to the detection module, the first preset time is interrupted, and the foregoing S101 to S103 are performed again, and the interface state detection is performed again.

In another implementation manner, after the determining module determines that the interface state is the uninserted state, the method further includes: after the second preset time interval, re-executing the foregoing S101 to S103, and performing the interface state detection again.

An interface detection method is provided by the embodiment of the present invention. The detection module is opened by the decision module, and the detection module detects the load signal corresponding to the load impedance, and the decision module determines the interface state of the device interface according to the load signal; thus, for different types The device interface can realize the universal interface state detection scheme only by partial adjustment without changing the circuit design structure, has strong portability, and improves the practicability of the interface detection circuit.

The interface detection circuit shown in FIG. 3 is taken as an example to describe the interface detection method provided by the embodiment of the present invention in detail.

In the interface detection circuit shown in FIG. 3, the first transistor Q1 and the second transistor Q2 may be bipolar transistors, and the third transistor may be a field effect transistor, and each transistor mentioned in the embodiment of the present invention may be Use other devices with the same characteristics to replace them. In the use, only the circuit needs to be adjusted accordingly. The specific selection can be determined according to the design requirements, which is not limited here.

Specifically, as shown in FIG. 5, the interface detection method provided by the embodiment of the present invention may include:

S201. Initialization phase: At this stage, the CPU sets the first terminal (point A) voltage of the first resistor R1 to a high level through the GPIO interface. At this time, the voltage of the second end (point B) of the first resistor R1 and the voltage of the second end (point C) of the second resistor are both high; since point B is the base of the first transistor Q1, point C is The base of the second transistor Q2, and points B and C are both high, and the first transistor Q1 and the second transistor Q2 are turned on.

Among them, the high level can be the VCC set by the system.

S202. Detection phase: At this stage, the first transistor Q1 and the second transistor Q2 are turned on to obtain the collector (point D) voltage of the first transistor Q1.

Wherein, according to whether the device interface is connected to the load, the collector voltage of the first transistor Q1 has two situations: a high level and a low level:

Exemplarily, when the device interface is not connected to the load, the connection between the two ends of the device interface is not established, that is, the connection between the emitter of the first transistor Q1 and the collector of the second transistor Q2 is disconnected. Always stay high;

Alternatively, when the device interface is connected to the load, the two ends of the device interface form a connection relationship, that is, there is a connection between the emitter of the first transistor Q1 and the collector of the second transistor Q2, and the voltage at the point D is maintained high before. The level changes to a low level;

Among them, the low level can be the GND set by the system.

It is worth mentioning that, assuming that the resistance of the device interface access load is RL, in the case where the first transistor Q1 and the second transistor Q2 are turned on, the voltage _{D D} at the D point is:

Wherein, according to the resistance value of the third resistor R3, the voltage _{D D} of the D point can be adjusted, and U _D is low level by adjusting, that is, U _{D is} less than a preset voltage value, and the preset voltage value can be The turn-on voltage of the third transistor Q3 itself is determined; the configuration of the third resistor R3 can be determined according to the application requirements of the interface detection circuit, that is, the resistance range of the corresponding interface insertion device type.

It can be seen that for different types of device interfaces, it is only necessary to adjust the resistance value of the third resistor R3 at the time of design, and the migration can be performed while maintaining the circuit structure unchanged, which has high practicability and is reduced. Industrial costs.

Further, the drain (E point) voltage of the third transistor Q3 is obtained; wherein, according to whether the device interface is connected to the load, the drain voltage of the third transistor Q3 has a high level and a low level:

Exemplarily, when the voltage at point D is high, the third transistor Q3 is turned off, and the voltage at point E is high; or, when the voltage at point D is low, the third transistor Q3 is turned on, and the voltage at point E is from before. The high level goes low.

S203, a decision stage: in this stage, the CPU obtains the voltage of the E point, determines whether the voltage of the E point meets the preset state condition, and if yes, determines that the interface state of the device interface is the inserted state; or, if not, determines The interface status is unplugged.

The preset state condition includes: the E point voltage is a low level.

Optionally, in the foregoing determining phase, when the CPU determines that the E-point voltage meets the preset state condition, that is, determines that the interface state of the device interface is the inserted state, the method further includes:

S204, feedback phase: In this phase, the CPU resets the voltage of point A to a low level through the GPIO interface.

At this time, the voltage at point B and the voltage at point C are both low; the first transistor Q1 and the second transistor Q2 are turned off, the detection is stopped, and the interface detection circuit 00 is prevented from causing interference to the original circuit of the device.

Further, after the CPU sets the voltage of the A point to a low level and stops the detection, the S201 to S203 may be performed again after the first preset time interval, and the interface state is re-detected; Whether the device inserted on the device interface is removed during the set time.

The first preset time is an interval time for performing the interface state detection again when the detection and confirmation interface state is the inserted state, and may be a system default setting value or an external input setting value. No restrictions are imposed.

Optionally, in the foregoing determining stage, when the CPU determines that the E point voltage does not satisfy the preset state condition, that is, determines that the interface state of the device interface is the uninserted state, the S201 may be performed again after the second preset time interval Go to S203 to re-detect the interface status.

The second preset time is an interval between when the interface is detected to be uninserted, and the interface is detected again, which may be a system default setting or an external input setting. No restrictions are imposed.

It is worth mentioning that, in an optional implementation manner, the interface detecting circuit may not include the third transistor Q3 and the fourth resistor R4, and the D point is directly connected to the second interface of the CPU, and the CPU determines according to the voltage of the D point. The interface status of the device interface is similar to the above steps, and is not described here. In the interface detection circuit shown in Figure 3, the third transistor Q3 is used to implement security isolation between the CPU and the interface load. It has better safety and stability when not in use.

It should be noted that the interface detection circuit shown in FIG. 3 is taken as an example to describe the interface detection method provided by the embodiment of the present invention. The interface detection method provided by the embodiment of the present invention can also be applied to an interface detection circuit having the same module structure, and each The module circuit structure can be different from that of FIG. 3, and the specific process will not be described one by one.

It can be seen that the interface detection method provided by the embodiment of the present invention, based on the coordination between the decision module and the detection module, determines the interface state by determining the load impedance of the device interface, and further determines the interface state as After the state is inserted, the detection is stopped. For different types of device interfaces, the general interface state detection scheme can be implemented only by partial adjustment without changing the circuit design structure, which has strong portability and avoids the original device. The circuit introduces additional interference and improves the usability of the interface detection circuit.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to the program instructions. The foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

The above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the appended claims.

Claims

An interface detection circuit is characterized in that: the interface detection circuit comprises: a decision module and a detection module, wherein:

The decision module is connected to the detection module, and configured to send an open signal to the detection module, where the open signal is used to open the detection module;

The detecting module is configured to connect a device interface, detect a load impedance on the device interface, and generate a load signal corresponding to the load impedance;

The determining module is further configured to: when the load signal meets a preset state condition, determine that an interface state of the device interface is an inserted state, or when the load signal does not satisfy the preset state condition, It is determined that the interface state is an unplugged state.
The interface detection circuit according to claim 1, wherein the decision module is further configured to:

After determining that the interface state is the inserted state, sending a shutdown signal to the detection module, the shutdown signal being used to close the detection module.
The interface detection circuit according to claim 2, wherein the decision module is further configured to:

After the closing signal is sent to the detecting module, the opening signal is sent to the detecting module at intervals of a first preset time, and the load signal is acquired again from the detecting module, and is determined according to the load signal. The interface status.
The interface detection circuit according to claim 1, wherein the decision module is further configured to:

After determining that the interface state is the uninserted state, the second predetermined time interval is sent, the opening signal is sent to the detecting module, and the load signal is acquired again from the detecting module, according to the load signal. Determine the interface status.
The interface detecting circuit according to any one of claims 1 to 4, characterized in that

The decision module includes a central processing unit CPU;

The detecting module includes: a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein the first transistor and the second transistor are bipolar transistors The third transistor is a field effect transistor;

a first interface of the CPU and a first end of the first resistor and a first resistor Connected to the terminal, the second interface is connected to the drain of the third transistor;

a base of the first transistor is connected to a second end of the first resistor, a collector is connected to a gate of the third transistor, a first end of the third resistor, and an emitter is connected to the device Connected to the first end;

The base of the second transistor is connected to the second end of the second resistor, the collector is connected to the second end of the device interface, and the emitter is connected to the first voltage end;

The second end of the third resistor is connected to the second voltage end;

a source of the third transistor is connected to the first voltage end, and a drain is further connected to a first end of the fourth resistor;

The second end of the fourth resistor is connected to the second voltage end;

The first voltage terminal is at a low level, and the second voltage terminal is at a high level;

The CPU in the decision module sends the open signal to the detecting module, and the open signal includes a signal for setting a first terminal voltage of the first resistor to a high level, so that the first resistor The second terminal voltage and the second terminal voltage of the second resistor are both high, and the first transistor is electrically connected to the second transistor;

The detecting module acquires a corresponding load signal according to a connection situation between the first end and the second end of the device interface, where the load signal is a drain voltage of the third transistor; when the device interface is first When the terminal and the second terminal are already connected, the collector voltage of the first transistor is a low level, the third transistor is turned on, and the drain voltage of the third transistor is a low level; or When the first end and the second end of the device interface are not connected, the collector voltage of the first transistor is a low level, the third transistor is turned off, and the drain voltage of the third transistor is a high level ;

The CPU in the decision module determines that the interface state is an inserted state when the drain voltage of the third transistor is a low level, or when the drain voltage of the third transistor is a high level And determining that the interface state is an uninserted state.
An interface detecting device, characterized in that the interface detecting device comprises a device interface, and the interface detecting circuit according to any one of claims 1 to 5.
An interface detection method, the method comprising:

Initialization phase: the decision module sends an open signal to the detection module, the open signal is used to open the detection module;

Detection phase: the detection module detects the load impedance on the interface of the device, and generates and a load signal corresponding to the load impedance;

a decision stage: when the load signal meets a preset state condition, the decision module determines that an interface state of the device interface is an inserted state, or when the load signal does not satisfy the preset state condition, The decision module determines that the interface state is an uninserted state.
The method according to claim 7, wherein after the determining module determines that the interface state of the device interface is the inserted state, the method further includes:

The decision module sends a shutdown signal to the detection module, the shutdown signal is used to close the detection module and stop detecting.
The method according to claim 8, wherein after the decision module sends a shutdown signal to the detection module, the method further includes:

After the first predetermined time interval, the initialization phase is re-executed to the decision phase.
The method according to claim 7, wherein after the determining module determines that the interface state is an uninserted state, the method further includes:

After the second predetermined time interval, the initialization phase is re-executed to the decision phase.