WO2016039694A1

WO2016039694A1 - Memory cell and method of forming the same

Info

Publication number: WO2016039694A1
Application number: PCT/SG2015/050312
Authority: WO
Inventors: Yu Jiang; Jinquan Huang; Rong Zhao
Original assignee: Agency For Science, Technology And Research
Priority date: 2014-09-12
Filing date: 2015-09-10
Publication date: 2016-03-17

Abstract

Various embodiments provide a memory cell including a memory layer having a first surface and a second surface opposite to the first surface. The memory layer includes a material configured to provide variable resistances. The memory cell further includes a first electrode disposed on the first surface of the memory layer; and a second electrode disposed on the second surface of the memory layer. The first electrode includes a silicon pillar with a tapered tip, and the tapered tip is in contact with the first surface of the memory layer.

Description

MEMORY CELL AND METHOD OF FORMING THE SAME

Cross-reference to Related Applications

[0001] The present application claims the benefit of the Singapore patent application 10201405705U filed on 12 September 2014, the entire contents of which are incorporated herein by reference for all purposes.

Technical Field

[0002] Embodiments relate generally to a memory cell and a method of forming a memory cell.

Background

[0003] Phase change random access memory (PCRAM) and resistive random access memory (RRAM) are promising candidates for next-generation non-volatile memory (NVM). PCRAM and RRAM rely on a metal-insulator-metal sandwich structure in which the insulator respectively refer to phase-change material and resistive-change material, both capable of providing variable resistances.

[0004] For PCRAM, the resistance change of the phase- change material is a result of transformation between the amorphous and crystalline phases caused by electric current generated joule heating. The required amount of thermal energy, which defines the operating currents and the switching speed, is determined by the volume of the phase- change material undergoing amorphous- crystalline transformation during the switching process.

[0005] For RRAM, the common consensus behind the resistance change is the formation or rupture of a conductive filament path between the two metal electrodes. Uniformity of the RRAM devices is dependent on the control over the filament foiTaation (i.e. filament size, location).

Summary

[0006] Various embodiments provide a memory cell including a memory layer having a first surface and a second surface opposite to the first surface. The memory layer includes a material configured to provide variable resistances. The memory cell further includes a first electrode disposed on the first surface of the memory layer; and a second electrode disposed on the second surface of the memory layer. The first electrode includes a silicon pillar with a tapered tip, and the tapered tip is in contact with the first surface of the memory layer.

[0007] Various embodiments provide a method of forming a memory cell. The method includes forming a silicon pillar from a silicon wafer; forming a tapered tip from the silicon pillar, the silicon pillar with the tapered tip forming a first electrode; forming a memory layer comprising a material configured to provide variable resistances, wherein the memory layer has a first surface in contact with the tapered tip and a second surface opposite to the first surface; and forming a second electrode on the second surface of the memory layer. Brief Description of the Drawings

[0008] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments are described with reference to the following drawings, in which:

Fig. 1 shows a cross-sectional view of a memory cell according to various embodiments.

Fig. 2 shows a flowchart illustrating a method of forming a memory cell, e.g. a memory cell of Fig. 1 above, according to various embodiments.

Fig. 3 shows a structure after patterning and development of a resist pattern for silicon pillar formation according to various embodiments.

Fig. 4 shows a structure after patterning and development of resist patterns for silicon pillar formation according to various embodiments.

Fig. 5 shows a structure after an etching process to form the silicon pillar according to various embodiments.

Fig. 6(a) shows a structure after a photoresist stripping and cleaning process according to various embodiments; Fig. 6(b) shows a scanning electron microscope (SEM) image of the silicon pillar as formed according to various embodiments.

Fig. 7 shows a structure after a dielectric deposition and chemical mechanical polishing (CMP) process according to various embodiments. Fig. 8 shows a structure after an etching process to expose a portion of the silicon pillar according to various embodiments.

Fig. 9(a) shows a structure after an anisotropic silicon wet etching process to form the tapered tip from the silicon pillar according to various embodiments; Fig. 9(b) shows an SEM image showing the silicon pillar with the tapered tip according to various embodiments.

Fig. 10 shows a structure after a dielectric deposition and CMP process according to various embodiments.

Fig. 1 1 shows a memory cell formed according to a process of various embodiments.

Fig. 12 shows a memory cell after a backend process and metal line formation according to various embodiments.

Fig. 13 shows a cross-sectional view of a memory device of a 1D1 (one-diode one-resistor) structure according to various embodiments.

Fig. 14 shows a cross-sectional view of a memoiy device of a 1D1R (one-diode one-resistor) structure according to various embodiments.

Fig. 15 shows a cross-sectional view of a memory device of a 1T1R (one- transistor one-resistor) structure according to various embodiments.

Fig. 16(a) shows a memory cell with a conventional nanowire electrode; Fig. 16(b) shows a memory cell using a silicon nanowire with a tapered tip as the bottom electrode according to various embodiments; Fig. 16(c) shows the simulated electric potential for the conventional nanowire electrode of Fig. 16(a); Fig. 16(d) shows the simulated electric potential for the tapered tip electrode of Fig. 16(b).

Fig. 17 shows a silicon pillar with a tapered tip according to various embodiments.

Fig. 18 shows a process of forming a structure of Fig. 17 according to various embodiments.

Fig. 19 shows a silicon pillar with a tapered tip having two tapered portions according to various embodiments.

Fig. 20 shows a process of forming a structure of Fig. 19 according to various embodiments.

Fig. 21 illustrates the investigation result of the tolerance for the CMP process and the impact of CMP process uniformity on the resulting tip width or diameter.

Fig. 22 shows a graph illustrating the exposed tip CD variation dependence with the tip angle.

Description

[0009] Various embodiments provide a contact minimized structure for a memory cell, e.g. a non-volatile memory (NVM) cell, by utilizing a tapered tip formed from a vertical nanowire structure as an electrode, such that the electrode has a minimal contact area with the memory material. The fabrication process may start with the formation of a free-standing silicon (Si) pillar which can be achieved through a top-down approach employing an etching process, e.g. reactive ion etching. The Si pillar is then anisotropically wet etched to give the self-limiting formation of an atomically sharp Si tip. When used as an electrode for a memory cell, this tip provides an extremely small electrical contact area, which is beneficial for NVM applications, such as phase change random access memory (PCRAM) and resistive random access memory (RRAM) applications. The tip structure also allows ease in both 1D1R (one-diode one-resistor) and 1T1R (one-transistor one-resistor) array-level integrations.

[0010] Fig. 1 shows a cross-sectional view of a memory cell 10 according to various embodiments.

[0011] The memory cell 10 may include a memory layer 3 having a first surface and a second surface opposite to the first surface, wherein the memory layer 3 may include a material configured to provide variable resistances. The memory cell 10 further includes a first electrode 1 disposed on the first surface of the memory layer 3, and a second electrode 4 disposed on the second surface of the memory layer 3. The first electrode 1 includes a silicon pillar 11 with a tapered tip 12, and the tapered tip 12 is in contact with the first surface of the memory layer 3.

[0012] In other words, various embodiments provides a memory cell having a tapered tip as an electrode in contact with a memory layer of the memory cell, wherein the tapered tip may be formed on a silicon pillar which is a vertical structure disposed at least substantially perpendicular to the memory layer. According to various embodiments, a contact minimized structure for a memory cell is provided, such that the electrode has a minimal contact area with the memory layer. [0013] In various embodiments, the tapered tip 12 may refer to a tip tapered from a body of the silicon pillar towards an end portion of the tip. In various embodiments, the tapered tip 12 may be in a shape selected from cone, truncated cone, pyramid, or truncated pyramid. In various embodiments, the tapered tip 12 may include an end portion in contact with the first surface of the memory layer 3, wherein the end portion is in a shape selected from cone, truncated cone, pyramid, truncated pyramid, cylinder, or cuboid. In various embodiments, the tapered tip 12 may further include one or more tapered portion arranged between the end portion of the tapered tip and a body of the silicon pillar 11, as illustrated in Figs. 17 and 1 below, for example.

[0014] In various embodiments, the silicon pillar 11 is a silicon nanowire having a diameter on the order of nanometers, also referred to as a nanoscale silicon pillar. Nanoscale may refer to a range from lOOnm down to the size of atoms on the order of O.lnm. In various embodiments, the silicon pillar 11 may have a diameter or a width in a range from about lOOnm down to 20nm .

[0015] In various embodiments, the tapered tip 12 may have a diameter or a width in a range from about 50nm down to an atomic size level (such as 0.1 nm or 1 Angstrom). The tapered tip 12 may be a nanoscale tip or an atomic scale tip. The nanoscale tip may have an end portion with a diameter between lnm and 50nm, for example. Atomic scale may refer to a size or dimension on the order of 0.1 nm or 1 Angstrom. The atomic scale tip may have an end portion with a diameter of less than lnm, for example, between lnm and O.lnm.

[0016] In various embodiments, a diameter of an end portion of the tapered tip 12 is substantially smaller than the diameter of the silicon pillar 1 1. By way of example, the size (e.g. diameter or width) of the silicon pillar 1 1 may be about 90nm, and the size (e.g. diameter or width) of the end portion of the tapered tip 12 may be about 20nm. In another example, the size of the silicon pillar 1 1 may be about 90nm, and the size of the end portion of the tapered tip 12 may be about 30mn or about 40nm. In a further example, the size of the silicon pillar 11 may be about 20nm, and the size of the end portion of the tapered tip 12 may be about 5nm to lnm.

[0017] The first electrode 1 may also be referred to as a bottom electrode, and the second electrode 4 may also be referred to as a top electrode in this context.

[0018] In various embodiments, the first electrode 1 may further include a silicon layer 13 arranged at least substantially parallel to the memory layer 3, wherein the silicon pillar 1 1 is disposed on the silicon layer 13 such that a longitudinal axis of the silicon pillar 1 1 is perpendicular or at least substantially perpendicular to the silicon layer 13. In various embodiments, the silicon pillar 11 may be formed from the silicon layer 13, and the tapered tip 12 may be further formed from the silicon pillar 11. In various embodiments, the silicon layer 13 may be removed after formation of the silicon pillar 11 and the tapered tip 12.

[0019] According to various embodiments, the first electrode 1 may include doped silicon with p-type or n-type dopants, or may include nickel silicide (NiSi). In various embodiments, the silicon layer 13 and the silicon pillar 11 with the tapered tip 12 may be or may include doped silicon, e.g. highly doped at a dopant concentration of more than 10¹⁶ /cm³. In various embodiments, the silicon layer 13 and the silicon pillar 11 with the tapered tip 12 may be or may include nickel silicide (NiSi). [0020] In various embodiments, an insulating dielectric film 2, such as a Si0₂ layer, may be arranged to surround the silicon pillar 1 1 and the tapered tip 12 of the first electrode 1. In various embodiments, the insulating film 2 may be sandwiched between the memory layer 3 and the silicon layer 13 of the first electrode 1.

[0021] In various embodiment, the second electrode 4 may include a metal film disposed on the memory layer 3.

[0022] According to various embodiments, the memory cell 10 may be a PCRAM memory cell. The memory layer 3 may include a phase change material for the PCRAM memory cell, such as Germanium-Antimony-Tellurium (GeSbTe) alloy, Silver-Indium- Antimony-Tellurium alloy or Aluminum- Antimony alloy. In various embodiments, the memory cell 10 may be a RRAM memory cell. The memory layer 3 may include a resistive material for the RRAM memory cell, such as chalcogenide materials (e.g. Pri_-xCa_xMn0₃, SrTiO), binary metal oxide materials (e.g. NiO, ZnO, Ti0_2} Hf0₂), solid electrolytes (e.g. AgGeS, AgGeSe) or other amorphous films (e.g. amorphous silicon, amoiphous carbon or polymers). In various embodiments, the memory layer 3 may include any other materials capable of providing variable resistances.

[0023] According to various embodiments above, the first electrode 1 with the tapered tip 12 only contacts the memory material 3 at a very small area. In the embodiments of a PCRAM memory cell, the amount of thermal energy required is determined by the volume of the phase-change material undergoing amorphous- crystalline transformation during the switching process. With a minimized electrode contact area, the active volume will be effectively minimized, thereby reducing the amount of thermal energy required. This has the further benefits of reducing the operating current and increasing the switching speed. In the embodiments of a RRAM cell, the common consensus behind the resistance change is the formation or rupture of a conductive filament path between the two metal electrodes. Uniformity of the RRAM devices is dependent on the control over the filament formation (for example, filament size or location). With a minimized electrode contact area provided by the tapered tip 12 of the embodiments, the filament will be localized to a small point, and will improve device-to-device uniformity.

[0024] A memory device may be provided, including the memoiy cell 10 of various embodiments above and a memory access device. The memory access device may be configured to access the memory cell 10 by reading or writing, for example.

[0025] In various embodiments, the memory access device may include a diode disposed in the silicon pillar 11 of the memoiy cell 10. The diode, e.g., the PN junction, may be formed vertically along the longitudinal axis of the silicon pillar 11.

[0026] In various embodiments, the memory access device may include a diode disposed in the silicon layer 13 arranged at least substantially parallel to the memory layer 3. The diode, e.g., the PN junction, may be formed horizontally within the silicon layer 13. The silicon pillar 11 is disposed on the silicon layer 13 such that the longitudinal axis of the silicon pillar 1 1 is at least substantially perpendicular to the silicon layer 13.

[0027] In various embodiments, the memory access device may include a transistor. The transistor may be formed using at least a portion of the silicon pillar 11 as a channel region and using the tapered tip 12 as one of a source region or a drain region. The transistor may be formed using at least another portion of the silicon pillar 11 as one of the source region or the drain region.

[0028] Fig. 2 shows a flowchart 200 illustrating a method of forming a memory cell, e.g. a memory cell of Fig. 1 above, according to various embodiments.

[0029] Various embodiments of the memory cell described above are analogously valid for the method of forming the memory cell, and vice versa.

[0030] At 210, a silicon pillar is formed from a silicon wafer.

[0031] At 220, a tapered tip is formed from the silicon pillar. The silicon pillar with the tapered tip forms a first electrode.

[0032] At 230, a memory layer including a material configured to provide variable resistances is formed. The memory layer has a first surface in contact with the tapered tip and a second surface opposite to the first surface.

[0033] At 240, a second electrode is formed on the second surface of the memory layer.

[0034] In various embodiments, the silicon pillar may be formed by etching a portion of the silicon wafer to form the silicon pillar disposed on a silicon layer, wherein a longitudinal axis of the silicon pillar is substantially perpendicular to the silicon layer.

[0035] In various embodiments, the tapered tip may be formed by forming an insulating layer over the silicon layer and the silicon pillar; etching a portion of the insulating layer to expose a portion of the silicon pillar; and etching the exposed portion of the silicon pillar to form the tapered tip. [0036] In various embodiments, the silicon wafer has a crystal lattice direction of [100], and the exposed portion of the silicon pillar is anisotropically etched.

[0037] In various embodiments, the tapered tip may be formed by fonning a hard mask on the silicon pillar; trimming the hard mask; and anisotropically etching the silicon pillar to form the tapered tip. In various embodiment, the hard mask may be formed on the exposed portion of the silicon pillar, wherein the remaining portion of the silicon pillar may be covered or surrounded by the insulating layer.

[0038] In various embodiments, after anisotropically etching the silicon pillar to form the tapered tip, the tapered tip may be isotropically etched to further trim the tapered tip.

[0039] In various embodiments, after forming the tapered tip, a doping process may be performed for the silicon layer, the silicon pillar and the tapered tip, e.g. to heavily dope the silicon layer and the silicon pillar with the tapered tip at a dopant concentration of more than 10¹⁶ /cm³. In various embodiments, a nickel silicide formation process may be performed for the silicon layer, the silicon pillar and the tapered tip, e.g. to form nickel silicide (NiSi) in the silicon layer and the silicon pillar with the tapered tip. In various embodiments, the doping process or the nickel silicide formation process may be performed for the silicon layer and/or at least a portion of the silicon pillar before formation of the tapered tip, and may be separately performed for the tapered tip after formation of the tapered tip.

[0040] In various embodiments, a diode may be further formed in the silicon pillar. In various embodiments, a diode may be further formed in the silicon layer. In various embodiments, a transistor may be at least partially formed using the silicon pillar and the tapered tip. [0041] The method of forming the memory cell according to various embodiments are described in more detail with reference to Figs. 3 to 1 1 below.

[0042] Figs. 3 to 11 show the fabrication process of the memory cell shown in Fig. 1 according to various embodiments.

[0043] In Fig. 3, a structure 300 after patterning and development of a resist pattern for silicon pillar formation is shown. A photoresist layer 7 is patterned and developed on a silicon wafer 13. The silicon wafer 13 may have a surface orientation of [100] as indicated in Fig. 3. The patterning and development step may be carried out using various lithographic techniques, such as electron-beam, optical and laser interference, depending on the final size requirement on the silicon pillar 11. The pillar size may be further reduced to desired critical dimensions (CD) by resist trimming process, e.g. using 0₂ plasma.

[0044] Fig. 3 shows an embodiment of the resist pattern for a silicon pillar. In various embodiments, a plurality of silicon pillars may be formed by resist patterns as shown in a structure 400 of Fig. 4. As shown in Fig. 4, the photoresist layer 7 is formed in rectangular resist patterns with edges along the [1 10] direction, on the silicon wafer 13 having a surface orientation of [100] direction. In various embodiments, the photoresist layer 7 may also be formed in circular resist patterns or other suitable patterns, depending on a desired shape of the silicon pillar.

[0045] Fig. 5 shows a structure 500 after an etching process to form the silicon pillar according to various embodiments. A portion of the silicon wafer 13 as shown in Fig. 3 is etched, for example, by dry etching process, e.g. using Reactive Ion Etching (RIE) process, to form the silicon pillar 1 1 vertically arranged on another portion of the silicon wafer 13 which has not been etched and is denoted as a silicon layer 13. The height (etching depth) and profile of the silicon pillar 13 may be controlled by the etching conditions.

[0046] Fig. 6(a) shows a structure 600 after a photoresist stripping and cleaning process, in which the photoresist layer 7 is stripped to expose the silicon pillar 11 and the wafer 13 is cleaned. The scanning electron microscope (SEM) image 650 showing the silicon pillar as formed is shown in Fig. 6(b).

[0047] In Fig. 7, a structure 700 after a dielectric deposition and chemical mechanical polishing (CMP) process according to various embodiments is shown. An insulating dielectric layer 2, e.g. Si0₂ layer, is deposited on the surface of the silicon layer 13 and the silicon pillar 11, covering the entire Si pillar 11. A chemical mechanical polishing process is then perfonned for surface planarization. The duration of the CMP may be controlled such that a dielectric layer 2 of about 500A~1000A remains on top of the silicon pillar 11.

[0048] Fig, 8 shows a structure 800 after an etching process to expose a portion of the silicon pillar according to various embodiments. As shown in Fig. 8, a portion of the dielectric layer 2 is etched back, e.g. by oxide wet etching using dilute HF (hydrofluoric acid) or using other suitable etchants, to reveal or expose a top portion or an end portion of the silicon pillar 11. The etching duration may be controlled such that the height of the exposed silicon pillar is equal to or larger than the critical dimension of the silicon pillar.

[0049] Fig. 9(a) shows a structure 900 after a process to form the tapered tip from the silicon pillar according to various embodiments. As shown in Fig. 9(a), an anisotropic silicon wet etching process using a suitable chemical etching solution, such as KOH (potassium hydroxide), is performed on the exposed silicon pillar to form the tapered tip 12. The anisotropic wet etching may use any suitable anisotropic etchants for formation of the tapered tip 12, such as IPA (Isopropyl alcohol), TMAH (Tetramethylammonium hydroxide), or EDP (Ethylenediamine pyrocatechol). The anisotropic etching is a result of different etching rates of Si atoms at different crystal planes, due to different bonding energies of silicon atoms for different crystal planes. By way of illustration, the etching rate at { 111 } plane is significantly lower as compared to that at {100} plane. For example, the etchant KOH (44%, 85°C) may yield an etching rate ratio of 300 for { 100}/{1 11} planes and an etching rate ratio of 600 for {110}/{ 111 } planes. Accordingly, the {1 11 } plane may act as an etch stopper. An etching duration that is enough to etch half of the silicon pillar CD (critical dimension) may be sufficient for the formation of the tapered silicon tip 12.

[0050] In the embodiments shown in Fig. 9(a), the tapered tip 12 is shown in a cone shape having a triangular cross-section, it is understood that the tapered tip 12 may also be formed in other tapered shapes, such as a truncated cone shape, a pyramid shape, or a truncated pyramid shape.

[0051] In various embodiments, an NiSi process or a high-doping process may be performed for the first electrode 1. In various embodiments, the silicon layer 13 and the silicon pillar 11 with the tapered tip 12 may be doped, e.g. highly doped at a dopant concentration of more than 10¹⁶ /cm³. In various embodiments, the silicon layer 13 and the silicon pillar 1 1 with the tapered tip 12 may be diffused with nickel, e.g. to form nickel silicide (NiSi). Accordingly, the first electrode of doped silicon or NiSi is formed, including the silicon pillar 11 with the tapered tip 12 and the silicon layer 13. In other embodiments, the first electrode may not need to include the silicon layer 13, which may be removed after fonnation of the silicon pillar and the tapered tip. The silicide or doping process is compatible with CMOS processes.

[0052] Fig. 9(b) shows an SEM image 950 at Ιμιη view field, showing the silicon pillar with the tapered tip according to various embodiments. The tapered silicon tip, also referred to as a NW(nanowire) tip, may be formed by a wet etching process as described above, or may be formed by a dry etching process in other embodiments.

[0053] Fig. 10 shows a structure 1000 after a dielectric deposition and CMP process according to various embodiments. The dielectric material is deposited to cover the surface of the dielectric layer 2 of Fig. 9(a) and the tapered tip 12, and the CMP process is performed for surface planarization. In various embodiments, the CMP process may stop at the top of the tapered tip 12, e.g. at the top surface of the end portion of the tapered tip 12. In various embodiments, the CMP process may stop halfway on top of the tapered tip, followed by an oxide wet etch to release or expose the top of the tapered tip, e.g. to expose the top surface of the end portion of the tapered tip. The wet etch back may be controlled to release just the top surface of the tapered tip 12, and the rest of the tapered tip and the Si pillar 1 1 underneath the tip 12 remain buried in the dielectric layer 2.

[0054] Fig. 11 shows a memory cell 10 formed according to a process of various embodiments. The process includes memory material deposition, top electrode metal deposition, top electrode lithography, and dry etching for top electrode and memory material, so as to form the memory layer 3 and the second electrode 4 (in other words, the top electrode 4) of Fig. 1. R AM material, or PCRAM material, or any suitable material capable of providing variable resistances to be used as a memory material, may be used to form the memory layer 3. The memory cell 10 of Fig. 1 is thus formed.

[0055] In various embodiments, various contact structures may be further formed for the memory cell. Fig. 12 shows a memory cell 20 after carrying out a backend process and metal line formation to form further contact structures for the memory cell 10 of Fig. 10 according to various embodiments.

[0056] As shown in Fig. 12, a via contact 5a may be formed over the top electrode (TE) 4 and a metal line 6a is further formed over the via contact 5a. A through via contact 5b may also be formed throughout the dielectric layer 2. The through via contact 5b is in contact with the silicon layer 13 of the bottom electrode (BE) 1 at one end, and is in contact with a metal line 6b formed thereon at the other end.

[0057] According to various embodiments above, a tapered tip, e.g., a nanoscale tip or an atomic scale tip, may be achieved by self-limiting anisotropic etching of an exposed silicon pillar. The tapered tip formation may require only one mask process, and is fully CMOS compatible.

[0058] In various embodiments, a memory device may be provided, including a memory cell described in various embodiments above and a memory access device.

[0059] Fig. 13 shows a cross-sectional view of a memory device 30 of a 1D1R (one- diode one-resistor) structure according to various embodiments. The memory device 30 includes the memory cell 20 of Fig. 12 above, and further includes a memory access device 31. In various embodiments, the memory device 30 may also include the memory cell 10 of Fig. 11 above. In various embodiments, the memory access device 31 may include a diode 31 disposed horizontally in the silicon layer 13 of the first electrode (BE). The PN diode 31 may have one terminal in connection with the first electrode 1 of the memory cell, and have the other terminal in connection with the through via contact 5b. In this embodiment, the memoiy access device 31 is integrated in the silicon layer 13 of the first electrode 1.

[0060] Fig. 14 shows a cross-sectional view of a memoiy device 40 of a 1D1R (one- diode one-resistor) structure according to various embodiments. The memory device 40 includes the memory cell 20 described in Fig. 12 above, and further includes a memory access device 41. In various embodiments, the memory device 40 may also include the memory cell 10 of Fig. 1 1 above. In various embodiments, the memory access device 41 may include a diode 41 disposed vertically in the silicon pillar 11 of the first electrode (BE). In this embodiment, the vertical silicon nanowire structure is utilized to integrate the memoiy access device 41 vertically beneath the memory cell, which is advantageous in achieving a reduced footprint.

[0061] Fig. 15 shows a cross-sectional view of a memory device 50 of a IT 1R (one- transistor one-resistor) structure according to various embodiments. The memory device 50 includes the memory cell 20 described in Fig. 12 above, and further includes a memory access device 51. In various embodiments, the memory device 50 may also include the memory cell 10 of Fig. 11 above. In various embodiments, the memory access device 51 may include a transistor 1 at least partially integrated in the silicon pillar 11 and the tapered tip 12 of the first electrode 1. The transistor 51 may be vertically formed, including a polysilicon layer 8 or a metal layer 8 formed in the dielectric layer 2 and surrounding the silicon pillar 1 1 to serve as the gate electrode of the transistor 51. The tapered tip 12 may serve as one of a source electrode or a drain electrode of the tapered tip 12, e.g. the drain electrode of the transistor 51 as shown in Fig. 15. At least a portion of the silicon pillar 11 may serve as a channel region of the transistor 51. At least another portion of the silicon pillar 11 of the bottom electrode 1, e.g. a bottom portion of the silicon pillar 1 1 at a distance away from the tapered tip 12, may serve as one of the source electrode or the drain electrode of the tapered tip 12, e.g. the source electrode of the transistor 51 as shown in Fig. 15. In an embodiment wherein the bottom electrode 1 may further include the silicon layer 13 disposed under the silicon pillar 11 as shown in Fig. 15, the silicon layer 13 along with the portion of the silicon pillar 11 may serve as the source electrode of the transistor 51. A via contact 5c may be further formed in the dielectric layer 2 to be in contact with the polysilicon/metal layer 8 at one end, and in contact with a metal line 6c formed at the other end. In this embodiment, the transistor 51 does not occupy additional footprint, making the memory device 50 more compact.

[0062] In various embodiments, the formation of the transistor 51 may start from the structure 600 of Fig. 6(a). Dopant ion implantation is performed on the structure 600 to form the source region of the transistor, e.g. in the silicon layer 13 and at least a portion of the silicon pillar 11 (e.g. a portion of the silicon pillar 11 adjacent to the silicon layer 13). This is followed by a dielectric deposition and chemical mechanical polishing (CMP) process to form structure 700 of Fig. 6, further followed by an etching process to expose a portion of the silicon pillar as indicated in structure 800 of Fig. 8. The insulating layer 2 of the structure 800 may be further etched, e.g. using a wet etching process, to a predetermined depth to release or expose the silicon pillar 11 until a position where the gate electrode of the transistor 51 is to be formed. Gate oxidation is then preformed to form a gate oxide layer on the top surface of the insulating layer 2 and surrounding the exposed silicon pillar 11. A polysilicon layer or a metal layer is then deposited on the gate oxide layer. Gate lithography and gate etching processes are performed for the polysilicon/metal layer to form the gate pattern. An oxide deposition is performed to deposit the insulating layer 2 covering the silicon pillar 11 and the polysilicon/metal layer, followed by a CMP process to flatten the surface of the insulating layer 2. An etching process, e.g. an oxide wet etching process, is then performed to etch a portion of the insulating layer 2, so as to release or expose a portion of the silicon pillar surrounded by the polysilicon/metal layer to a predetermined height. The exposed polysilicon/metal layer surrounding the silicon pillar is then etched to expose the portion of the silicon pillar. A dopant ion implantation is then earned out on the exposed portion of the silicon pillar to form the drain region of the transistor. From the exposed portion of the silicon pillar, the tapered tip formation process as shown in Fig. 9 onwards is then continued to form the entire memory device 50.

[0063] Various embodiments above accordingly provide 1D1R integration or 1T1R integration using the vertical silicon nanowire for memory access device integration and using the tapered tip as the memory electrode.

[0064] Various embodiments of the fabrication process of the memory cell described above may be analogously applied to form any one of the memory devices of Figs. 13-15.

[0065] Fig. 16 shows ANSYS Finite Element Model (FEM) to simulate the silicon nanowire (silicon pillar) and the tapered tip structure for electrical potential comparison. Fig. 16(a) shows a memory cell 1610 with a conventional nanowire electrode, including a nanowire (NW) bottom electrode with a critical dimension (CD) of 20nm, a switching layer as the memory layer, and a metal layer as the top electrode. Fig. 16(b) shows a memory cell 1620 using a silicon nanowire with a tapered tip as the bottom electrode as described in various embodiments above. In Fig. 16(b), the silicon nanowire has a diameter of 20nm and a height of 300nm, the memory layer has a thickness of 50nm and a width of 1 OOnm.

[0066] Fig. 16(c) shows the simulated electric potential 1630 for the conventional nanowire electrode of Fig. 16(a), in which the electric potential is evenly distributed along the top surface of the nanowire, which indicates large effective active area. Fig. 16(d) shows the simulated electric potential 1 40 for the tapered tip electrode of Fig. 16(b), in which the electric potential is concentrated at the top end of the tip and the electric field is the highest at the top end of the tip. This results in a localized electric field, and thus the effective active area is greatly reduced. This localized electric field for the tapered tip structure greatly benefits the RRAM and PCRAM uniformity and operation power.

[0067] The various embodiments in Figs. 1 to 16 above show a tapered tip in a cone shape. It is understood that the tapered tip may be in other shapes in other embodiments.

[0068] Fig. 17 shows a structure 1700 illustrating a silicon pillar with a tapered tip according to various embodiments.

[0069] In Fig. 17, a rectangular end portion with a flat top surface is shown. The tapered tip 12 may include an end portion 12a in the shape of a cylinder or cuboid, which has a rectangular cross section as shown in Fig. 17. The end portion 12a is in contact with the bottom surface of the memory layer 3. The tapered tip 12 may further include one or more tapered portion 12b arranged between the end portion 12a of the tapered tip and a body of the silicon nanowire 11. This tapered tip structure 1700 may be formed by etching the silicon pillar 11 shown in Fig. 5 using a hard mask process, as illustrated in Fig. 18 below. The SEM image 1710 on the right side indicates that such a structure 1700 can be formed successfully using an oxide hard mask (HM).

[0070] Fig. 18 shows a process of forming the structure 1700 of Fig. 17 according to various embodiments. After formation of the silicon pillar 1 1 as shown in Fig. 5, the photoresist layer 7 is stripped, and a hard mask 18 (e.g. Si0₂ mask or any other suitable material which can be used as the hard mask) is deposited on the top surface of the silicon pillar 11, as shown in Fig. 18(a). The hard mask 18 is further trimmed using a hard mask trimming process, e.g., a wet chemical oxide etch, to further reduce the dimension of the hard mask 18, as shown in Fig. 18(b). This may be then followed by Si anisotropic dry etching process in Fig. 18(c) to partially etch the silicon pillar 11. The rectangle- shaped tip top 12a is formed with the protection of the hard mask 18. The shape of the tapered portion 12b may be naturally formed, for example, in the anisotropic etching process which is not 100% anisotropic in practice. Accordingly, the structure 1700 is formed.

[0071] Defining an angle Θ as the angle of the tip edge with respect to a vertical line, the end portion 12a of the structure 1700 has the tip angle θ=0°, and may ideally achieve the 3σ variation of Onm in tip critical dimension (CD).

[0072] Fig. 19 shows a structure 1900 illustrating a silicon pillar with a tapered tip according to various embodiments. In Fig. 19, a sharp angled end portion of the tapered tip is shown. The tapered tip 12 may include an end portion 12c in the shape of a cone, a truncated cone, a pyramid, or a truncated pyramid. The end portion 12c is in contact with the bottom surface of the memory layer 3. The tapered tip 12 may further include one or more tapered portion 12d arranged between the end portion 12c of the tapered tip and a body of the silicon nanowire 11. The SEM image 1 10 on the right side shows a plurality of the structure 1700 with the sharp angled end portion.

[0073] Fig. 20 shows a process of forming the structure 1900 of Fig. 19 according to various embodiments. Similar to the process of Fig. 18 above, after formation of the silicon pillar 1 1 as shown in Fig. 5, the photoresist layer 7 is stripped and the hard mask 18 (e.g. Si0₂ mask or any other suitable material which can be used as the hard mask) is deposited on the top surface of the silicon pillar 11 , as shown in Fig. 20(a). The hard mask 18 is trimmed using a hard mask trimming process, e.g., a wet chemical oxide etch, to further reduce the dimension of the hard mask 18, as shown in Fig. 20(b). Next, the anisotropic dry etching process is performed in Fig. 20(c) to partially etch the silicon pillar 1 1, which may form a rectangle shaped tip top 12a with the protection of the hard mask 18 and the tapered portion 12b naturally formed due to an non-100% anisotropic etching process similar to Fig. 18(c) above. Next, an isotropic silicon etching process is performed in Fig. 20(d) to further etch the top end portion 12a and the tapered portion 12b of the silicon pillar. This isotropic etching process will further trim both the top end portion 12a and the bottom tapered portion 12b, so as to form the final end portion 12c and the final tapered portion 12d of the structure 1900 at the same time. The isotropic Si dry etching process (e.g. using SF6/C12 chemistry) may have a sharpening effect on a pillar structure. [0074] The end portion 12c of the structure 1900 has the tip angle θ< 9°, and may achieve the 3σ variation of smaller than lnm in tip critical dimension (CD).

[0075] The processes in Fig. 18 and Fig. 20 described in the above embodiments are started from the silicon pillar 11 formed in Fig. 5. It is understood that in other embodiments the processes in Fig. 18 and Fig. 20 may also be started from the structure 800 of Fig. 8, wherein a portion of silicon pillar 11 is exposed and the remaining portion of the silicon pillar 11 is buried in the insulating layer 2. The processes in Fig. 18 and Fig. 20 may thus be performed on the exposed portion of the silicon pillar 11 to fonn the tapered tip 12 according to various embodiments of Fig. 17 and Fig. 19 above. After formation of the tapered tip 12, further processes according to the embodiments of Figs. 9 to 15 may be performed to form the entire memory cell or the entire memory device.

[0076] The embodiments of Fig. 17 and 19 may have better process tolerance compared with the tapered tip in the shape of a cone, a truncated cone, a pyramid, or a truncated pyramid. The embodiments of Fig. 17 and 19 may be used in the memory cell 10, 20 of Figs. 1 1-12 and the memory devices 20, 30, 40 of Figs. 13-15 above.

[0077] Fig. 21 illustrates the investigation result 2100 of the tolerance for the CMP process and the impact of CMP process uniformity on the resulting tip width or diameter, if the approach to reveal the electrode tip 12 involves directly polishing the dielectric layer until the electrode tip 12 is actually exposed. Since the polishing rate may be different across different parts of the wafer, the effect of this process variation on the resulting tip width/diameter is important. After formation of the tapered tip 12, due to non-uniformity of the CMP process, CMP stopping point for different portions of the tip across a wafer may be different. Accordingly, the CMP may not stop at a target CMP stopping point but in a stopping range. As shown in the zoom-in figure 21 10 of the tip top on the right, the angle Θ is defined as the angle of the tip edge with respect to a vertical line. The relationship between the tip angle Θ and the exposed tip critical dimension

(CD) variation is calculated for a typical CMP process with non-uniformity of 3.3% is investigated and shown in Fig. 1 below.

[0078] Fig. 22 shows a graph 2200 illustrating the exposed tip CD variation dependence with the tip angle Θ. For a CMP thickness of lOOnm

and a

CMP non-uniformity of 3.3%, the relationship between the tip angle Θ and the 3σ variation in tip CD is calculated. As depicted by the rectangle 2210 in Fig. 19, when Θ <

9°, the 3σ CD variation will be smaller than 1 nm, which means that uniform tip CDs can be achieved to be within 1 nm accuracy despite variations in CMP polishing rates and therefore a good process tolerance is able to be achieved.

[0079] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

Claims What is claimed is:

1. A memory cell, comprising:

a memory layer having a first surface and a second surface opposite to the first surface, the memory layer comprising a material configured to provide variable resistances;

a first electrode disposed on the first surface of the memory layer; and

a second electrode disposed on the second surface of the memory layer;

wherein the first electrode comprises a silicon pillar with a tapered tip, and the tapered tip is in contact with the first surface of the memory layer.

2. The memory cell of claim 1,

wherein the silicon pillar is a silicon nanowire^

3. The memory cell of claim 1 or 2,

wherein a diameter of an end portion of the tapered tip is substantially smaller than a diameter of the silicon pillar.

4. The memory cell of any one of claims 1 to 3, wherein

the tapered tip is in a shape selected from cone, truncated cone, pyramid, or truncated pyramid.

5. The memory cell of any one of claims 1 to 3,

wherein the tapered tip comprises an end portion in contact with the first surface of the memory layer,

wherein the end portion is in a shape selected from cone, truncated cone, pyramid, truncated pyramid, cylinder, or cuboid.

6. The memory cell of any one of claims 1 to 5,

wherein the tapered tip comprises one or more tapered portion arranged between an end portion of the tapered tip and a body of the silicon pillar.

7. The memory device of any one of claims 1 to 6,

wherein the first electrode further comprises a silicon layer arranged at least substantially parallel to the memory layer,

wherein the silicon pillar is disposed on the silicon layer such that a longitudinal axis of the silicon pillar is at least substantially perpendicular to the silicon layer.

8. The memory cell of any one of claims 1 to 7,

wherein the first electrode comprises at least one of nickel silicide or doped silicon.

9. The memory cell of any one of claims 1 to 8, wherein the memory cell is one of a resistive random access memory cell or a phase change memory cell.

10. A memory device, comprising:

a memory cell of any one of claims 1 to 9; and

a memoiy access device.

1 1. The memory device of claim 10,

wherein the memory access device comprises a diode disposed in the silicon pillar.

12. The memory device of claim 10,

wherein the memory access device comprises a diode,

wherein the diode is disposed in a silicon layer arranged at least substantially parallel to the memoiy layer, and the silicon pillar is disposed on the silicon layer such that a longitudinal axis of the silicon pillar is at least substantially perpendicular to the silicon layer.

13. The memoiy device of claim 10,

wherein the memoiy access device comprises a transistor,

wherein the transistor is formed with at least a portion of the silicon pillar as a channel region of the transistor, and with the tapered tip as one of a source region or a drain region of the transistor.

14. A method of forming a memory cell, comprising:

forming a silicon pillar from a silicon wafer;

forming a tapered tip from the silicon pillar, the silicon pillar with the tapered tip forming a first electrode;

forming a memory layer comprising a material configured to provide variable resistances, wherein the memory layer has a first surface in contact with the tapered tip and a second surface opposite to the first surface;

forming a second electrode on the second surface of the memory layer.

15. The method of claim 14, wherein forming the silicon pillar comprises:

etching a portion of the silicon wafer to form the silicon pillar on a silicon layer, wherein a longitudinal axis of the silicon pillar is at least substantially perpendicular to the silicon layer.

16. The method of claim 15, wherein forming the tapered tip comprises:

forming an insulating layer over the silicon layer and the silicon pillar, etching a portion of the insulating l yer to expose a portion of the silicon pillar; etching the exposed portion of the silicon pillar to form the tapered tip.

17. The method of claim 18,

wherein the silicon wafer has a crystal lattice direction of [100], and

wherein the exposed portion of the silicon pillar is anisotropically etched.

18. The method of any one of claims 14 to 17, wherein forming the tapered tip comprises:

forming a hard mask on the silicon pillar;

trimming the hard mask; and

anisotropically etching the silicon pillar to form the tapered tip.

19. The method of claim 18, further comprising:

after anisotropically etching the silicon pillar to form the tapered tip, isotropically etching the tapered tip to trim the tapered tip.

20. The method of any one of claims 15 to 19, further comprising at least one of: doping the silicon layer, the silicon pillar and the tapered tip; or

forming nickel silicide in the silicon layer, the silicon pillar and the tapered tip.