WO2016049903A1 - Method and apparatus for intersect parallel data between multi-ingress and multi-egress - Google Patents
Method and apparatus for intersect parallel data between multi-ingress and multi-egress Download PDFInfo
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Abstract
A method and an apparatus for determining route information of intersect parallel data between multi-ingress and multi-egress are disclosed. Herein the number of ingress, egress and MUX are all N, each ingress connects to all the MUXes and each MUX connects to one egress, and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes. The method comprises generating a route-table group based on data transfer sequences between the multi-ingress and multi-egress, wherein the route-table group includes a set of route-table for each ingress to indicate the retrieving address of data samples to be transferred, a set of route-table for each egress to indicate the data samples selected from those transferred from all the ingresses, and a set of route-table for each egress to indicate the saving address of the selected data samples. The method enables to synchronously retrieve one data sample from different ingresses-RAMs and then push the data samples into destination egress-RAMs, respectively.
Description
The present invention relates to the technology of intersect parallel data transferring between multi-ingress and multi-egress.
BACKGROUND OF INVENTION
The requirement of intersect parallel data transferring between multi-ingress and multi-egress is shown in Fig. 1. It is widely applied to any platform of telecommunication. Fig. 2 shows an existing solution to implement intersect parallel data. However， the defect of the solution is obvious. Data needs to be redundant stored in the block-RAMs between the ingress-RAMs and the MUXes， and thus this costs a large amount of storage of the block-RAMs. The cost becomes larger with more links.
SUMMARY OF INVENTION
The objective of the present invention is to provide a method and apparatus for determining route information of intersect parallel data between multi-ingress and multi-egress.
According to one aspect of the present invention， a method for determining route information of intersect parallel data between multi-ingress and multi-egress is provided. Herein the number of ingress， egress and MUX are all N， each ingress connects to all the MUXes and each MUX connects to one egress， and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes. The method comprises the following step：
-generating a route-table group based on data transfer sequences between the multi-ingress and multi-egress， wherein the route-table group includes a set of route-table for each ingress to indicate the retrieving address
of data samples to be transferred， a set of route-table for each egress to indicate the data samples selected from those transferred from all the ingresses， and a set of route-table for each egress to indicate the saving address of the selected data samples.
According to one aspect of the present invention， a switch device for intersect parallel data between multi-ingress and multi-egress is provided. The switch device comprises multiple ingresses， multiple egresses， and multiple MUX between the multi-ingress and multi-egress， wherein the number of ingress， egress and MUX are all N， each ingress connects to all the MUXes and each MUX connects to one egress， and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes；
wherein in the transfer of a data sequence，
each ingress is configured to retrieve data to be transferred according to a route-table of the ingress which indicates the retrieving address of the data， and transfer the retrieved data to all the MUX；
each MUX is configured to transfer the data received from an ingress to a corresponding egress according to a route-table of the MUX which indicates the destination egress corresponding to an ingress transferring the retrieved data；
each egress is configured to save the data received from a corresponding MUX according to a route-table which indicates the saving address of the received data.
According to one aspect of the present invention， a device for determining route information of intersect parallel data between multi-ingress and multi-egress is provided. Herein the number of ingress， egress and MUX are all N， each ingress connects to all the MUXes and each MUX connects to one egress， and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes. The device is configured to：
-generate a route-table group based on data transfer sequences between the multi-ingress and multi-egress， wherein the route-table group includes a
set of route-table for each ingress to indicate the retrieving address of data to be transferred， a set of route-table for each egress to indicate the data samples selected from those transferred from all the ingresses， and a set of route-table for each egress to indicate the saving address of the selected data samples.
According to one aspect of the present invention， a computer-readable medium is provided. The computer readable medium containing computer code， when executed by a switch device comprising multiple ingresses， multiple egresses， and multiple MUX between the multi-ingress and multi-egress， wherein the number of ingress， egress and MUX are all N， each ingress connects to all the MUX and each MUX connects to one egress， and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes；
wherein the computer-readable medium is operable to cause the switch device to perform the following step：
-generate a route-table group based on data transfer sequences between the multi-ingress and multi-egress， wherein the route-table group includes a set of route-table for each ingress to indicate the retrieving address of data to be transferred， a set of route-table for each egress to indicate the data samples selected from those transferred from all the ingresses， and a set of route-table for each egress to indicate the saving address of the selected data samples.
According to one aspect of the present invention， a computer program is provided. When executed by a switch device comprising multiple ingresses， multiple egresses， and multiple MUX between the multi-ingress and multi-egress， wherein the number of ingress， egress and MUX are all N， each ingress connects to all the MUX and each MUX connects to one egress， and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes；
wherein the computer program is operable to cause the switch device to perform the following step：
-generate a route-table group based on data transfer sequences between
the multi-ingress and multi-egress， wherein the route-table group includes a set of route-table for each ingress to indicate the retrieving address of data to be transferred， a set of route-table for each egress to indicate the data samples selected from those transferred from all the ingresses， and a set of route-table for each egress to indicate the saving address of the selected data samples.
The present application enables to synchronously retrieve one data sample from different ingresses-RAMs and then push the data samples into destination egress-RAMs， respectively.
DESCRIPTION OF ACCOMPANIED DRAWINGS
Through reading the following detailed depiction on the non-limiting embodiments with reference to the accompanying drawings， the other features， objectives， and advantages of the present invention will become clearer.
Fig. 1 shows a schematic of the requirement for intersect parallel data between multi-ingress and multi-egress；
Fig. 2 shows a schematic of the existing solution to implement intersect parallel data；
Fig. 3 shows a schematic of block-RAMs for intersect parallel data according to the present application；
Fig. 4 shows a schematic of RRH architechture according to an embodiment of the present application；
Fig. 5 shows a schematic of function block of crossbar module of the RRH shown in Fig. 4 according to an embodiment of the present application.
Same or like reference numerals in the accompanying drawings indicate the same or corresponding components.
EMBODIMENT OF INVENTION
Hereinafter， the present invention will be further described in detail with reference to the accompanying drawings.
The present invention provides a solution to determine route information of intersect parallel data transferring between multi-ingress and multi-egress. Further， the present invention is applicable to any kind of switch devices having a symmetrical multi-ingress and multi-egress. Moreover， besides the switch devices， the determination of route information can also be done by other devices such as a dedicated determination device， though the route information is used in the switch devices having a symmetrical multi-ingress and multi-egress.
Specifically， for the multi-ingress and multi-egress， the number of ingress and egress are both N， and N MUXes are between the multi-ingress and multi-egress. Each ingress connects to all the MUXes and each MUX connects to one egress.
For a packet containing N*M data samples， it needs M transfer cycles to be transferred from the multi-ingress to the multi-egress. The packet to be transferred constitutes a N*N data matrix. And in each transfer cycle， a data transfer sequence from the multi-ingress to the multi-egress constitutes a N*N transfer matrix. Thus there are M transfer matrixes for a packet transferring. In each N*N transfer matrix， no more than one data sample in every row and column， and thus N data samples at most get transferred in a transfer cycle.
According to the transfer sequences for data transferring， a route-table group is generated. The route-table group includes three sets of route-table for the multi-ingress， the multi-MUX and the multi-egress， respectively. Specifically， a set of route-table is for each ingress to indicate the retrieving address of data samples to be transferred， a set of route-table is for each egress to indicate the data samples selected from those transferred from all the ingresses， and a set of route-table is for each egress to indicate the saving address of the selected data samples.
The route-table group can be generated at least in the following two
manners：
1) The route-table group can be generated in real time based on the data transfer sequences that have been already determined.
When the data transfer sequences from the multi-ingress to the multi-egress are determined， the route-table group including three sets of route-table respectively for each ingress and each egress are generated accordingly.
2) The route-table group can be generated by adjusting a predefined route-table group based on the data transfer sequences that have been already determined.
A route-table group can be predefined. It includes a set of predefined route-table for each ingress to indicate the retrieving address of data samples to be transferred， a set of predefined route-table for each egress to indicate the data samples selected from those transferred from all the ingresses， and a set of predefined route-table for each egress to indicate the saving address of the selected data samples.
When the data transfer sequences from the multi-ingress to the multi-egress are known， the route-table group can be adjusted accordingly. Specifically， every data sample in a transfer matrix indicates a corresponding transferring relationship between an ingress and an egress. In the predefined route-table group， a data sample from any ingress can be transferred to any egress. Thus the routing sequence in each route-table can be adjusted based on the data transfer sequences， and then the real-time route-table group can be generated.
With reference to Fig. 3， taking a 4*4 multi-links for example， 4 block-RAMs on the left side represent the multi-ingress RAMs， 4 block-RAMs on the right side represent the multi-egress RAMs， and 4 MUX between them. Each ingress-RAM stores data samples to be transferred to multi-egress via multi-MUX. Each egress-RAM stores data samples received from multi-ingress via multi-MUX.
Every ingress-RAM connects to all the MUXes， and each MUX connects to one egress-RAM. A route-table group can be generated offline. Specifically， the route-table group includes three sets of route-table： one set of route-table at each ingress is for the corresponding ingress to know where to retrieve the data samples to be transferred； one set of route-table at each MUX is for the corresponding egress to know which data samples to be selected from those transferred from the multi-ingress； and one set of route-table at each egress is for the corresponding egress to know where to save the selected data samples.
Herein， each route-table can be stored into the corresponding block-RAM such as ingress-RAM， MUX and egress RAM， or it can be stored into another block-RAM connected to the corresponding link. Preferably， the whole route-table group can be stored into a standalone block-RAM， e. g. ， route-table block-RAM.
When the data transfer sequences are known， eg. ， 64 transfer matrixes for a packet， the route-table group can be generated accordingly. For easy illustration and description， here below 4 transfer sequences in ingress 1-4 are used to illustrate in Table 1.
| 1 | 2 | 3 | 4 | |
| ingress-1 | egress 1-1 | egress 2-1 | egress 3-1 | egress 4-1 |
| ingress-2 | egress 1-2 | egress 2-2 | egress 3-2 | egress 4-2 |
| ingress-3 | egress 1-3 | egress 2-3 | egress 3-3 | egress 4-3 |
| ingress-4 | egress 1-4 | egress 2-4 | egress 3-4 | egress 4-4 |
Table 1
wherein for egress m-n， m indicates the egress number and n indicates the transfer sequence number.
The cross connection relationships of the multi-ingress and the multi-egress are shown as below in Table 2.
| egress-1 | egress-2 | egress-3 | egress-4 | |
| ingress-1 | 1 | 1 | 1 | 1 |
| ingress-2 | 1 | 1 | 1 | 1 |
| ingress-3 | 1 | 1 | 1 | 1 |
| ingress-4 | 1 | 1 | 1 | 1 |
Table 2
wherein “1” indicates there is a connection between an ingress and an egress.
Assuming that： the diagonal element 1-1， 2-2， 3-3， 4-4 is the first transfer sequence； the diagonal element 2-1， 3-2， 4-3， 1-4 is the second transfer sequence； the diagonal element 3-1， 4-2， 1-3， 2-4 is the third transfer sequence； and the diagonal element 4-1， 1-2， 2-3， 3-4 is the fourth transfer sequence. Herein， the element is represented by egress number-ingress number. The routing sequences are exemplarily shown in the below Table 3.
| 1 | 2 | 3 | 4 | |
| ingress-1- |
1 | 2 | 3 | 4 |
| mux-1- |
1 | 2 | 3 | 4 |
| egress-1- |
1 | 2 | 3 | 4 |
| ingress-2- |
2 | 3 | 4 | 1 |
| mux-2- |
2 | 3 | 4 | 1 |
| egress-2- |
2 | 3 | 4 | 1 |
| ingress-3- |
3 | 4 | 1 | 2 |
| mux-3- |
3 | 4 | 1 | 2 |
| egress-3- |
3 | 4 | 1 | 2 |
| ingress-4- |
4 | 1 | 2 | 3 |
| mux-4- |
4 | 1 | 2 | 3 |
| egress-4- |
4 | 1 | 2 | 3 |
Table 3
As shown above， the ingress-x-address indicates the corresponding ingress where to retrieve the data sample， and the mux-x-address indicates the corresponding egress which data sample to be selected， and the ingress-x-address indicates the corresponding egress where to save the data
sample.
According to all the known transfer sequences， the corresponding routing sequences can be determined and thus the route-table group can be generated.
On the condition of same throughput between ingress and egress， it needs higher process frequency to serially transfer data from ingress to egress. Thus it is necessary to intersect parallel data to reduce the process frequency.
To avoid the congestion of ingress and egress， the retrieving sequence from the multi-ingress and the saving sequence to the multi-egress must be designed consistently.
For an exemplary illustration of the present invention， the route-table group is described to be generated by a switch device. Preferably， a dedicated generator is incorporated in the switch device to generate the route-table group.
The switch device comprises a module exemplarily arranged as Fig. 3. Specifically， every ingress has a block-RAM to store data that to be transferred to the multi-egress， and each ingress connects to all the MUXes. Each MUX connects to an egress.
According to the data transfer sequences， the corresponding routing sequences are determined. And thus three sets of route-table respectively for multi-ingress， multi-MUX and multi-egress are determined， which are specifically as below：
1) The route-table applied at each ingress includes In-Ram read addresses for a corresponding ingress， and the read address indicates where to retrieve data samples from the ingress_RAM at the specific sequence；
2) The route-table applied at each egress includes Out-Ram write addresses for a corresponding egress， and the write address indicates where to save data samples to the egress-RAM at the specific sequence；
3) The route-table applied at each MUX includes switch addresses for a corresponding egress， and the switch address enables to realize the inter-link
transferring.
Preferably， the switch device can predefine a route-table group based on the connection between the multi-ingress， multi-MUX and multi-egress. When the data transfer sequences are known， the switch device can update the route-table group by adjusting the routing sequences to the transfer sequences.
Each ingress is configured to retrieve data to be transferred according to a route-table of the ingress which indicates the retrieving address of the data， and transfer the retrieved data to all the MUXes；
Each MUX is configured to transfer the data received from an ingress to a corresponding egress according to a route-table of the MUX which indicates the destination egress corresponding to an ingress transferring the retrieved data；
Each egress is configured to save the data received from a corresponding MUX according to a route-table which indicates the saving address of the received data.
According to an embodiment of the present invention， a RRH device is applicable. Referring to Fig. 4， the RRH architecture is illustrated. The RRH device comprises a crossbar module which functions as a packet switch. As shown in Fig. 4， the crossbar module locates between CPRI interface and antennae process chain (hereinafter abbreviated as antennae-x/x) .
LTE-BBU packages X*Y*Z data samples as one packet. X is the number of antennae， Y is the number of carriers per antennae， and K is the number of data samples per carrier.
For example， LTE-BBU package 8*4*8 data samples as one packet in this specification for exemplarily illustration. The total number of data samples is 256.
The packet transfers from LTE-BBU to RRH by CPRI lane.
One CPRI lane only provides 64 data samples capability， and thus 4 CPRI lanes exist.
LTE-BBU packages the 64 data samples according to the customer
configuration. An exemplary example of “packet format” is shown in the below Table 4， wherein LTE-BBU packages the data samples based on the same carrier. The packet format is random for RRH.
| CPRI-Lane-1 | CPRI-Lane-2 | CPRI-Lane-3 | CPRI-Lane-4 |
| Antennae_1-Carrier_1 | Antennae_1-Carrier_2 | Antennae_1-Carrier_3 | Antennae_1-Carrier_4 |
| Antennae_2-Carrier_1 | Antennae_2-Carrier_2 | Antennae_2-Carrier_3 | Antennae_2-Carrier_4 |
| Antennae_3-Carrier_1 | Antennae_3-Carrier_2 | Antennae_3-Carrier_3 | Antennae_3-Carrier_4 |
| Antennae_4-Carrier_1 | Antennae_4-Carrier_2 | Antennae_4-Carrier_3 | Antennae_4-Carrier_4 |
| Antennae_5-Carrier_1 | Antennae_5-Carrier_2 | Antennae_5-Carrier_3 | Antennae_5-Carrier_4 |
| Antennae_6-Carrier_1 | Antennae_6-Carrier_2 | Antennae_6-Carrier_3 | Antennae_6-Carrier_4 |
| Antennae_7-Carrier_1 | Antennae_7-Carrier_2 | Antennae_7-Carrier_3 | Antennae_7-Carrier_4 |
| Antennae_8-Carrier_1 | Antennae_8-Carrier_2 | Antennae_8-Carrier_3 | Antennae_8-Carrier_4 |
Table 4
As shown in Fig. 4， the crossbar module provides the switch function to assign the data samples from CPRI into respective antennae process chain. The package format information has been transferred to RRH by other channel.
Any CPRI container can be routed to any antennae container：
i. CPRI-X transfers packet continuously. The data sample at same packet spot combines into one container.
ii. It only spends 64 cycles to transfer one packet from the CPRI-X to Antennae-x/x side.
iii. CPRI-X only ejects one data sample at one cycle. 4 data samples must transfer synchronously.
iv. Antennae-x/x only accepts one data sample at one cycle.
The CPRI-X is an exemplary example of ingress and the antennae is an exemplary example of egress， thus the data samples transferred from the CPRI to the antennae constitutes a multi-ingress and multi-egress scenario.
With reference to Fig. 4， every CPRI-X and Antennae-x/x only loads 64 data samples. Herein two Antennae are combined into one group for the equipotent between CPRI-Lane and antennae process chain. Thus the CPRI lane number is 4 and antennae group number is 4 too.
A data matrix to be transferred is shown as below：
And the first 4 transfer matrixes are shown as below：
According to the above 4 transfer matrix， the corresponding routing sequences are shown in the above Table
Fig. 5 exemplarily shows the function blocks of the cross module. Referring to Fig. 5， source represents the ingress and sink represents the egress.
The transfer sequence defines to get which antennae data sample from respective CPRI-Lane.
All data sample deposit in source memory and have their identify address. Source and sink are the memory with the depth of 64.
Herein， the route tables respectively at source， MUX and sink are source table， mux table and sink table. Each source has its source table which designates where to get the data sample from the source cell. Each sink has its mux table， and the mux table designates where the sink select the data sample from the source. Each sink has its sink table which designates where the sink put the data sample into the sink cell.
It spends 64 times to move all data samples from source (CPRI Lane)
to sink (Antennae) .
It has three steps to move one data sample from source (CPRI Lane) to sink (Antennae) .
1) A CPRI Lane gets the data sample from a memory address where the source table designates；
2) An Antennae group selects the data sample which the mux table designates；
3) The Antennae group puts the data sample to a memory address where the sink table designates.
Following steps direct how to match the transfer sequence and the route table group.
1) Ascertain which antennae data sample to be retrieved according to a transfer sequence. Search the designated antennae data sample and get the retrieving address in source. The retrieving address is stored in the source table.
2) Ascertain the source and sink according to the transfer sequence. Save the source identifier into the sink’s mux table. Search the empty space in sink’s memory to get the saving address. The saving address is stored in the sink’s sink table.
3) Repeat the above step 1) and step 2) till all data samples routed from source memory into sink memory.
It should be noted that the present invention may be implemented in software or a combination of software and hardware； for example， it may be implemented by an ASIC (Application Specific Integrated Circuit) ， a general-purpose computer， or any other similar hardware devices.
The software program of the present invention may be executed by a processor to implement the above steps or functions. Likewise， the software program of the present invention (including relevant data structure) may be
stored in a computer readable recording medium， for example， a RAM memory， a magnetic or optical driver， or a floppy disk， and other similar devices. Besides， some steps or functions of the present invention may be implemented by hardware， for example， a circuit cooperating with a processor to execute various functions or steps.
Additionally， a portion of the present invention may be applied as a computer program product， for example， a computer program instruction， which， may invoke or provide a method and/or technical solution according to the present invention through operations of the computer when executed by the computer. Further， the program instruction invoking the method of the present invention may be stored in a fixed or mobile recording medium， and/or transmitted through broadcast or data flow in other signal bearer media， and/or stored in a working memory of a computer device which operates based on the program instruction. Here， one embodiment according to the present invention comprises an apparatus comprising a memory for storing a computer program instruction and a processor for executing the program instruction， wherein when the computer program instruction is executed by the processor， the apparatus is triggered to run the methods and/or technical solutions according to a plurality of embodiments of the present invention.
To those skilled in the art， it is apparent that the present invention is not limited to the details of the above exemplary embodiments， and the present invention may be implemented with other embodiments without departing from the spirit or basic features of the present invention. Thus， in any way， the embodiments should be regarded as exemplary， not limitative； the scope of the present invention is limited by the appended claims instead of the above description， and all variations intended to fall into the meaning and scope of equivalent elements of the claims should be covered within the present invention. No reference signs in the claims should be regarded as limiting of
the involved claims. Besides， it is apparent that the term “comprise” does not exclude other units or steps， and singularity does not exclude plurality. A plurality of units or modules stated in a system claim may also be implemented by a single unit or module through software or hardware. Terms such as the first and the second are used to indicate names， but do not indicate any particular sequence.
Claims (9)
- A method for determining route information of intersect parallel data between multi-ingress and multi-egress，wherein the number of ingress， egress and MUX are all N， each ingress connects to all the MUXes and each MUX connects to one egress， and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes；wherein the method comprises the following step：-generating a route-table group based on data transfer sequences between the multi-ingress and multi-egress， wherein the route-table group includes a set of route-table for each ingress to indicate the retrieVing address of data samples to be transferred， a set of route-table for each egress to indicate the data samples selected from those transferred from all the ingresses， and a set of route-table for each egress to indicate the saving address of the selected data samples.
- The method of claim 1， wherein the method further comprises：-predefining a route-table group， wherein the predefined route-table group includes a set of predefined route-table for each ingress to indicate the retrieVing address of data to be transferred， aset of predefined route-table for each egress to indicate the data samples selected from those transferred from all the ingresses， and a set of predefined route-table for each egress to indicate the saving address of the selected data samples；wherein the generating step further comprises：-generating a current route-table group by adjusting the predefined route-table group， based on the data transfer sequences between the multi-ingress and multi-egress.
- A switch device for intersect parallel data between multi-ingress and multi-egress， the switch device comprises multiple ingresses， multiple egresses， and multiple MUX between the multi-ingress and multi-egress，wherein the number of ingress，egress and MUX are all N，each ingress connects to all the MUXes and each MUX connects to one egress，and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes；wherein in the transfer of a data sequence，each ingress is configured to retrieve data to be transferred according to a route-table of the ingress which indicates the retrieVing address of the data，and transfer the retrieved data to all the MUX；each MUX is configured to transfer the data receiVed from an ingress to a corresponding egress according to a route-table of the MUX which indicates the destination egress corresponding to an ingress transferring the retrieved data；each egress is configured to save the data receiVed from a corresponding MUX according to a route-table which indicates the saving address of the receiVed data.
- The Switch device of claim 3，wherein the switch device is configured to：-generate a route-table group based on data transfer sequences between the multi-ingress and multi-egress，wherein the route-table group includes a set of route-table for each ingress to indicate the retrieVing address of data to be transferred，a set of route-table for each egress to indicate the data samples selected from those transferred from all the ingresses，and a set of route-table for each egress to indicate the saving address of the selected data samples.
- The switch device of claim 3，wherein the switch device is configured to：-predefine a route-table group，wherein the predefined route-table group includes a set of predefined route-table for each ingress to indicate the retrieVing address of data to be transferred，a set of predefined route-table for each egress to indicate the data samples selected from those transferred from all the ingresses，and a set of predefined route-table for each egress to indicate the saving address of the selected data samples；-generate a current route-table group by adjusting the predefined route-table group，based on the data transfer sequences between the multi-ingress and multi-egress.
- A device for determining route information of intersect parallel data between multi-ingress and multi-egress，wherein the number of ingress，egress and MUX are all N，each ingress connects to all the MUXes and each MUX connects to one egress，and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes；wherein the device is configured to：-generate a route-table group based on data transfer sequences between the multi-ingress and multi-egress，wherein the route-table group includes a set of route-table for each ingress to indicate the retrieVing address of data to be transferred，a set of route-table for each egress to indicate the data samples selected from those transferred from all the ingresses，and a set of route-table for each egress to indicate the saving address of the selected data samples.
- The device of claim 6，wherein the device is further configured to：-predefine a route-table group，wherein the predefined route-table group includes a set of predefined route-table for each ingress to indicate the retrieVing address of data to be transferred，a set of predefined route-table foreach egress to indicate the data samples selected from those transferred from all the ingresses，and a set of predefined route-table for each egress to indicate the saving address of the selected data samples；wherein the operation of generate a route-table group is further comprises：-generate a current route-table group by adjusting the predefined route-table group，based on the data transfer sequences between the multi-ingress and multi-egress.
- A computer-readable medium，the computer readable medium containing computer code，when executed by a Switch device comprising multiple ingresses，multiple egresses，and multiple MUX between the multi-ingress and multi-egress，wherein the number of ingress，egress and MUX are all N，each ingress connects to all the MUX and each MUX connects to one egress，and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes；wherein the computer-readable medium is operable to cause the switch device to perform the following step：-generate a route-table group based on data transfer sequences between the multi-ingress and multi-egress，wherein the route-table group includes a set of route-table for each ingress to indicate the retrieVing address of data to be transferred，a set of route-table for each egress to indicate the data samples selected from those transferred from all the ingresses，and a set of route-table for each egress to indicate the saving address of the selected data samples.
- A computer program，when executed by a switch device comprising multiple ingresses，multiple egresses，and multiple MUX between the multi-ingress and multi-egress，wherein the number of ingreSS，egress and MUX are all N，each ingress connects to all the MUX and each MUX connects to one egress，and data transfer sequences from the multi-ingress to the multi-egress are N*N matrixes；wherein the computer program is operable to cause the switch device to perform the following step：-generate a route-table group based on data transfer sequences between the multi-ingress and multi-egress，wherein the route-table group includes a set of route-table for each ingress to indicate the retrieVing address of data to be transferred，a set of route-table for each egress to indicate the data samples selected from those transferred from all the ingresses，and a set of route-table for each egress to indicate the saving address of the selected data samples.
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| PCT/CN2014/088026 WO2016049903A1 (en) | 2014-09-30 | 2014-09-30 | Method and apparatus for intersect parallel data between multi-ingress and multi-egress |
| CN201480082374.0A CN107078945B (en) | 2014-09-30 | 2014-09-30 | Method and apparatus for cross-parallel data between multiple entries and multiple exits |
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| PCT/CN2014/088026 WO2016049903A1 (en) | 2014-09-30 | 2014-09-30 | Method and apparatus for intersect parallel data between multi-ingress and multi-egress |
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