WO2016163585A1 - Method of manufacturing cap substrate, method of manufacturing mems device using same, and mems device - Google Patents

Method of manufacturing cap substrate, method of manufacturing mems device using same, and mems device Download PDF

Info

Publication number
WO2016163585A1
WO2016163585A1 PCT/KR2015/004919 KR2015004919W WO2016163585A1 WO 2016163585 A1 WO2016163585 A1 WO 2016163585A1 KR 2015004919 W KR2015004919 W KR 2015004919W WO 2016163585 A1 WO2016163585 A1 WO 2016163585A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating layer
manufacturing
cap substrate
silicon
silicon trench
Prior art date
Application number
PCT/KR2015/004919
Other languages
French (fr)
Korean (ko)
Inventor
서평보
이종성
Original Assignee
주식회사 스탠딩에그
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 스탠딩에그 filed Critical 주식회사 스탠딩에그
Publication of WO2016163585A1 publication Critical patent/WO2016163585A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Definitions

  • the present invention relates to a method of manufacturing a cap substrate, a method of manufacturing a MEMS device using the same, and a MEMS device. More specifically, the hole resistance is minimized by using a through silicon via process in the form of a roof. It is related with the manufacturing method of a cap substrate, the manufacturing method of a MEMS apparatus using the same, and a MEMS apparatus which can be used.
  • TSV Through Silicon Via
  • TSV Various technologies of TSV can be classified into frontend, middle, backend TSV, etc.
  • the front-end TSV process which is usually performed at the beginning of the process, mainly uses a polysilicon process.
  • the polysilicon TSV process is described as a pattern forming process for via holes in a silicon wafer, a through silicon etching process, an oxidation process for insulating silicon and via holes, and a lower silicon.
  • Such conventional MEMS structures must detect very small characteristic values and also transmit electrical signals through the wiring, so signal reduction due to the wiring resistance to be transmitted should be minimized.
  • the conventional polysilicon TSV process has a limitation in increasing the hole size because it is required to grow and fill all the polysilicon inside the TSV holes.
  • the inability to increase the TSV hole size is a technical limitation that cannot solve the electrical signal reduction caused by the resistance that the TSV size is not large.
  • Patent Document 1 Republic of Korea Patent No. 1471190 (registered on Dec. 3, 2014), manufacturing method of MEMS structure
  • the present invention has been made to solve the above problems, and the present invention provides a method for manufacturing a cap substrate and a MEMS device using the same, which can minimize hole resistance using a double through silicon via process. It is an object to provide a manufacturing method and a MEMS device.
  • a cap substrate comprising: depositing an upper insulating layer and a lower insulating layer on upper and lower surfaces of a silicon substrate; Photo patterning is performed on the insulating layer on any one of the upper insulating layer and the lower insulating layer by using photoresist, and in the photo patterning step, the upper surface in the form of one or more closed loops Removing the insulating layer to expose one surface of the silicon substrate in the form of one or more closed loops; Performing silicon etching on the photo patterned region to form a silicon trench; Allowing a first insulating layer to be formed inside the silicon trench; Growing a conductive material (eg, polysilicon) including the inside of the silicon trench in which the first insulating layer is formed, and filling the inside of the silicon trench with the polysilicon; Removing unnecessary portions of the polysilicon; Removing at least one of the one or more closed loops of the one or more closed loops, the insulating layer on the
  • the insulating layer in the step of depositing the top insulating layer and the bottom insulating layer and the step of allowing the first insulating layer to be formed inside the silicon trench is preferably formed by using oxidation (oxidation).
  • CMP chemical mechanical polishing
  • the metal layer is deposited so that the insulating layer on the one surface is removed and the metal layer is deposited so that the polysilicon in the silicon trench contacts the metal layer.
  • a photo process a metal layer etching process and a photo resist removal process.
  • the method may further include forming a cavity on one side of the insulating layer on one surface.
  • the manufacturing method of the MEMS device using the cap substrate manufacturing method according to the second embodiment of the present invention preparing a cap substrate using the cap substrate manufacturing method described above; Preparing a MEMS structure substrate comprising a MEMS structure; Bonding the cap substrate and the MEMS structure substrate; Thinning the cap substrate to remove the other surface of the cap substrate such that polysilicon inside the silicon trench of the cap substrate is exposed to the outside; Forming a second insulating layer on the thinning surface of the thinned cap substrate; Removing the second insulating layer on the closed loop and the second insulating layer inside the closed loop opposite the first bonding portion of the at least one closed loop on which the first bonding portion is formed; And forming a second bonding portion covering the top of the removed Perupe and contacting the polysilicon inside the silicon trench.
  • the method may further include connecting a solder ball to one side of the second bonding part.
  • the MEMS device according to the third embodiment of the present invention is manufactured using the above-described method for manufacturing the MEMS device.
  • the conventional polysilicon TSV process uses polysilicon inside TSV holes. Because it is necessary to grow and fill all the holes, there is a limit to increasing the hole size, and the inability to increase the TSV hole size is a technical problem that cannot solve the electrical signal reduction caused by the resistance that may be caused by the small TSV size. Although the cause of the limitation, in the present invention, through-through vias in the form of a loop can be used to minimize the hole resistance without increasing the hole size.
  • 1 to 5 is a process chart for explaining a cap substrate manufacturing method according to an embodiment of the present invention.
  • FIGS. 6 to 9 are process diagrams for explaining a method for manufacturing a MESMS device having a cap substrate manufactured by a cap substrate manufacturing method according to a preferred embodiment of the present invention shown in FIGS.
  • 1 to 5 are process charts for explaining the cap substrate manufacturing method according to a preferred embodiment of the present invention.
  • the cap substrate according to the first embodiment of the present invention deposits the upper insulating layer 20 and the lower insulating layer on the upper and lower surfaces of the silicon substrate 10.
  • the insulating layer in the step of depositing the upper insulating layer 20 and the lower insulating layer is preferably formed using oxidation (oxidation).
  • FIG. 1 an insulating layer on any one surface of the upper insulating layer 20 and the lower insulating layer (in FIG. 1, a case in which the upper insulating layer 20 is an insulating layer on one surface) is illustrated.
  • Photo patterning is performed using a photoresist.
  • the photo patterning here is patterning for forming the silicon TSV to be described below.
  • the top insulating layer is removed in at least one closed loop form to form a silicon TSV so that one surface of the silicon substrate is exposed in at least one closed loop form. Steps.
  • silicon etching is performed on the photo patterned region to form a silicon trench 40.
  • the silicon trench 40 herein preferably has an etching depth of about 100 to 200 microns. Etching utilizes photoresist application, etching, photoresist removal and cleaning processes.
  • the first insulating layer 21 is formed in the silicon trench 40.
  • the insulating layer in the step of allowing the first insulating layer 20 to be formed in the silicon trench is preferably formed using oxidation.
  • the conductive material 50 is grown to include the inside of the silicon trench 40 on which the first insulating layer 21 is formed, and thus the inside of the silicon trench 40 is electrically conductive. It is filled with the material (50).
  • the conducting material herein may be, for example, polysilicon, tungsten, titanium, tin nitride, aluminum or germanium.
  • CMP chemical mechanical polishing
  • the insulating layer 20 on the one surface inside the closed loop is removed.
  • the first bonding portion 70 covering the top of the stripped insulation layer 20 is contacted with the polysilicon 50 inside the silicon trench. Form.
  • the insulating layer 20 on one surface is removed through a photoresist pattern coating, an insulating layer removal, a photoresist removal, and a washing process.
  • the forming of the first bonding part 70 may include depositing the metal layer (Al or Sn, etc.) so as to cover the top of the stripped insulating layer of the insulating layer, and forming polysilicon in the silicon trench.
  • the metal layer may be contacted through a photo process for forming a pattern, a metal layer etching process, and a photo resist removal process.
  • the method may further include forming a cavity 80 on one side of the insulating layer on one surface.
  • the cavity is formed through a photo process for forming the cavity, a silicon etching process of the cavity region, and a photo resist removal process.
  • FIGS. 6 to 9 are process drawings for explaining a method of manufacturing a MESMS device having a cap substrate manufactured through a cap substrate manufacturing method according to a preferred embodiment of the present invention shown in FIGS. 1 to 5. .
  • a cap substrate using the cap substrate manufacturing method described in the first embodiment is prepared, and a MEMS structure After preparing a MEMS structure substrate including a, the cap substrate and the MEMS structure substrate is bonded.
  • the thinning of the cap substrate is performed to remove the other surface of the cap substrate so that the polysilicon 50 inside the silicon trench of the cap substrate is exposed to the outside.
  • a second insulating layer is formed on the thinning surface of the thinned cap substrate.
  • the second insulating layer may be formed using an oxidation process.
  • the photo process may be performed through a photo process, a second insulating layer etching process, a photoresist removing process, and a cleaning process for connecting the TSV pattern.
  • a second bonding part 71 is formed to cover the top of the removed tupe and contact the polysilicon 50 inside the silicon trench.
  • the second bonding part 71 may be formed through deposition of Al or the like. It can be made through a photo process and an etching process for forming a pad for the wiring and the second bonding portion.
  • the method may further include connecting a solder ball to one side of the second bonding part 71.
  • the MEMS device according to the third embodiment of the present invention may be manufactured using the manufacturing method of the MEMS device according to the first and second embodiments.

Abstract

The present invention provides a method of manufacturing a cap substrate, a method of manufacturing a MEMS device using same, and a MEMS device. The method of manufacturing a cap substrate comprises the steps of: depositing a top surface insulating layer and a bottom surface insulating layer on the top surface and the bottom surface of a silicon substrate; photo patterning by using a photoresist on one of the surface insulating layers from among the top surface insulating layer and the bottom surface insulating layer, included in the photo patterning step is a step of the top surface insulating layer being removed in the form of one or more of a closed loop and one surface of the silicon substrate being exposed in the form of one or more of a closed loop; forming a silicon trench by conducting silicon etching on the photo patterned region; forming a first insulating layer inside the silicon trench; growing a conductive material (such as polysilicon) including the inside of the silicon trench in which the insulating layer is formed, and filling the inside of the silicon trench with polysilicon; removing an unneeded portion of the polysilicon; removing the insulating layer on the one surface inside at least one or more closed loop from the one or more closed loops; and covering the top of the closed loop from which the insulating layer on the one surface has been removed, and forming a first bonding portion for contacting the polysilicon inside the silicon trench.

Description

캡 기판의 제조 방법, 이를 이용한 ＭＥＭＳ 장치의 제조 방법, 및 ＭＥＭＳ 장치Method for manufacturing cap substrate, method for manufacturing MES apparatus using the same, MES apparatus
본 발명은 캡 기판의 제조 방법, 이를 이용한 MEMS 장치의 제조 방법, 및 MEMS 장치에 관한 것으로, 좀 더 구체적으로는, 패루프 형태의 쓰루 실리콘 비어(through silicon via) 공정을 이용하여 홀 저항을 최소화하는 것이 가능한, 캡 기판의 제조 방법, 이를 이용한 MEMS 장치의 제조 방법, 및 MEMS 장치에 관한 것이다. The present invention relates to a method of manufacturing a cap substrate, a method of manufacturing a MEMS device using the same, and a MEMS device. More specifically, the hole resistance is minimized by using a through silicon via process in the form of a roof. It is related with the manufacturing method of a cap substrate, the manufacturing method of a MEMS apparatus using the same, and a MEMS apparatus which can be used.
반도체 및 MEMS 기술이 집적화되어 가면서 실리콘 패키지 기술도 다양하게 발전해 가고 있다. 그 중에서 TSV(Through Silicon Via) 기술을 이용한 패키지 기술은 MEMS 구조물의 크기를 증가시키지 않고 실리콘을 관통하여 배선을 연결할 수 있어 다양하게 연구되고 발전하고 있는 기술이다. As semiconductor and MEMS technologies are integrated, various silicon package technologies are being developed. Among them, package technology using TSV (Through Silicon Via) technology is a technology that has been variously researched and developed as it can connect wiring through silicon without increasing the size of the MEMS structure.
TSV의 다양한 기술은 프런트엔드(frontend), 미들(middle), 백엔드(backend) TSV 등으로 구분할 수 있으며, 보통 공정 초기에 이루어지는 프런트엔드 TSV 공정은 폴리실리콘 공정을 주로 이용한다. Various technologies of TSV can be classified into frontend, middle, backend TSV, etc. The front-end TSV process, which is usually performed at the beginning of the process, mainly uses a polysilicon process.
폴리실리콘 TSV 공정에 대해서 간락하게 설명하면, 실리콘 웨이퍼에 비어 홀(via hole)을 위한 패턴 형성 공정, 쓰루 실리콘(through silicon) 에칭 공정, 실리콘과 비어 홀의 절연을 위한 절연 공정(oxidation) 및 실리콘 하부와 실리콘 상부를 연결하는 폴리실리콘 성장 공정, 그리고 성장된 폴리실리콘을 평탄화하는 폴리 CMP 공정이 있으며, 후속 공정으로 TSV 폴리실리콘의 최종 연결을 위한 배선 및 PAD 형성 공정 또는 솔더볼(solder ball)로 마무리할 수 있다.Briefly, the polysilicon TSV process is described as a pattern forming process for via holes in a silicon wafer, a through silicon etching process, an oxidation process for insulating silicon and via holes, and a lower silicon. Polysilicon growth process connecting silicon and silicon top, and poly CMP process to planarize the grown polysilicon, followed by wiring and PAD formation process or solder ball for final connection of TSV polysilicon. Can be.
이와 같은 종래의 MEMS 구조물은 매우 작은 특성값을 검출하고 또한 배선을 통하여 전기적 신호를 전달해야 하기 때문에, 전달되는 배선 저항에 의한 신호 감소를 최소화하여야 한다. 그런데, 종래의 폴리실리콘 TSV 공정은 TSV 홀 내부에 폴리 실리콘을 성장시켜 모두 채워야 하기 때문에 홀 크기(hole size)를 크게 하는데에는 한계가 있다. TSV 홀 크기를 크게 할 수 없다는 것은 TSV 크기가 크지 않음으로써 발생할 수 있는 저항에 의한 전기적 신호 감소를 해결할 수 없는 기술적인 한계의 원인이 된다. Such conventional MEMS structures must detect very small characteristic values and also transmit electrical signals through the wiring, so signal reduction due to the wiring resistance to be transmitted should be minimized. However, the conventional polysilicon TSV process has a limitation in increasing the hole size because it is required to grow and fill all the polysilicon inside the TSV holes. The inability to increase the TSV hole size is a technical limitation that cannot solve the electrical signal reduction caused by the resistance that the TSV size is not large.
[선행기술문헌][Preceding technical literature]
[특허문헌][Patent Documents]
(특허문헌 1) 대한민국 특허 제1471190호 (2014.12.03 등록), 멤즈 구조체의 제조 방법 (Patent Document 1) Republic of Korea Patent No. 1471190 (registered on Dec. 3, 2014), manufacturing method of MEMS structure
본 발명은 상술한 문제점을 해결하기 위하여 창출된 것으로, 본 발명은 더블 쓰루 실리콘 비어(double through silicon via) 공정을 이용하여 홀 저항을 최소화하는 것이 가능한, 캡 기판의 제조 방법, 이를 이용한 MEMS 장치의 제조 방법, 및 MEMS 장치를 제공하는 것을 목적으로 한다. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the present invention provides a method for manufacturing a cap substrate and a MEMS device using the same, which can minimize hole resistance using a double through silicon via process. It is an object to provide a manufacturing method and a MEMS device.
상기의 목적을 달성하기 위한 본 발명의 제 1 실시예에 따른 캡 기판은, 실리콘 기판의 상면 및 하면에 상면 절연층 및 하면 절연층을 증착시키는 단계; 상기 상면 절연층 및 상기 하면 절연층 중 어느 일면의 절연층에 대해서, 포토 레지스트를 이용하여 포토 패터닝을 하는 단계로서, 상기 포토 패터닝을 하는 단계에서는, 하나 이상의 폐루프(closed loop) 형태로 상기 상면 절연층이 제거되어, 상기 실리콘 기판의 일면이 하나 이상의 폐루프 형태로 노출되도록 하는 단계를 포함하고; 상기 포토 패터닝된 영역에 대해서 실리콘 에칭을 실행하여 실리콘 트렌치(trench)를 형성하는 단계; 상기 실리콘 트렌치 내부에 제 1 절연층이 형성되도록 하는 단계; 상기 제 1 절연층이 형성된 상기 실리콘 트렌치 내부를 포함하여 도전 물질(예 : 폴리실리콘(polysilicon))을 성장시켜서, 상기 실리콘 트렌치 내부를 상기 폴리실리콘으로 채우는 단계; 상기 폴리실리콘 중 불필요한 부분을 제거하는 단계; 상기 하나 이상의 폐루프 중 적어도 하나 이상의 폐루프에 대해서, 그 폐루프 내부의 상기 일면의 절연층을 제거하는 단계; 및 상기 일면의 절연층이 제거된 페루프 위를 덮으며, 상기 실리콘 트렌치 내부의 폴리실리콘과 접촉하는 제 1 본딩부를 형성하는 단계;를 포함한다. According to a first aspect of the present invention, there is provided a cap substrate comprising: depositing an upper insulating layer and a lower insulating layer on upper and lower surfaces of a silicon substrate; Photo patterning is performed on the insulating layer on any one of the upper insulating layer and the lower insulating layer by using photoresist, and in the photo patterning step, the upper surface in the form of one or more closed loops Removing the insulating layer to expose one surface of the silicon substrate in the form of one or more closed loops; Performing silicon etching on the photo patterned region to form a silicon trench; Allowing a first insulating layer to be formed inside the silicon trench; Growing a conductive material (eg, polysilicon) including the inside of the silicon trench in which the first insulating layer is formed, and filling the inside of the silicon trench with the polysilicon; Removing unnecessary portions of the polysilicon; Removing at least one of the one or more closed loops of the one or more closed loops, the insulating layer on the one surface inside the closed loop; And forming a first bonding portion covering the one-sided insulating layer on which the insulating layer is removed and in contact with polysilicon in the silicon trench.
또한, 상기 상면 절연층 및 하면 절연층을 증착시키는 단계 및 상기 실리콘 트렌치 내부에 제 1 절연층이 형성되도록 하는 단계에서의 절연층은 산화(oxidation)을 이용하여 형성하는 것이 바람직하다. In addition, the insulating layer in the step of depositing the top insulating layer and the bottom insulating layer and the step of allowing the first insulating layer to be formed inside the silicon trench is preferably formed by using oxidation (oxidation).
또한, 상기 폴리실리콘 중 불필요한 부분을 제거하는 단계에서는, 화학적 기계적 연마 공정(CMP, Chemical Mechanical polishing)을 이용하는 것이 바람직하다. In addition, in the step of removing unnecessary portions of the polysilicon, it is preferable to use a chemical mechanical polishing (CMP).
또한, 상기 제 1 본딩부를 형성하는 단계는, 상기 일면의 절연층이 제거된 페루프 위를 덮도록 상기 금속층이 증착되고, 상기 실리콘 트렌치 내부의 폴리실리콘과 상기 금속층이 접촉되도록 하는, 패턴 형성을 위한 포토 공정, 금속층 에칭 공정 및 포토 레지스트 제거 공정을 통해서 이루어질 수 있다. In the forming of the first bonding part, the metal layer is deposited so that the insulating layer on the one surface is removed and the metal layer is deposited so that the polysilicon in the silicon trench contacts the metal layer. Through a photo process, a metal layer etching process and a photo resist removal process.
또한, 상기 일면의 절연층의 일측에 캐비티(cavity)를 형성하는 단계를 더 포함할 수 있다. In addition, the method may further include forming a cavity on one side of the insulating layer on one surface.
한편, 본 발명의 제 2 실시예에 따른 캡 기판의 제조 방법을 이용한 MEMS 장치의 제조 방법은, 상술한 캡 기판 제조 방법을 이용한 캡 기판를 준비하는 단계; MEMS 구조물을 포함하는 MEMS 구조물 기판을 준비하는 단계; 상기 캡 기판 및 상기 MEMS 구조물 기판을 본딩하는 단계; 상기 캡 기판의 상기 실리콘 트렌치 내부의 폴리실리콘이 외부로 노출되도록 상기 캡 기판의 타면을 제거하는 상기 캡 기판의 씬닝(thinning) 단계; 상기 씬닝된 캡 기판의 씬닝 면에 대해서, 제 2 절연층을 형성하는 단계; 상기 제 1 본딩부가 형성된 하나 이상의 폐루프의 상기 제 1 본딩부의 반대쪽의 그 폐루프 내부의 상기 제 2 절연층 및 상기 폐루프 상의 제 2 절연층을 제거하는 단계; 및 상기 제 2 절연층이 제거된 페루프 위를 덮으며, 상기 실리콘 트렌치 내부의 폴리실리콘과 접촉하는 제 2 본딩부를 형성하는 단계;를 포함한다. On the other hand, the manufacturing method of the MEMS device using the cap substrate manufacturing method according to the second embodiment of the present invention, preparing a cap substrate using the cap substrate manufacturing method described above; Preparing a MEMS structure substrate comprising a MEMS structure; Bonding the cap substrate and the MEMS structure substrate; Thinning the cap substrate to remove the other surface of the cap substrate such that polysilicon inside the silicon trench of the cap substrate is exposed to the outside; Forming a second insulating layer on the thinning surface of the thinned cap substrate; Removing the second insulating layer on the closed loop and the second insulating layer inside the closed loop opposite the first bonding portion of the at least one closed loop on which the first bonding portion is formed; And forming a second bonding portion covering the top of the removed Perupe and contacting the polysilicon inside the silicon trench.
또한, 제 2 본딩부의 일측에 솔더볼(solder ball)을 연결하는 단계를 더 포함할 수 있다. The method may further include connecting a solder ball to one side of the second bonding part.
한편, 본 발명의 제 3 실시예에 따른 MEMS 장치는, 상술한 MEMS 장치의 제조 방법을 이용하여 제조된다. On the other hand, the MEMS device according to the third embodiment of the present invention is manufactured using the above-described method for manufacturing the MEMS device.
본 발명에 따른 캡 기판의 제조 방법, 이를 이용한 ＭＥＭＳ 장치의 제조 방법, 및 ＭＥＭＳ 장치에 의하면,According to the manufacturing method of the cap substrate which concerns on this invention, the manufacturing method of MEMS apparatus using the same, and MEMS apparatus,
첫째, MEMS 구조물은 매우 작은 특성값을 검출하고 또한 배선을 통하여 전기적 신호를 전달해야 하기 때문에, 전달되는 배선 저항에 의한 신호 감소를 최소화하여야 하나, 종래의 폴리실리콘 TSV 공정은 TSV 홀 내부에 폴리 실리콘을 성장시켜 모두 채워야 하기 때문에 홀 크기(hole size)를 크게 하는데 한계가 있고, TSV 홀 크기를 크게 할 수 없다는 것은 TSV 크기가 크지 않음으로써 발생할 수 있는 저항에 의한 전기적 신호 감소를 해결할 수 없는 기술적인 한계의 원인이 되었으나, 본 발명에서는, 패루프 형태의 쓰루 실리콘 비어(through silicon via) 공정을 이용하여, 홀 크기를 크게 하지 않고도 홀 저항을 최소화하는 것이 가능하게 된다. First, since MEMS structures must detect very small characteristic values and also transmit electrical signals through the wiring, signal reduction due to transmitted wiring resistance should be minimized. However, the conventional polysilicon TSV process uses polysilicon inside TSV holes. Because it is necessary to grow and fill all the holes, there is a limit to increasing the hole size, and the inability to increase the TSV hole size is a technical problem that cannot solve the electrical signal reduction caused by the resistance that may be caused by the small TSV size. Although the cause of the limitation, in the present invention, through-through vias in the form of a loop can be used to minimize the hole resistance without increasing the hole size.
둘째, 홀 저항을 최소화하는 것이 가능하여, 종래 MEMS 구조물에서 저항에 의해 전기적 신호가 감소하는 것을 근본적으로 해결하는 것이 가능하다. Secondly, it is possible to minimize the Hall resistance, which essentially solves the reduction of the electrical signal by the resistance in conventional MEMS structures.
셋째, MEMS 구조물의 크기를 증가시키지 않고도, 간단한 공정만으로 개선된 성능을 제공하는 것이 가능하여, 제조 단가를 절감할 수 있으며, 제품의 경쟁 우위를 확보하는 것이 가능하다. Third, it is possible to provide improved performance with a simple process without increasing the size of the MEMS structure, thereby reducing the manufacturing cost and securing a competitive advantage of the product.
도 1 내지 도 5는 본 발명의 바람직한 실시예에 따른 캡 기판 제조 방법을 설명하기 위한 공정도, 1 to 5 is a process chart for explaining a cap substrate manufacturing method according to an embodiment of the present invention,
도 6 내지 도 9는 도 1 내지 도 5에서 도시한 본 발명의 바람직한 실시예에 따른 캡 기판 제조 방법을 통해서 제조된 캡 기판을 가지고, MESMS 장치를 제조하는 방법에 대해서 설명하기 위한 공정도이다. 6 to 9 are process diagrams for explaining a method for manufacturing a MESMS device having a cap substrate manufactured by a cap substrate manufacturing method according to a preferred embodiment of the present invention shown in FIGS.
이하 첨부된 도면을 참조하면서 본 발명에 따른 바람직한 실시예를 상세히 설명하기로 한다. 이에 앞서, 본 명세서 및 청구범위에 사용된 용어나 단어는 통상적이거나 사전적인 의미로 한정해서 해석되어서는 아니 되며, 발명자는 그 자신의 발명을 가장 최선의 방법으로 설명하기 위해 용어의 개념을 적절하게 정의할 수 있다는 원칙에 입각하여, 본 발명의 기술적 사상에 부합하는 의미와 개념으로 해석되어야만 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the present specification and claims should not be construed as being limited to the common or dictionary meanings, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that it can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention.
따라서, 본 명세서에 기재된 실시예와 도면에 도시된 구성은 본 발명의 가장 바람직한 일 실시예에 불과할 뿐이고 본 발명의 기술적 사상을 모두 대변하는 것은 아니므로, 본 출원시점에 있어서 이들을 대체할 수 있는 다양한 균등물과 변형예들이 있을 수 있음을 이해하여야 한다.Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.
(제 1 실시예)(First embodiment)
도 1 내지 도 5는 본 발명의 바람직한 실시예에 따른 캡 기판 제조 방법을 설명하기 위한 공정도이다. 1 to 5 are process charts for explaining the cap substrate manufacturing method according to a preferred embodiment of the present invention.
도 1을 참조하여 설명하면, 본 발명의 제 1 실시예에 따른 캡 기판은, 실리콘 기판(10)의 상면 및 하면에 상면 절연층(20) 및 하면 절연층을 증착시킨다. 여기서, 상기 상면 절연층(20) 및 하면 절연층을 증착시키는 단계에서의 절연층은 산화(oxidation)을 이용하여 형성하는 것이 바람직하다. Referring to FIG. 1, the cap substrate according to the first embodiment of the present invention deposits the upper insulating layer 20 and the lower insulating layer on the upper and lower surfaces of the silicon substrate 10. Here, the insulating layer in the step of depositing the upper insulating layer 20 and the lower insulating layer is preferably formed using oxidation (oxidation).
도 1에 도시된 바와 같이, 상기 상면 절연층(20) 및 상기 하면 절연층 중 어느 일면의 절연층(도 1에서는 상면 절연층(20)이 어느 일면의 절연층인 경우를 예시함)에 대해서, 포토 레지스트를 이용하여 포토 패터닝(photo patterning)을 한다. 즉, 여기서의 포토 패터닝은 이하에서 설명할 실리콘 TSV를 형성을 위한 패터닝이다. As shown in FIG. 1, an insulating layer on any one surface of the upper insulating layer 20 and the lower insulating layer (in FIG. 1, a case in which the upper insulating layer 20 is an insulating layer on one surface) is illustrated. Photo patterning is performed using a photoresist. In other words, the photo patterning here is patterning for forming the silicon TSV to be described below.
다시 말해, 상기 포토 패터닝을 하는 단계에서는, 실리콘 TSV 형성을 위해, 하나 이상의 폐루프(closed loop) 형태로 상기 상면 절연층이 제거되어, 상기 실리콘 기판의 일면이 하나 이상의 폐루프 형태로 노출되도록 하는 단계를 포함한다. In other words, in the photo patterning, the top insulating layer is removed in at least one closed loop form to form a silicon TSV so that one surface of the silicon substrate is exposed in at least one closed loop form. Steps.
다음으로, 도 2에 도시된 바와 같이, 상기 포토 패터닝된 영역에 대해서 실리콘 에칭을 실행하여 실리콘 트렌치(trench)(40)를 형성한다. 여기서의 실리콘 트렌치(40)는 에칭 깊이가 100 내지 200 마이크론 정도로 진행하는 것이 바람직하다. 에칭은 포토 레지스트 도포, 에칭, 포토 레지스트 제거 및 세척(cleaning) 공정을 이용한다. Next, as shown in FIG. 2, silicon etching is performed on the photo patterned region to form a silicon trench 40. The silicon trench 40 herein preferably has an etching depth of about 100 to 200 microns. Etching utilizes photoresist application, etching, photoresist removal and cleaning processes.
여기서의 상기 실리콘 트렌치(40) 내부에 제 1 절연층(21)이 형성되도록 한다. 여기서, 상기 실리콘 트렌치 내부에 제 1 절연층(20)이 형성되도록 하는 단계에서의 절연층은 산화(oxidation)을 이용하여 형성하는 것이 바람직하다. Herein, the first insulating layer 21 is formed in the silicon trench 40. Here, the insulating layer in the step of allowing the first insulating layer 20 to be formed in the silicon trench is preferably formed using oxidation.
다음으로, 도 3에 도시된 바와 같이, 상기 제 1 절연층(21)이 형성된 상기 실리콘 트렌치(40) 내부를 포함하여 도전 물질(50)을 성장시켜서, 상기 실리콘 트렌치(40) 내부를 상기 도전 물질(50)로 채우게 된다. 여기서의 도전 물질(conducting material)은 예를 들어 폴리실리콘(polysilicon), 텅스턴, 티타늄, 틴타늄 나이트라이드, 알루미늄 또는 게르마늄 등일 수 있다. Next, as shown in FIG. 3, the conductive material 50 is grown to include the inside of the silicon trench 40 on which the first insulating layer 21 is formed, and thus the inside of the silicon trench 40 is electrically conductive. It is filled with the material (50). The conducting material herein may be, for example, polysilicon, tungsten, titanium, tin nitride, aluminum or germanium.
다음으로, 상기 폴리실리콘(50) 중 불필요한 부분을 제거하는 단계를 거친다. 여기서, 상기 폴리실리콘 중 불필요한 부분을 제거하는 단계에서는, 화학적 기계적 연마 공정(CMP, Chemical Mechanical polishing)을 이용하는 것이 바람직하다. Next, the unnecessary portion of the polysilicon 50 is removed. Here, in the step of removing the unnecessary portion of the polysilicon, it is preferable to use a chemical mechanical polishing (CMP).
도 3에 도시된 바와 같이, 상기 하나 이상의 폐루프 중 적어도 하나 이상의 폐루프에 대해서, 그 폐루프 내부의 상기 일면의 절연층(20)을 제거한다. As shown in FIG. 3, for at least one of the one or more closed loops, the insulating layer 20 on the one surface inside the closed loop is removed.
도 4 및 도 5에 도시된 바와 같이, 상기 일면의 절연층(20)이 제거된 페루프 위를 덮으며, 상기 실리콘 트렌치 내부의 폴리실리콘(50)과 접촉하는 제 1 본딩부(70)를 형성한다. As shown in FIG. 4 and FIG. 5, the first bonding portion 70 covering the top of the stripped insulation layer 20 is contacted with the polysilicon 50 inside the silicon trench. Form.
여기서, 상기 일면의 절연층(20) 제거는 포토 레지스트 패턴 도포, 절연층 제거, 포토 레지스트 제거 및 세척 공정을 통해서 이루어지는 것이 바람직하다. Here, it is preferable that the insulating layer 20 on one surface is removed through a photoresist pattern coating, an insulating layer removal, a photoresist removal, and a washing process.
여기서, 상기 제 1 본딩부(70)를 형성하는 단계는, 상기 일면의 절연층이 제거된 페루프 위를 덮도록 상기 금속층(Al 또는 Sn 등)이 증착되고, 상기 실리콘 트렌치 내부의 폴리실리콘과 상기 금속층이 접촉되도록 하는, 패턴 형성을 위한 포토 공정, 금속층 에칭 공정 및 포토 레지스트 제거 공정을 통해서 이루어질 수 있다. Here, the forming of the first bonding part 70 may include depositing the metal layer (Al or Sn, etc.) so as to cover the top of the stripped insulating layer of the insulating layer, and forming polysilicon in the silicon trench. The metal layer may be contacted through a photo process for forming a pattern, a metal layer etching process, and a photo resist removal process.
도 5에 도시된 바와 같이, 상기 일면의 절연층의 일측에 캐비티(cavity)(80)를 형성하는 단계를 더 포함할 수 있다. 캐비티 형성은 캐비티 형성을 위한 포토 공정, 캐비티 영역의 실리콘 에칭 공정 및 포토 레지스트 제거 공정 등을 통해서 이루어진다. As shown in FIG. 5, the method may further include forming a cavity 80 on one side of the insulating layer on one surface. The cavity is formed through a photo process for forming the cavity, a silicon etching process of the cavity region, and a photo resist removal process.
(제 2 실시예) (Second embodiment)
한편, 도 6 내지 도 9는 도 1 내지 도 5에서 도시한 본 발명의 바람직한 실시예에 따른 캡 기판 제조 방법을 통해서 제조된 캡 기판을 가지고, MESMS 장치를 제조하는 방법에 대해서 설명하기 위한 공정도이다. 6 to 9 are process drawings for explaining a method of manufacturing a MESMS device having a cap substrate manufactured through a cap substrate manufacturing method according to a preferred embodiment of the present invention shown in FIGS. 1 to 5. .
도 6에 도시된 바와 같이, 본 발명의 제 2 실시예에 따른 캡 기판의 제조 방법을 이용한 MEMS 장치의 제조 방법은, 제 1 실시예에서 설명한 캡 기판 제조 방법을 이용한 캡 기판를 준비하고, MEMS 구조물을 포함하는 MEMS 구조물 기판을 준비한 다음에, 상기 캡 기판 및 상기 MEMS 구조물 기판을 본딩하게 된다. As shown in FIG. 6, in the MEMS device manufacturing method using the cap substrate manufacturing method according to the second embodiment of the present invention, a cap substrate using the cap substrate manufacturing method described in the first embodiment is prepared, and a MEMS structure After preparing a MEMS structure substrate including a, the cap substrate and the MEMS structure substrate is bonded.
도 7에 도시된 바와 같이, 상기 캡 기판의 상기 실리콘 트렌치 내부의 폴리실리콘(50)이 외부로 노출되도록 상기 캡 기판의 타면을 제거하는 상기 캡 기판의 씬닝(thinning) 단계를 실행한다. As shown in FIG. 7, the thinning of the cap substrate is performed to remove the other surface of the cap substrate so that the polysilicon 50 inside the silicon trench of the cap substrate is exposed to the outside.
그리고 나서, 상기 씬닝된 캡 기판의 씬닝 면에 대해서, 제 2 절연층을 형성한다. 여기서, 제 2 절연층은 산화 공정을 이용하여 형성할 수 있다. Then, a second insulating layer is formed on the thinning surface of the thinned cap substrate. Here, the second insulating layer may be formed using an oxidation process.
또한, 도 7에 도시된 바와 같이, 상기 제 1 본딩부(70)가 형성된 하나 이상의 폐루프의 상기 제 1 본딩부의 반대쪽(즉, 기판의 상하에서의 반대쪽)의 그 폐루프 내부의 상기 제 2 절연층 및 상기 폐루프 상의 제 2 절연층을 제거한다. 즉, TSV 패턴 연결을 위한 포토 공정, 제 2 절연층 에칭 공정, 포토 레지스트 제거 공정 및 세척 공정 등을 통해서 이루어질 수 있다. Further, as shown in FIG. 7, the second inside of the closed loop opposite the first bonding portion (ie, opposite the upper and lower sides of the substrate) of the one or more closed loops in which the first bonding portion 70 is formed. The insulating layer and the second insulating layer on the closed loop are removed. That is, the photo process may be performed through a photo process, a second insulating layer etching process, a photoresist removing process, and a cleaning process for connecting the TSV pattern.
다음으로, 도 8에 도시된 바와 같이, 상기 제 2 절연층이 제거된 페루프 위를 덮으며, 상기 실리콘 트렌치 내부의 폴리실리콘(50)과 접촉하는 제 2 본딩부(71)를 형성한다. 예를 들어, Al 등의 증착을 통해서 제 2 본딩부(71)가 형성될 수 있다. 배선 및 제 2 본딩부를 위한 패드(pad) 형성을 위한 포토 공정 및 에칭 공정을 통해서 이루어질 수 있다. Next, as shown in FIG. 8, a second bonding part 71 is formed to cover the top of the removed tupe and contact the polysilicon 50 inside the silicon trench. For example, the second bonding part 71 may be formed through deposition of Al or the like. It can be made through a photo process and an etching process for forming a pad for the wiring and the second bonding portion.
다음으로, 도 9에 도시된 바와 같이, 제 2 본딩부(71)의 일측에 솔더볼(solder ball)을 연결하는 단계를 더 포함할 수 있다. Next, as shown in FIG. 9, the method may further include connecting a solder ball to one side of the second bonding part 71.
(제 3 실시예)(Third embodiment)
도 1 내지 도 9에 도시된 바와 같이, 본 발명의 제 3 실시예에 따른 MEMS 장치는, 제 1 및 제 2 실시예에 따른 MEMS 장치의 제조 방법을 이용하여 제조될 수 있다. As shown in FIGS. 1 to 9, the MEMS device according to the third embodiment of the present invention may be manufactured using the manufacturing method of the MEMS device according to the first and second embodiments.
이상과 같이, 본 발명은 비록 한정된 실시예와 도면에 의해 설명되었으나, 본 발명은 이것에 의해 한정되지 않으며 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 본 발명의 기술 사상과 아래에 기재될 청구범위의 균등 범위 내에서 다양한 수정 및 변형이 가능함은 물론이다.As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

Claims (8)

  1. 실리콘 기판의 상면 및 하면에 상면 절연층 및 하면 절연층을 증착시키는 단계; Depositing a top insulating layer and a bottom insulating layer on the top and bottom surfaces of the silicon substrate;
    상기 상면 절연층 및 상기 하면 절연층 중 어느 일면의 절연층에 대해서, 포토 레지스트를 이용하여 포토 패터닝을 하는 단계로서, 상기 포토 패터닝을 하는 단계에서는, 하나 이상의 폐루프(closed loop) 형태로 상기 상면 절연층이 제거되어, 상기 실리콘 기판의 일면이 하나 이상의 폐루프 형태로 노출되도록 하는 단계를 포함하고; Photo patterning is performed on the insulating layer on any one of the upper insulating layer and the lower insulating layer by using photoresist, and in the photo patterning step, the upper surface in the form of one or more closed loops Removing the insulating layer to expose one surface of the silicon substrate in the form of one or more closed loops;
    상기 포토 패터닝된 영역에 대해서 실리콘 에칭을 실행하여 실리콘 트렌치(trench)를 형성하는 단계; Performing silicon etching on the photo patterned region to form a silicon trench;
    상기 실리콘 트렌치 내부에 제 1 절연층이 형성되도록 하는 단계; Allowing a first insulating layer to be formed inside the silicon trench;
    상기 제 1 절연층이 형성된 상기 실리콘 트렌치 내부를 포함하여 도전 물질(conducting material)을 성장시켜서, 상기 실리콘 트렌치 내부를 상기 도전 물질로 채우는 단계; Growing a conductive material including an inside of the silicon trench in which the first insulating layer is formed, and filling the inside of the silicon trench with the conductive material;
    상기 도전 물질 중 불필요한 부분을 제거하는 단계; Removing unnecessary portions of the conductive material;
    상기 하나 이상의 폐루프 중 적어도 하나 이상의 폐루프에 대해서, 그 폐루프 내부의 상기 일면의 절연층을 제거하는 단계; 및Removing at least one of the one or more closed loops of the one or more closed loops, the insulating layer on the one surface inside the closed loop; And
    상기 일면의 절연층이 제거된 페루프 위를 덮으며, 상기 실리콘 트렌치 내부의 도전 물질과 접촉하는 제 1 본딩부를 형성하는 단계;를 포함하는, Forming a first bonding portion covering the one-sided insulating layer on the one-sided stripped Perupe and contacting a conductive material in the silicon trench.
    캡 기판 제조 방법. Cap substrate manufacturing method.
  2. 제 1 항에 있어서, The method of claim 1,
    상기 상면 절연층 및 하면 절연층을 증착시키는 단계 및 상기 실리콘 트렌치 내부에 제 1 절연층이 형성되도록 하는 단계에서의 절연층은 산화(oxidation)을 이용하여 형성하는, Insulating the upper insulating layer and the lower insulating layer and the insulating layer in the step of allowing the first insulating layer to be formed inside the silicon trench is formed using oxidation (oxidation),
    캡 기판 제조 방법. Cap substrate manufacturing method.
  3. 제 1 항에 있어서, The method of claim 1,
    상기 도전 물질 중 불필요한 부분을 제거하는 단계에서는, 화학적 기계적 연마 공정(CMP, Chemical Mechanical polishing)을 이용하는, In the step of removing the unnecessary portion of the conductive material, using a chemical mechanical polishing (CMP, Chemical Mechanical polishing),
    캡 기판 제조 방법. Cap substrate manufacturing method.
  4. 제 1 항에 있어서, The method of claim 1,
    상기 제 1 본딩부를 형성하는 단계는, Forming the first bonding portion,
    상기 일면의 절연층이 제거된 페루프 위를 덮도록 상기 금속층이 증착되고, 상기 실리콘 트렌치 내부의 도전 물질과 상기 금속층이 접촉되도록 하는, 패턴 형성을 위한 포토 공정, 금속층 에칭 공정 및 포토 레지스트 제거 공정을 통해서 이루어지는, A photo process for forming a pattern, a metal layer etching process, and a photoresist removing process for depositing the metal layer so as to cover the one-side insulating layer on which the insulating layer is removed, and contacting the conductive layer and the metal layer in the silicon trench. Through
    캡 기판 제조 방법. Cap substrate manufacturing method.
  5. 제 1 항에 있어서, The method of claim 1,
    상기 일면의 절연층의 일측에 캐비티(cavity)를 형성하는 단계를 더 포함하는, Further comprising the step of forming a cavity (cavity) on one side of the insulating layer on one surface,
    캡 기판 제조 방법. Cap substrate manufacturing method.
  6. 제 1 항 내지 제 5 항 중 어느 한 항에 기재된 캡 기판 제조 방법을 이용한 캡 기판를 준비하는 단계; Preparing a cap substrate using the cap substrate manufacturing method according to any one of claims 1 to 5;
    MEMS 구조물을 포함하는 MEMS 구조물 기판을 준비하는 단계; Preparing a MEMS structure substrate comprising a MEMS structure;
    상기 캡 기판 및 상기 MEMS 구조물 기판을 본딩하는 단계;Bonding the cap substrate and the MEMS structure substrate;
    상기 캡 기판의 상기 실리콘 트렌치 내부의 도전 물질이 외부로 노출되도록 상기 캡 기판의 타면을 제거하는 상기 캡 기판의 씬닝(thinning) 단계; Thinning the cap substrate to remove the other surface of the cap substrate so that the conductive material inside the silicon trench of the cap substrate is exposed to the outside;
    상기 씬닝된 캡 기판의 씬닝 면에 대해서, 제 2 절연층을 형성하는 단계; Forming a second insulating layer on the thinning surface of the thinned cap substrate;
    상기 제 1 본딩부가 형성된 하나 이상의 폐루프의 상기 제 1 본딩부의 반대쪽의 그 폐루프 내부의 상기 제 2 절연층 및 상기 폐루프 상의 제 2 절연층을 제거하는 단계; 및Removing the second insulating layer on the closed loop and the second insulating layer inside the closed loop opposite the first bonding portion of the at least one closed loop on which the first bonding portion is formed; And
    상기 제 2 절연층이 제거된 페루프 위를 덮으며, 상기 실리콘 트렌치 내부의 도전 물질과 접촉하는 제 2 본딩부를 형성하는 단계;를 포함하는, Forming a second bonding portion covering the removed tuft of the second insulating layer and contacting a conductive material in the silicon trench;
    캡 기판의 제조 방법을 이용한 MEMS 장치의 제조 방법. The manufacturing method of the MEMS apparatus using the manufacturing method of a cap substrate.
  7. 제 6 항에 있어서, The method of claim 6,
    제 2 본딩부의 일측에 솔더볼(solder ball)을 연결하는 단계를 더 포함하는, The method may further include connecting a solder ball to one side of the second bonding part.
    캡 기판의 제조 방법을 이용한 MEMS 장치의 제조 방법. The manufacturing method of the MEMS apparatus using the manufacturing method of a cap substrate.
  8. 제 6 항 또는 제 7 항 중 어느 한 항에 기재된 MEMS 장치의 제조 방법을 이용하여 제조된, MEMS 장치. MEMS device manufactured using the manufacturing method of the MEMS device as described in any one of Claims 6-7.
PCT/KR2015/004919 2015-04-08 2015-05-15 Method of manufacturing cap substrate, method of manufacturing mems device using same, and mems device WO2016163585A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2015-0049770 2015-04-08
KR1020150049770A KR101644266B1 (en) 2015-04-08 2015-04-08 Method of manufacturing cap substrate, method of manufacturing mems device using the same, and mems device

Publications (1)

Publication Number Publication Date
WO2016163585A1 true WO2016163585A1 (en) 2016-10-13

Family

ID=56617902

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2015/004919 WO2016163585A1 (en) 2015-04-08 2015-05-15 Method of manufacturing cap substrate, method of manufacturing mems device using same, and mems device

Country Status (2)

Country Link
KR (1) KR101644266B1 (en)
WO (1) WO2016163585A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050121768A1 (en) * 2003-12-05 2005-06-09 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
KR20080016340A (en) * 2006-08-18 2008-02-21 삼성전자주식회사 Method of forming through electrode, mems structure and method of manufacturing thereof using the same
KR20100112699A (en) * 2009-04-10 2010-10-20 (주)엠투엔 Gas sensing device and method for manufacturing the same
US20110095435A1 (en) * 2009-10-28 2011-04-28 International Business Machines Corporation Coaxial through-silicon via
KR20140014251A (en) * 2011-06-23 2014-02-05 인터내셔널 비지네스 머신즈 코포레이션 Optimized annular copper tsv

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100230392B1 (en) * 1996-12-05 1999-11-15 윤종용 The method of forming contact plug in semiconductor device
KR100988780B1 (en) * 2008-05-15 2010-10-20 주식회사 동부하이텍 Method of manufacturing a capacitor of a semiconductor device
KR20110078176A (en) * 2009-12-30 2011-07-07 주식회사 동부하이텍 Method for manufacturing semiconductor device
KR101471190B1 (en) 2012-12-31 2014-12-11 한국과학기술원 Method of manufacturing Mems structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050121768A1 (en) * 2003-12-05 2005-06-09 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
KR20080016340A (en) * 2006-08-18 2008-02-21 삼성전자주식회사 Method of forming through electrode, mems structure and method of manufacturing thereof using the same
KR20100112699A (en) * 2009-04-10 2010-10-20 (주)엠투엔 Gas sensing device and method for manufacturing the same
US20110095435A1 (en) * 2009-10-28 2011-04-28 International Business Machines Corporation Coaxial through-silicon via
KR20140014251A (en) * 2011-06-23 2014-02-05 인터내셔널 비지네스 머신즈 코포레이션 Optimized annular copper tsv

Also Published As

Publication number Publication date
KR101644266B1 (en) 2016-07-29

Similar Documents

Publication Publication Date Title
CN101048868B (en) Method for manufacturing semiconductor device having three-dimensional multilayer structure
US5424245A (en) Method of forming vias through two-sided substrate
WO2014104516A1 (en) Circuit board having interposer embedded therein, electronic module using same, and method for manufacturing same
CN101312161B (en) Electronic structure and manufacturing method
EP2466634B1 (en) Integration of shallow trench isolation and through-substrate vias into integrated circuit designs
CN102074564B (en) Bonding process for CMOS image sensor
WO2009151274A2 (en) Rear illuminated image sensor and manufacturing method for same
US8653648B2 (en) Zigzag pattern for TSV copper adhesion
CN102301465B (en) Through substrate vias
CN103107157B (en) Wafer encapsulation body and forming method thereof
JP2010199589A (en) Image sensor device and manufacturing method for semiconductor image sensor device
CN1795552A (en) Method for manufacturing a multi-level interconnect structure
US7074716B2 (en) Method of manufacturing a semiconductor device
WO2013147358A1 (en) Semiconductor package and method for manufacturing same
WO2012115333A1 (en) Substrate having penetrating structure and manufacturing method thereof, package device including substrate having penetrating structure and manufacturing method thereof
CN115101546A (en) Method for manufacturing semiconductor device
WO2016163585A1 (en) Method of manufacturing cap substrate, method of manufacturing mems device using same, and mems device
WO2013147359A1 (en) Semiconductor package and method for manufacturing same
WO2016182395A1 (en) Sensor packaging and method for manufacturing same
WO2015072723A1 (en) Substrate separation-type three-dimensional chip stacking image sensor and method for manufacturing same
CN109148360A (en) Manufacturing method of semiconductor device
KR100639073B1 (en) Method of forming metal interconnect for semiconductor device by selective damascene process
CN108511473B (en) Interconnection process for metal layers between wafers
CN102832162A (en) Air bridge three-dimensional circuit and manufacturing method thereof
CN112928030A (en) Capacitor structure processing method and semiconductor structure

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15888570

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 28/02/2018)

122 Ep: pct application non-entry in european phase

Ref document number: 15888570

Country of ref document: EP

Kind code of ref document: A1