WO2016167146A1 - Sine wave multiplication device and input device having same - Google Patents
Sine wave multiplication device and input device having same Download PDFInfo
- Publication number
- WO2016167146A1 WO2016167146A1 PCT/JP2016/060948 JP2016060948W WO2016167146A1 WO 2016167146 A1 WO2016167146 A1 WO 2016167146A1 JP 2016060948 W JP2016060948 W JP 2016060948W WO 2016167146 A1 WO2016167146 A1 WO 2016167146A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- square wave
- signal
- wave
- capacitor
- input signal
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/548—Trigonometric functions; Co-ordinate transformations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1466—Passive mixer arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1483—Balanced arrangements with transistors comprising components for selecting a particular frequency component of the output
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/006—Signal sampling
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/0066—Mixing
- H03D2200/0074—Mixing using a resistive mixer or a passive mixer
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/0086—Reduction or prevention of harmonic frequencies
Definitions
- the present invention relates to a sine wave multiplier that multiplies an input signal by a sine wave, and an input device having the sine wave multiplier.
- the Gilbert cell type analog multiplier has been put into practical use, for example, with the configuration shown in FIG.
- the thermal voltage VT is included as a coefficient in the multiplication result, as shown in the equations (14) and (20) of Patent Document 1.
- the thermal voltage VT is expressed by “k ⁇ T / q”, where k is a Boltzmann constant, T is an absolute temperature, and q is an elementary charge of an electron. Therefore, the multiplication result of the Gilbert cell, that is, the output voltage changes depending on the temperature.
- analog multiplier it is necessary to limit the range of the input voltage in order to ensure the multiplication accuracy due to the nonlinearity of the input / output characteristics of the transistor. For this reason, for example, when an analog multiplier is used in a capacitance type input device, securing a dynamic range of a signal and fluctuation due to temperature are problems.
- sine wave multiplication is performed using an analog multiplier, it is necessary to generate a sine wave separately. Therefore, for example, in order to perform high-precision signal extraction by multiplying the input signal by a sine wave, it is necessary to generate a high-precision sine wave, which increases the circuit scale for generating a sine wave and reduces power consumption. There is a problem that increases.
- the present invention has been made in view of such circumstances, and an object of the present invention is to provide a sine wave multiplication device having a simple configuration, a wide range of input signal levels, and a small variation in characteristics due to temperature.
- a first aspect of the present invention relates to a sine wave multiplier that multiplies an input signal by a sine wave having a predetermined frequency.
- the sine wave multiplication device includes a plurality of square wave multiplication units that multiply the input signal by square waves having different frequencies, and a signal synthesis unit that synthesizes output signals of the plurality of square wave multiplication units.
- the square wave can be approximated as the sum of a fundamental wave that is a sine wave having the lowest frequency and a plurality of harmonics that are sine waves each having an integer multiple of the fundamental wave.
- the plurality of square wave multiplication units include one first square wave multiplication unit and one or more second square wave multiplication units.
- the first square wave multiplier multiplies the input signal by a first square wave having the sine wave of the predetermined frequency as the fundamental wave.
- the second square wave multiplication unit is a second square wave having the fundamental wave as a sine wave equal to one harmonic included in the first square wave or a sine wave obtained by inverting the phase of the one harmonic. Is multiplied by the input signal.
- the signal synthesis unit converts a signal component corresponding to a product of at least one harmonic of the first square wave included in the output signal of the first square wave multiplication unit and the input signal into the second square wave. The signal is canceled by a signal component corresponding to the product of the fundamental wave of the second square wave and the input signal included in the output signal of the multiplier.
- a signal component corresponding to a product of at least one harmonic of the first square wave and the input signal included in the output signal of the first square wave multiplier is the second square wave.
- the signal is canceled by a signal component corresponding to the product of the fundamental wave of the second square wave and the input signal included in the output signal of the wave multiplier. Therefore, in the signal resulting from the synthesis by the signal synthesis unit, the signal component corresponding to the product of the harmonic of the first square wave and the input signal is reduced, and the fundamental wave of the first square wave (the A signal component corresponding to a product of a sine wave having a predetermined frequency and the input signal becomes a dominant component.
- the square wave multiplication unit is used to multiply the sine wave (the fundamental wave of the first square wave) and the input signal. Less susceptible to fluctuations, and changes in characteristics due to temperature are small. Further, the use of the square wave multiplication unit makes it difficult to be affected by the input / output nonlinear characteristics of the transistor as in the case of an analog multiplier, so that the range of the level of the input signal is widened. Further, in the sine wave multiplication device, the sine wave generator can be omitted by using the square wave multiplication unit, so that the circuit configuration is simplified.
- the square wave multiplication unit generates an output signal proportional to the input signal in each of one half cycle and the other half cycle in one cycle of the square wave multiplied by the input signal, and
- the output signal may be generated such that the absolute value of the ratio between the input signal and the output signal is equal in one half cycle and the other half cycle, and the sign of the ratio is inverted.
- the absolute value of the ratio between the input signal and the output signal is the same in one half cycle and the other half cycle in one cycle of the square wave multiplied by the input signal.
- the output signal is generated so that the sign of the ratio is inverted.
- the input signal and the square wave are multiplied by inverting the sign of each square wave half cycle while maintaining the absolute value of the ratio of the output signal to the input signal. Therefore, unlike an analog multiplier, it is difficult to be influenced by the temperature characteristics and input / output nonlinear characteristics of the transistor.
- the square wave multiplication unit is a charge that accumulates a charge proportional to the voltage of the input signal in each of one half cycle and the other half cycle of the square wave multiplied by the input signal.
- the operation and the charge output operation of outputting the charge accumulated by the charging operation to the signal synthesizer are alternately repeated at a predetermined sampling period, and the half cycle and the other half cycle,
- the charging operation and the charge output operation may be performed so that the ratio between the voltage of the input signal and the amount of charge accumulated by the charging operation is equal, and the polarity of the charge output to the signal synthesis unit is inverted.
- the signal synthesis unit responds to the sum of the charges output from the plurality of square wave multiplication units by the charge output operation each time the charge output operation is performed a predetermined number of times in the plurality of square wave multiplication units.
- a signal may be generated.
- the first square wave multiplication unit and the second square wave multiplication unit may include at least one capacitor that accumulates electric charge in the charging operation.
- the capacitance of the capacitor in which the first square wave multiplication unit accumulates electric charge in the charging operation, and the capacitance of the capacitor in which the second square wave multiplication unit accumulates electric charge in the charging operation Is a value corresponding to a ratio between the amplitude of the fundamental wave of the first square wave and the amplitude of the harmonic wave of the first square wave having the same frequency as the fundamental wave of the second square wave. You may have.
- the ratio of the charge output from the first square wave multiplication unit and the charge output from the second square wave multiplication unit in the charge output operation is equal to that of the first square wave multiplication unit. It has a value corresponding to the ratio between the capacitance of the capacitor and the capacitance of the capacitor of the second square wave multiplier. And the ratio of the capacitance is the amplitude of the fundamental wave of the first square wave and the amplitude of the harmonic wave of the first square wave having the same frequency as the fundamental wave of the second square wave. It has a value according to the ratio.
- the signal output from the first square wave multiplication unit and the charge output from the second square wave multiplication unit are added together in the signal synthesis unit, so that the harmonics of the first square wave and the The signal component corresponding to the product of the input signal can be canceled by the signal component corresponding to the product of the fundamental wave of the second square wave and the input signal. Further, since the capacitance ratio of the capacitor is hardly affected by variations due to temperature and manufacturing process, the signal components can be accurately canceled.
- the sine wave multiplier may include an input node to which the input signal is input and an output node to which outputs of the plurality of square wave multipliers are connected in common.
- the square wave multiplication unit connects one end of the first capacitor to the input node in one half cycle of the first capacitor and the second capacitor, and one cycle of the square wave multiplied by the input signal.
- a charge operation for connecting the other end of the first capacitor to a reference potential; and a charge output for connecting the one end of the first capacitor to the output node and for connecting the other end of the first capacitor to the reference potential.
- one end of the second capacitor is connected to the input node.
- a charging operation for connecting the other end of the second capacitor to the reference potential; and the other end of the second capacitor connected to the output node. May have a second switch section for repeating the charge output operation for connecting said one end of said second capacitor to said reference potential alternately at the sampling period with connecting.
- the signal synthesizer sets the voltage at the other terminal of the third capacitor so that a voltage difference between the third capacitor having one terminal connected to the output node and the output node and the reference potential is zero.
- the first switch unit includes a first switch element provided in a current path between the input node and the one end of the first capacitor, and the one end of the first capacitor and the output node. And a second switch element provided in a current path therebetween.
- the other end of the first capacitor may be connected to the reference potential.
- the second switch unit includes a third switch element provided in a current path between the input node and the one end of the second capacitor, and between the other end of the second capacitor and the reference potential.
- a fourth switch element provided in a current path, a fifth switch element provided in a current path between the other end of the second capacitor and the output node, the one end of the second capacitor, and the reference
- a sixth switch element provided in a current path between the potential.
- the first switch element is turned on and the other switch elements are turned off during the charging operation, and the charge output operation is performed.
- the second switch element may be turned on and the other switch elements may be turned off.
- the third switch element and the fourth switch element are turned on and the other switch elements are turned off during the charging operation.
- the fifth switch element and the sixth switch element may be turned on and the other switch elements may be turned off.
- the square wave multiplication unit may include a fourth capacitor provided in a current path between the first switch element and the input node.
- the first switch unit includes a seventh switch element provided in a current path between one end of the fourth capacitor and the input node, and a current path between the one end of the fourth capacitor and the reference potential.
- an ninth switch element provided in a current path between the other end of the fourth capacitor and the reference potential.
- the seventh switch element may be turned on / off under the same conditions as the first switch element.
- the eighth switch element and the ninth switch element may be turned on / off under the same conditions as the second switch element.
- the sine wave multiplier is a noise component included in the input signal input to the plurality of square wave multipliers, from a frequency that is an integral multiple of the sampling frequency to the signal band of the input signal.
- a first low-pass filter that attenuates the noise component that may cause aliasing noise may be provided. Thereby, the aliasing noise in the signal generated in the signal synthesis unit is reduced.
- the square wave multiplication unit inputs the input signal and an inverted input signal in which the polarity of the input signal is inverted, and in one half cycle of one cycle of the square wave to multiply the input signal, the input An output signal proportional to the signal at a predetermined ratio may be generated, and an output signal proportional to the inverted input signal at the predetermined ratio may be generated in the other half cycle of the one cycle.
- the square wave multiplier generates an output current proportional to the voltage of the input signal at a predetermined ratio in one half cycle of the square wave multiplied by the input signal, and the other in the one cycle. In this half cycle, an output current proportional to the voltage of the inverted input signal at the predetermined ratio may be generated.
- the signal synthesis unit may generate a signal corresponding to the sum of the output currents output from the plurality of square wave multiplication units.
- the sine wave multiplication device has N patterns of the second squares corresponding to the first to Nth harmonics in order of decreasing frequency among the harmonics included in the first square wave.
- the signal component corresponding to the harmonics of the first square wave is reduced in the signal generated in the signal synthesis unit.
- a second aspect of the present invention relates to an input device that inputs information according to the proximity of an object.
- This input device multiplies a DC signal by a sine wave having a predetermined frequency and a sensor unit including a sensor element whose capacitance changes in accordance with the proximity of the object, and as a result of the multiplication,
- a first sine wave multiplier for outputting a first sine wave; and a sine wave drive voltage corresponding to the first sine wave is applied to the sensor element, and the current flowing in the sensor element is applied by the application of the drive voltage.
- a detection signal generation unit that generates a detection signal, a second sine wave multiplication unit that multiplies the detection signal by a second sine wave having the predetermined frequency, and a signal obtained by multiplying the second sine wave multiplication unit by direct current.
- a low-pass filter for extracting components.
- the first sine wave multiplier and the second sine wave multiplier are sine wave multipliers according to the first aspect.
- the range of the level of the input signal can be widened with a simple configuration, and fluctuations in characteristics due to temperature can be reduced.
- FIG. 1A shows a block diagram
- FIG. 1B shows an example of a circuit configuration.
- FIG. 2A shows the frequency component of a square wave
- FIG. 2B shows the frequency component of a square wave.
- FIG. 3A shows a frequency component of a square wave having a predetermined frequency
- FIGS. 3B and 3C show a frequency component of a square wave including a fundamental wave equal to the harmonic of the square wave of FIG. 3A.
- FIG. 1 is a diagram showing a configuration example of a circuit that multiplies an input signal Si by a square wave.
- Square wave multiplication is different from sine wave multiplication, and can be realized by a simple circuit using fixed gain amplifier circuits 2 and 4 and a switch circuit 3, for example, as shown in FIG. 1B.
- an input signal Si or a signal obtained by inverting the input signal Si by the amplifier circuit 2 having a gain “ ⁇ 1” is input to the amplifier circuit 4 having a gain A through the switch circuit 3.
- the input signal Si is amplified (multiplied by A) by the amplifier circuit 4 having a gain A, and in the other half cycle of the square wave, the input signal Si has a gain A and a gain.
- FIG. 2 is a diagram showing frequency components of a sine wave and a square wave.
- a sine wave consists of only a single frequency component as shown in FIG. 2A, while a square wave consists of a fundamental wave and a harmonic as shown in FIG. 2B.
- the square wave multiplication result signal shown in FIG. 1 includes a signal component obtained by multiplying the input signal Si by the fundamental wave (input signal Si ⁇ fundamental wave) and a signal component obtained by multiplying the input signal Si by the harmonic wave (input signal). (Si ⁇ harmonic).
- the multiplication of the square wave has an advantage that the circuit configuration is simple and it is difficult to be influenced by the temperature characteristics and input / output nonlinear characteristics of the transistor as in the case of using an analog multiplier.
- the signal of the square wave multiplication result includes the harmonic signal component (input signal Si ⁇ harmonic) as described above, it cannot be used as it is as the multiplication result of the input signal Si and the sine wave. Therefore, in the sine wave multiplication device according to the present embodiment, a plurality of circuits that multiply the input signal and the square wave are provided, and their outputs are combined to be included in the multiplication result of the input signal and the square wave. Unnecessary signal components (input signal x harmonic) are canceled.
- FIG. 3 is a diagram showing frequency components of a square wave.
- FIG. 3A shows the frequency component of a square wave of frequency fs.
- FIG. 3B shows frequency components of a square wave having a frequency (3fs) that is three times that of the square wave of FIG. 3A and an amplitude (A / 3) that is one third.
- FIG. 3C shows a frequency component of a square wave having a frequency (5 fs) five times that of the square wave of FIG. 3A and an amplitude (A / 5) of one fifth.
- the square wave having the frequency fs includes a fundamental wave having the frequency fs and harmonics having frequencies (3fs, 5fs, 7fs,...) That are odd multiples thereof.
- the amplitude of the fundamental wave is “B”
- the amplitude of the harmonic having the frequency “K ⁇ fs” (hereinafter referred to as “Kth harmonic”) is “B / K”.
- the fundamental wave in the square wave of frequency 3fs and amplitude B / 3 shown in FIG. 3B is equal to the third harmonic in the square wave of frequency fs and amplitude B shown in FIG. 3A.
- the fundamental wave in the square wave of frequency 5fs and amplitude B / 5 shown in FIG. 3C is equal to the fifth harmonic in the square wave of frequency fs and amplitude B shown in FIG. 3A.
- FIG. 4 is a diagram illustrating an example of the configuration of the sine wave multiplier according to the first embodiment of the present invention.
- the sine wave multiplier shown in FIG. 1 includes three square wave multipliers U1, U2, and U3 that multiply square signals W1, W2, and W3 having different frequencies by an input signal Si, and the square wave multipliers U1, U2, and U3.
- a signal synthesizer 10 that synthesizes the output signals Su1, Su2, Su3 of U3 is provided.
- square wave multiplier U an arbitrary one of the square wave multipliers U1 to U3 is referred to as a “square wave multiplier U”
- an arbitrary one of the output signals Su1 to Su3 is referred to as an “output signal Su”
- the square waves W1 to W3 Arbitrary one is described as “square wave W”.
- the square wave W multiplied by the input signal Si in the square wave multiplication unit U has a waveform with the same amplitude and opposite polarity in one half cycle and the other half cycle.
- This square wave W can be approximated as the sum of a fundamental wave and a harmonic wave as shown in FIGS. 2 and 3, and the Kth harmonic wave has a frequency K times that of the fundamental wave and an amplitude of 1 / K. have.
- the square wave multiplier U generates, for example, an output signal Su proportional to the input signal Si in each of one half cycle and the other half cycle in one cycle of the square wave W to be multiplied by the input signal Si.
- the output signal Su is generated so that the absolute value of the ratio between the input signal Si and the output signal Su is equal in the half cycle and the other half cycle, and the sign of the ratio is inverted. That is, the square wave multiplication unit U sets the ratio of the output signal Su to the input signal Si in one half cycle in one cycle of the square wave W to “A”, and the other half cycle in one cycle of the square wave W.
- the ratio of the output signal Su to the input signal Si is “ ⁇ A”.
- the square wave multiplier U1 (hereinafter referred to as “first square wave multiplier U1”) has a square wave W1 having a sine wave of frequency fs as a fundamental wave (hereinafter referred to as “first square wave W1”). Is multiplied by the input signal Si.
- the frequency of the first square wave W1 is “fs”, and the amplitude is “A”.
- Square wave multipliers U2 and U3 are used to generate one harmonic wave included in first square wave W1 having frequency fs.
- Square waves W2 and W3 (hereinafter referred to as “second square wave W2” and “second square wave W3”) having sine waves with inverted phases as fundamental waves are respectively multiplied by the input signal Si. That is, the second square wave multiplication unit U2 multiplies the input signal Si by a second square wave W2 having a sine wave obtained by inverting the phase of the third harmonic in the first square wave W1 as a fundamental wave. As shown in FIG.
- the frequency of the second square wave W2 is “3fs” and the amplitude is “A / 3”.
- the second square wave multiplication unit U3 multiplies the input signal Si by a second square wave W3 having a sine wave obtained by inverting the phase of the fifth harmonic in the first square wave W1 as a fundamental wave. As shown in FIG. 4, the frequency of the second square wave W3 is “5fs” and the amplitude is “A / 5”.
- the signal synthesis unit 10 adds the output signal Su1 of the first square wave multiplication unit U1 and the output signals Su2 and Su3 of the second square wave multiplication units U2 and U3.
- the signal synthesizer 10 outputs the signal component corresponding to the product of the third harmonic of the first square wave W1 included in the output signal Su1 and the input signal Si by adding the output signals Su1 to Su3.
- the signal component is canceled by a signal component corresponding to the product of the fundamental wave of the second square wave W2 included in the signal Su2 and the input signal Si.
- the signal synthesizer 10 generates a signal component corresponding to the product of the fifth harmonic of the first square wave W1 included in the output signal Su1 and the input signal Si, and the second square wave W3 included in the output signal Su3. Is canceled by a signal component corresponding to the product of the fundamental wave and the input signal Si.
- the input signal Si in one half cycle and the other half cycle in one cycle of the square wave W multiplied by the input signal Si.
- the output signal Su is generated so that the absolute value of the ratio between the output signal Su and the output signal Su is equal and the sign of the ratio is inverted. That is, the input signal Si and the square wave W are multiplied by inverting the positive / negative sign for each half cycle of the square wave W while maintaining the absolute value of the ratio (signal gain) of the output signal Su to the input signal Si. Done.
- Such multiplication of the square wave W is discrete signal processing in which a fixed signal gain is switched every half cycle, and the influence of the analog characteristics of the transistor current and voltage on the multiplication result is reduced. Therefore, it is possible to make it difficult to be influenced by the temperature characteristics and input / output nonlinear characteristics of the transistor as in the case of using an analog multiplier.
- FIG. 5 is a diagram illustrating an example of the configuration of the sine wave multiplication device according to the second embodiment.
- FIG. 6 is a diagram showing an example of the configuration of square wave multipliers U1 to U3 (square wave multiplier U) in the sine wave multiplier shown in FIG.
- the inputs of the square wave multipliers U1 to U3 are connected to an input node Ni to which an input signal Si is applied, and the outputs of the square wave multipliers U1 to U3 are connected to a common output node Nc.
- the square wave multiplication unit U in the present embodiment outputs the multiplication result of the input signal Si and the square wave W as an electric charge. That is, the square wave multiplying unit U stores a charge proportional to the voltage of the input signal Si in each of one half cycle and the other half cycle in one cycle of the square wave W multiplied by the input signal Si. And a charge output operation for outputting the charge accumulated by the charging operation to the signal synthesizer 10 are alternately repeated at a predetermined sampling period T. Further, the square wave multiplication unit U calculates the voltage of the input signal Si and the amount of charge accumulated by the charging operation in one half cycle and the other half cycle in one cycle of the square wave W multiplied by the input signal Si. The charge operation and the charge output operation are performed so that the ratio (voltage / charge amount) is equal and the polarity of the charge output to the signal synthesis unit 10 is inverted.
- the square wave multiplication unit U includes a first capacitor C1 and a second capacitor C2, a first switch unit 21 that performs a charge operation and a charge output operation of the first capacitor C1, and a second capacitor C2. And a second switch unit 22 for performing the charge operation and the charge output operation.
- the first capacitor C1 is used for the charging operation and the charge output operation in one half cycle in one cycle of the square wave W multiplied by the input signal Si, and the second capacitor 2 is used in the other half cycle in the one cycle. Used for charge operation and charge output operation.
- the first capacitor C1 and the second capacitor C2 have the same capacitance.
- the capacitances of the first capacitor C1 and the second capacitor C2 in the first square wave multiplier U1, the second square wave multiplier U2, and the third square wave multiplier U3 are the harmonics of the first square wave W1 and the second The fundamental waves of the square waves W2, W3 are set to have the same amplitude.
- the capacitances of the first capacitor C1 and the second capacitor C2 in the first square wave multiplication unit U1 are “Cu1”, and the capacitances of the first capacitor C1 and the second capacitor C2 in the second square wave multiplication unit U2 are “Cu2”. If the capacitances of the first capacitor C1 and the second capacitor C2 in the third square wave multiplication unit U3 are “Cu3”, these capacitances are set as follows.
- the ratio between the electrostatic capacitance Cu1 and the electrostatic capacitance Cu2 is set as follows according to the ratio between the amplitude of the fundamental wave of the first square wave W1 and the amplitude of the third harmonic.
- the amount of charge output from the first square wave multiplier U1 by the third harmonic of the first square wave W1 and the second The amount of charge output from the second square wave multiplier U2 is equalized by the fundamental wave of the square wave W2. Since the third harmonic of the first square wave W1 and the fundamental wave of the second square wave W2 have opposite phases, the first square wave multiplier U1 according to the third harmonic of the first square wave W1. The charge output from the second square wave is canceled by the charge output from the second square wave multiplier U2 in accordance with the fundamental wave of the second square wave W2.
- the ratio between the electrostatic capacitance Cu1 and the electrostatic capacitance Cu3 is set as follows according to the ratio between the amplitude of the fundamental wave of the first square wave W1 and the amplitude of the fifth harmonic.
- the ratio of the capacitances Cu1, Cu2 and Cu3 is expressed by the following formula.
- the first switch unit 21 repeatedly performs the charging operation and the charge output operation of the first capacitor C1 in one half cycle of one cycle of the square wave W. In the half cycle in which the first switch unit 21 operates, the charging operation and the charge output operation of the second capacitor C2 by the second switch unit 22 are stopped.
- the first switch unit 21 connects one end of the first capacitor C1 to the input node Ni and connects the other end of the first capacitor C1 to the reference potential.
- the first switch unit 21 connects the one end of the first capacitor C1 to the output node Nc and connects the other end of the first capacitor C1 to the reference potential.
- the first switch unit 21 repeats the charging operation and the charge output operation alternately with the sampling period T.
- the first switch unit 21 includes a first switch element SW1 and a second switch element SW2, for example, as shown in FIG.
- the first switch element SW1 is provided in a current path between the input node Ni and one end of the first capacitor C1.
- the second switch element SW2 is provided in a current path between the one end of the first capacitor C1 and the output node Nc.
- the other end of the first capacitor C1 is connected to a reference potential.
- the second switch unit 22 repeatedly performs the charging operation and the charge output operation of the second capacitor C2 in the other half cycle in one cycle of the square wave W. In the other half cycle in which the second switch unit 22 operates, the charging operation and the charge output operation of the first capacitor C1 by the first switch unit 21 are stopped.
- the second switch unit 22 connects one end of the second capacitor C2 to the input node Ni and connects the other end of the second capacitor C2 to the reference potential.
- the second switch unit 22 connects the other end of the second capacitor C2 to the output node Nc and connects the one end of the second capacitor C2 to the reference potential.
- the second switch unit 22 repeats the charging operation and the charge output operation alternately with the sampling period T.
- the second switch section 22 includes, for example, a third switch element SW3, a fourth switch element SW4, a fifth switch element SW5, and a sixth switch element SW6 as shown in FIG.
- the third switch element SW3 is provided in a current path between the input node Ni and one end of the second capacitor C2.
- the fourth switch element SW4 is provided in a current path between the other end of the second capacitor C2 and the reference potential.
- the fifth switch element SW5 is provided in a current path between the other end of the second capacitor C2 and the output node Nc.
- the sixth switch element SW6 is provided in a current path between one end of the second capacitor C2 and the reference potential.
- the switch elements of the first switch unit 21 and the second switch unit 22 operate as follows. In one half cycle of the square wave W in which the first switch unit 21 operates, the first switch element SW1 and the second switch element SW2 are alternately turned on. That is, when the charging operation of the first capacitor C1 is performed, the first switch element SW1 is turned on and the other switch elements are turned off. When the charge output operation of the second capacitor C2 is performed, the second switch element SW2 is turned on and the other switch elements are turned off. In the other half cycle of the square wave W in which the second switch unit 22 operates, the pair of the third switch element SW3 and the fourth switch element SW4 and the pair of the fifth switch element SW5 and the sixth switch element SW6 are alternately turned on. To do.
- the pair of the third switch element SW3 and the fourth switch element SW4 are both turned on and the other switch elements are turned off.
- the pair of the fifth switch element SW5 and the sixth switch element SW6 are both turned on and the other switch elements are turned off.
- the charge output to the signal synthesis unit 10 when the same input signal Si is given.
- the polarity is reversed. That is, when the input signal Si has a positive voltage with respect to the reference potential, a positive charge is output to the signal synthesis unit 10 by the charging operation and the charge output operation of the first switch unit 21, and the second switch unit 22 is charged. A negative charge is output to the signal synthesis unit 10 by the operation and the charge output operation.
- an operation mode in which a positive charge is output to the signal synthesizer 10 when the input signal Si has a positive voltage with respect to the reference potential is referred to as a “forward rotation mode” and is negative to the signal synthesizer 10.
- the operation mode in which the electric charges are output is called “inversion mode”.
- the signal combiner 10 calculates the sum of the charges output from the square wave multipliers (U1 to U3). A corresponding output signal So is generated.
- the signal synthesis unit 10 includes a third capacitor C3, an amplifier circuit OP1, and a discharge circuit SWr.
- the third capacitor C3 has one terminal connected to the output node Nc and the other terminal connected to the output of the amplifier circuit OP1.
- the amplifier circuit OP1 controls the voltage of the other terminal of the third capacitor C3 so that the voltage difference between the output node Nc and the reference potential becomes zero.
- the amplifier circuit OP1 is an operational amplifier, for example, and an inverting input terminal is connected to the output node Nc, and a non-inverting input terminal is connected to a reference potential. In this case, the output node Nc connected to the inverting input terminal of the amplifier circuit OP1 is substantially equal to the reference potential.
- the discharge circuit SWr discharges the charge accumulated in the third capacitor C3 each time a predetermined number of charge output operations are performed in the square wave multipliers (U1 to U3).
- the discharge circuit SWr is configured by a switch element connected in parallel with the third capacitor C3.
- the capacitor (C1, C2) Since the other terminal is connected to the reference potential and the output node Nc is kept at the reference potential by the amplifier circuit OP1, the charge accumulated in the capacitors (C1, C2) of the square wave multipliers (U1 to U3) is reduced. Transferred to the second capacitor C3. Therefore, the voltage of the output signal So of the amplifier circuit OP1 is a voltage corresponding to the sum of charges transferred from the capacitors (C1, C2) of the square wave multipliers (U1 to U3).
- FIG. 7 is a timing chart showing the on / off states of the switch elements of the square wave multipliers (U1 to U3) and the signal synthesizer 10 in the sine wave multiplier according to the second embodiment.
- a high level indicates an on state of the switch element
- a low level indicates an off state of the switch element.
- the first switch element SW1 and the second switch element SW2 that are alternately turned on are controlled so that the on states of the first switch element SW1 and the second switch element SW2 do not overlap each other in order to avoid crosstalk due to a delay in the on / off operation.
- one period (1 / fs) of the first square wave W1 is set to 60 cycles (60T) of the sampling period T
- one period (1/3 fs) of the second square wave W2 is the sampling period.
- T is set to 20 cycles (20T)
- one cycle (1/5 fs) of the second square wave W3 is set to 12 cycles (12T) of the sampling cycle T.
- the number of cycles of the sampling period T that defines the half period of the first square wave W1 (30 cycles in the example of FIG. 7) is the first square wave to be canceled by the output of the second square wave multiplier (U2, U3).
- the frequency of harmonics of W1 (3fs, 5fs) is set to be a common multiple of the magnification (3 times, 5 times) of the fundamental frequency fs.
- “30” that is a common multiple of “3” and “5” is the first harmonic. It is set to the number of cycles of the sampling period T in the half period of one square wave W1.
- the cycle number of the sampling period T in the half cycle of the first square wave W1 can be set to an integer value. Therefore, the ratio between the period of the first square wave W1 and the period of the second square waves W2, W3 can be strictly set by the number of cycles of the sampling period T.
- the first switch unit 21 performs the forward mode operation 30 times in the first half cycle (30T) of the first square wave W1, and the second half cycle of the first square wave W1.
- the second switch unit 22 performs the inversion mode operation 30 times.
- inversion mode operation is performed ten times by the second switch unit 22 in the first half cycle (10T) of the second square wave W2, and the second half cycle of the second square wave W2 ( 10T), the first switch unit 21 performs the forward rotation mode 10 times.
- the first square wave multiplication unit U1 starts the forward rotation mode operation
- the second square wave multiplication unit U2 starts the inversion mode operation. Therefore, the fundamental wave of the second square wave W2 is the first square wave W1. It has an opposite phase to the third harmonic.
- the second switch unit 22 performs the inversion mode operation six times in the first half cycle (6T) of the second square wave W3, and the second half wave of the second square wave W3 ( 6T), the first switch unit 21 performs the forward rotation mode six times.
- the operation in the normal rotation mode is started in the first square wave multiplication unit U1
- the operation in the inversion mode is started in the second square wave multiplication unit U3. Therefore, the fundamental wave of the second square wave W2 is the first square wave W1. Have the opposite phase to the fifth harmonic.
- the discharge circuit SWr is turned on every sampling cycle T in which the charging operation is performed in the square wave multiplication units U1 to U3, and the charge of the third capacitor C3 is discharged.
- a subsequent circuit (not shown) that processes the output signal So of the signal synthesizer 10 samples the output signal So while the discharge circuit SWr is off, and performs low-pass filter processing or analog processing on the sampled and held analog signal. Perform processing such as digital conversion.
- the charge of the third capacitor C3 is discharged every cycle of the sampling period T.
- the discharge circuit SWr is turned on once every plural cycles of the sampling period T. It may be turned on.
- the subsequent circuit that processes the output signal So samples the output signal So immediately before the discharge circuit SWr is turned on.
- the amount of charge accumulated in the third capacitor C3 increases, so that the level of the output signal So can be increased.
- the charging operation and the charge output operation of the capacitors (C1, C2) are repeated at the sampling period T in the square wave multiplication unit U.
- the period and phase of the square wave in the square wave multiplication unit U can be strictly set by the number of cycles of the sampling period T.
- the capacitance ratio of the capacitors in the square wave multiplication unit U is not easily affected by variations due to temperature and manufacturing process, the ratio of the amplitudes of the square waves W multiplied by the input signal Si in each square wave multiplication unit U. Can be set with high accuracy.
- the signal component (charge) corresponding to the product of the harmonic of the first square wave W1 included in the output of the first square wave multiplier U1 and the input signal Si is output to the outputs of the second square wave multipliers U2 and U3. Can be accurately canceled by the signal component (charge) corresponding to the product of the fundamental wave of the second square waves W2 and W3 and the input signal Si.
- the sine wave multiplier according to the third embodiment is obtained by replacing the square wave multipliers U1 to U3 in the sine wave multiplier according to the second embodiment with square wave multipliers UA1 to UA3 shown in FIG.
- the configuration is the same as that of the sine wave multiplier according to the second embodiment.
- the square wave multiplication units UA1 to UA3 include a first capacitor C1, a second capacitor C2, a fourth capacitor C4, a first switch unit 21A, and a second switch unit 22. Since the second switch unit 22 and the second capacitor C2 are the same as the components having the same reference numerals in FIG. 6, the description thereof is omitted here.
- the first switch unit 21A includes switch elements (SW1, SW2) similar to those of the first switch unit 21, and includes a seventh switch element SW7, an eighth switch element SW8, and a ninth switch element SW9.
- the fourth capacitor C4 is provided in the current path between the first switch element SW1 and the input node Ni.
- the seventh switch element SW7 is provided in a current path between one end of the fourth capacitor C4 and the input node Ni.
- the eighth switch element SW8 is provided in a current path between the one end of the fourth capacitor C4 and a reference potential.
- the ninth switch element SW9 is provided between the other end of the fourth capacitor C4 and the reference potential.
- FIG. 9 is a timing chart showing the on / off states of the switch elements of the square wave multipliers (UA1 to UA3) and the signal synthesizer 10 in the sine wave multiplier according to the third embodiment.
- the seventh switch element SW7 is turned on / off under the same conditions as the first switch element SW1.
- the eighth switch element SW8 and the ninth switch element SW9 are turned on / off under the same conditions as the second switch element SW2.
- the operation of the other switch elements is the same as the timing chart shown in FIG.
- the two switch elements (SW1, SW2) connected to the terminal that is not connected to the reference potential in the first capacitor C1 give unnecessary charges to the first capacitor C1 due to charging / discharging of the parasitic capacitance. Unnecessary charges may cause errors, which may reduce the accuracy of multiplication processing. Therefore, in the square wave multipliers UA1 to UA3 shown in FIG. 8, the series circuit of the first capacitor C1 and the fourth capacitor C4 is charged by the input signal Si during the charging operation, and the charge of the first capacitor C1 is charged during the charge output operation. The signal is output to the signal synthesizer 10 and both ends of the fourth capacitor C4 are connected to the reference potential to discharge the charge. By such an operation, unnecessary charges given to the first capacitor C1 due to charging / discharging of the parasitic capacitances of the switch elements (SW1, SW2, SW9) can be canceled.
- the series circuit of the first capacitor C1 and the fourth capacitor C4 since the charge is charged by the series circuit of the first capacitor C1 and the fourth capacitor C4 during the charging operation, the series circuit of the first capacitor C1 and the fourth capacitor C4.
- the capacitances of the first capacitor C1 and the fourth capacitor C4 are set so that the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 are equal.
- the capacitances of the first capacitor C1 and the fourth capacitor C4 are set to twice the capacitance of the second capacitor C2.
- FIG. 10 is a diagram illustrating an example of the configuration of the sine wave multiplication device according to the fourth embodiment.
- the sine wave multiplier shown in FIG. 10 is obtained by providing the first low-pass filter 30 in the sine wave multiplier (FIG. 5) according to the second and third embodiments, and the other configurations are the second and third. This is the same as the sine wave multiplier according to the embodiment.
- the first low-pass filter 30 is for reducing the aliasing noise, and attenuates the high-frequency component of the input signal Si input to the square wave multiplication unit. That is, the first low-pass filter 30 is a noise component included in the input signal Si, and a noise component that can cause aliasing from a frequency that is an integral multiple of the sampling frequency (1 / T) to the signal band of the input signal Si. Attenuate. Thereby, even when the input signal Si includes noise having a relatively high frequency, it is possible to prevent aliasing noise to the signal band of the input signal Si and perform highly accurate multiplication processing.
- the seventh harmonic having the next largest amplitude after the fifth harmonic may affect the accuracy of the multiplication result.
- the second square waves W2 and W3 are not only the fundamental wave, but also their harmonics are some harmonics of the first square wave W1 (FIG. 3A). Is equal to In the example of FIG. 3, the third and fifth harmonics of the second square wave W2 are equal to the ninth and fifteenth harmonics of the first square wave W1. Further, the third harmonic of the second square wave W3 is equal to the fifteenth harmonic of the first square wave W1. Therefore, since the 15th harmonic of the first square wave W1 is subtracted by both the second square wave W2 and the second square wave W3, an error occurs.
- the first low-pass filter 30 attenuates the high-frequency component of the input signal Si before inputting it to the square wave multipliers (U1 to U3, UA1 to U3). Since the lowest harmonic that may affect the accuracy is the seventh harmonic (frequency 7 fs) of the first square wave W1, the frequency characteristic of the first low-pass filter 30 is a component having a frequency higher than the frequency 7 fs. Is set to attenuate to the extent that does not affect the multiplication accuracy.
- FIG. 11 is a diagram illustrating another configuration example of the sine wave multiplication device according to the fourth embodiment.
- the sine wave multiplier shown in FIG. 11 is obtained by adding a second low-pass filter 40 to the sine wave multiplier shown in FIG. 10, and the other configuration is the same as the sine wave multiplier shown in FIG.
- the sine wave multiplier shown in FIG. 11 can be operated as a circuit (narrowband bandpass filter circuit) that extracts only the signal component of the frequency fs contained in the input signal Si.
- the level of the DC component becomes a level corresponding to the amplitude of the signal component of the frequency fs included in the input signal Si.
- the second low-pass filter 40 is configured by, for example, a digital filter that discretely processes the AD conversion result of the output signal So.
- FIG. 12 is a diagram illustrating an example of the configuration of the sine wave multiplier according to the fifth embodiment.
- the sine wave multiplier shown in FIG. 12 has a low-pass filter 50 provided in the sine wave multiplier (FIG. 5) according to the second and third embodiments, and the input signal Si is a DC voltage VDD.
- the configuration is the same as that of the sine wave multiplier according to the second and third embodiments.
- the output signal So is a signal obtained by multiplying the DC voltage VDD and the sine wave, that is, a sine wave.
- the sine wave multiplier shown in FIG. 10 converts the signal component of frequency fs into a direct current component.
- the sine wave multiplier shown in FIG. 12 since the sine wave multiplier shown in FIG. 12 generates a signal of frequency fs from the direct current component, the input / output relationship. Is reversed. Therefore, the low-pass filter 50 attenuates a component having a frequency higher than the seventh harmonic component (frequency fs), similarly to the sine wave multiplier shown in FIG.
- the sine wave multiplication device can be operated as a highly accurate sine wave generation circuit.
- FIG. 13 is a diagram illustrating an example of the configuration of the square wave multipliers UB1 to UB3 in the sine wave multiplier according to the sixth embodiment.
- the sine wave multiplier according to the third embodiment is obtained by replacing the square wave multipliers U1 to U3 in the sine wave multiplier according to the second embodiment with square wave multipliers UB1 to UB3 shown in FIG.
- the configuration is the same as that of the sine wave multiplier according to the second embodiment.
- the two capacitors (C1, C2) are provided independently for the normal rotation mode and the inversion mode, but in the square wave multiplication units UB1 to UB3 shown in FIG.
- the common capacitor C2 is used in the normal rotation mode and the inversion mode.
- the square wave multipliers UB1 to UB3 include a third switch unit 23 and a second capacitor C2 in the example of FIG.
- the third switch unit 23 includes a tenth switch element SW10 in addition to the same switch elements (SW3, SW4, SW5, SW6) as the second switch unit 22.
- the connection relationship between the second capacitor C2 and the switch elements (SW3, SW4, SW5, SW6) is the same as in FIGS.
- the tenth switch element SW10 is provided in the current path between one end of the second capacitor C2 to which the third switch element SW3 and the sixth switch element SW6 are connected and the output node Nc.
- FIG. 14 is a timing chart showing the on / off states of the switch elements of the square wave multipliers UB1 to UB3 and the signal synthesizer 10 in the sine wave multiplier according to the sixth embodiment.
- the fourth switch element SW4 In the forward rotation mode, the fourth switch element SW4 is always on. In the charging operation in the forward rotation mode, the third switch element SW3 is turned on, and the other switch elements except for the fourth switch element SW4 are turned off. In the charge output operation in the forward rotation mode, the tenth switch element SW10 is turned on, and the other switch elements other than the fourth switch element SW4 are turned off. On the other hand, in the inversion mode, the tenth switch element SW10 is always in the off state.
- the pair of the third switch element SW3 and the fourth switch element SW4 is turned on, and the other switch elements are turned off.
- the fifth switch element SW5 and the sixth switch element SW6 are turned on, and the other switch elements are turned off. This operation is the same as that of the second switch unit 22 in FIGS.
- FIG. 15 is a diagram illustrating an example of the configuration of the sine wave multiplication device according to the seventh embodiment.
- the sine wave multiplication device shown in FIG. 15 has an inverting amplifier circuit 60, square wave multiplication units UD1 to UD3, and a signal synthesis unit 10A.
- the inverting amplifier circuit 60 is a circuit that inverts the polarity of the input signal Si with respect to the reference potential, and inputs the result obtained by multiplying the input signal Si by the gain “ ⁇ 1” to the square wave multipliers UD1 to UD3 as the inverted input signal -Si. To do.
- the square wave multipliers UD1 to UD3 receive the input signal Si and the inverted input signal ⁇ Si, respectively, and in one half cycle of the square waves W1 to W3 that multiply the input signal Si, The output signals Sud1 to Sud3 proportional to the ratio are generated, and the output signals Sud1 to Sud3 proportional to the inverting input signal -Si at the predetermined ratio are generated in the other half cycle of the one cycle.
- any one of the square wave multipliers UD1 to UD3 is referred to as “square wave multiplier UD”, and any one of the output signals Sud1 to Sud3 is referred to as “output signal Sud”.
- An arbitrary one of the waves W1 to W3 is referred to as a “square wave W”.
- FIG. 16 is a diagram illustrating an example of the configuration of the square wave multiplication unit UD.
- a square wave multiplier UD shown in FIG. 16 includes a resistor R1, a switch element SW12, and a switch element SW13.
- the switch element SW13 is provided in a current path between one end of the resistor R1 and the input node NiX connected to the output of the inverting amplifier circuit 60.
- the switch element SW12 is provided in a current path between the one end of the resistor R1 and the input node Ni.
- the other end of the resistor R1 is connected to the output node Nc. In one half cycle of the square wave W, the switch element SW12 is turned on and the switch element SW13 is turned off.
- the switch element SW12 is turned off and the switch element SW13 is turned on.
- the operation mode during the half cycle of the square wave W in which the switch element SW12 is turned on and the switch element SW13 is turned off is referred to as a “forward rotation mode”.
- the operation mode during the other half cycle of the wave W is called “inversion mode”.
- the input node Ni is connected to the output node Nc via the resistor R1. Since the output node Nc is maintained at a reference potential by a signal synthesis unit 10A described later, the current output from the square wave multiplication unit UD to the signal synthesis unit 10A has a value proportional to the voltage of the input signal Si. The ratio of the output current to the voltage of the input signal Si is the conductivity of the resistor R1.
- the input node NiX is connected to the output node Nc via the resistor R1. Also in this case, since the output node Nc is kept at the reference potential, the current output from the square wave multiplier UD to the signal synthesizer 10A has a value proportional to the voltage of the inverted input signal -Si. The ratio of the output current to the voltage of the inverting input signal -Si is the conductivity of the resistor R1.
- Square wave multiplier UD1 (hereinafter referred to as “first square wave multiplier UD1”) is a square wave W1 having a sine wave of frequency fs as a fundamental wave (hereinafter referred to as “first square wave W1”). Is multiplied by the input signal Si. The frequency of the first square wave W1 is “fs”, and the amplitude is “A”.
- the square wave multipliers UD2 and UD3 (hereinafter referred to as “second square wave multiplier U2” and “second square wave multiplier UD3”) include third harmonics included in the first square wave W1 having the frequency fs.
- Second square wave W2 Square waves W2 and W3 (hereinafter referred to as “second square wave W2” and “second square wave W3”) having sine waves obtained by inverting the phase of the fifth harmonic as fundamental waves, respectively. Multiply by.
- the frequency of the second square wave W2 is “3fs” and the amplitude is “A / 3”, the frequency of the second square wave W3 is “5fs”, and the amplitude is “A / 5”.
- the conductivity of the resistor R1 in the first square wave multiplier UD1 is “Yu1”
- the conductivity of the resistor R1 in the second square wave multiplier UD2 is “Yu2”
- the conductivity of the resistor R1 in the third square wave multiplier UD3 is Assuming “Yu3”, these electrical conductivities are set to a ratio represented by the following equation.
- the amplitude of the current component corresponding to the third harmonic of the first square wave W1 included in the output current of the first square wave multiplier UD1 becomes equal.
- the amplitude of the current component corresponding to the fifth harmonic of the first square wave W1 included in the output current of the first square wave multiplier UD1 becomes equal.
- the amplitude of the current component corresponding to the fifth harmonic of the first square wave W1 included in the output current of the first square wave multiplier UD1 and the second included in the output current of the second square wave multiplier UD3.
- the amplitude of the current component corresponding to the fundamental wave of the square wave W3 becomes equal.
- the signal synthesis unit 10A generates an output signal So corresponding to the sum of the currents output from the square wave multiplication units UD1 to UD3.
- the signal synthesis unit 10A includes a resistor R3 and an amplifier circuit OP2.
- the resistor R3 is connected between the output node Nc and the output of the amplifier circuit OP2.
- the amplifier circuit OP2 controls the output voltage at one end of the resistor R3 so that the output node Nc becomes equal to the reference potential.
- the amplifier circuit OP2 is an operational amplifier, for example, and has an inverting input terminal connected to the output node Nc and a non-inverting input terminal connected to a reference potential.
- FIG. 17 is a timing chart showing the on / off states of the switch elements of the square wave multipliers UD1 to UD3.
- the first square wave multiplication unit UD1 performs one cycle multiplication of the first square wave W1 composed of the normal mode and the inversion mode
- the second square wave multiplication unit UD2 performs the second square shape.
- the wave W2 is multiplied by 3 cycles
- the second square wave multiplier UD3 multiplies the second square wave W3 by 5 cycles.
- the first square wave multiplication unit UD1 starts the forward rotation mode of the first square wave W1
- the second square wave multiplication unit UD2 starts the inversion mode of the second square wave W2, and the second square wave multiplication.
- the inversion mode of the second square wave W3 is started. Therefore, the fundamental wave of the second square wave W2 has an opposite phase to the third harmonic of the first square wave W1, and the fundamental wave of the second square wave W3 becomes the fifth harmonic of the first square wave W1.
- the current component corresponding to the third harmonic of the first square wave W1 included in the output current of the first square wave multiplier UD1 is the second square wave included in the output current of the second square wave multiplier UD2.
- the current component corresponding to the fifth harmonic of the first square wave W1 included in the output current of the first square wave multiplier UD1 is the second square wave included in the output current of the second square wave multiplier UD3. It is canceled out by the current component corresponding to the fundamental wave of W3.
- the input signal Si and the sine wave can be accurately multiplied with a simple configuration as in the embodiments described above.
- the input device is an input device such as a touch sensor that inputs information according to the proximity of an object, and includes a sensor unit 110, a selection unit 120, a detection signal generation unit 130, 1 sine wave multiplication unit 140, second sine wave multiplication unit 150, and low-pass filter 160 are provided.
- the sensor unit 110 includes a sensor element whose capacitance changes in accordance with the proximity of an object.
- the sensor unit 110 includes electrodes ES1 to ESn that form capacitors with the object.
- an object such as a fingertip
- the capacitance of the capacitor formed between the electrodes ES1 to ESn and the object changes.
- the selection unit 120 selects one of the electrodes ES1 to ESn in the sensor unit 110 and connects it to the input of the detection signal generation unit 130.
- the detection signal generation unit 130 applies a sine wave drive voltage corresponding to the first sine wave supplied by the first sine wave multiplication unit 140 to the electrodes (ES1 to ESn) of the sensor unit 110 selected by the selection unit 120. And a detection signal Sn corresponding to the current flowing in the electrode is generated by applying the drive voltage.
- the detection signal generation unit 130 includes an operational amplifier OP3, a capacitor Cf, and a subtracter 131, for example, as shown in FIG.
- the capacitor Cf is connected between the inverting input terminal and the output terminal of the operational amplifier OP3.
- the first sine wave of the first sine wave multiplier 140 is input to the non-inverting input terminal of the operational amplifier OP3.
- the subtracter 131 subtracts the first sine wave from the output signal of the operational amplifier OP3 and outputs the subtraction result as the detection signal Sn.
- the detection signal Sn is a signal that vibrates at the same frequency fs as the first sine wave, and the amplitude thereof is proportional to the capacitance formed between the electrode of the sensor unit 110 and the object (fingertip).
- the first sine wave multiplication unit 140 is a circuit that multiplies a DC signal by a sine wave having a frequency fs and outputs a first sine wave having a predetermined frequency as a result of the multiplication.
- the first sine wave multiplication device shown in FIG. It has the same configuration as.
- the second sine wave multiplication unit 150 is a circuit that multiplies the detection signal Sn generated by the detection signal generation unit 130 by the second sine wave having the frequency fs.
- the second sine wave multiplication unit 150 has the same configuration as the sine wave multiplication device shown in FIG. Have
- the low-pass filter 160 extracts a DC component signal Da from the signal Ds obtained as a multiplication result of the second sine wave multiplication unit 150.
- the second sine wave multiplier 150 and the low-pass filter 160 operate as a narrow-band band-pass filter that extracts a signal component of the frequency fs included in the detection signal Sn.
- the DC component signal Da has a level corresponding to the amplitude of the signal component of the frequency fs included in the detection signal Sn, and is an electrostatic capacitance formed between the electrode of the sensor unit 110 and the object (fingertip). Is proportional to
- the first sine wave multiplication unit 140 and the second sine wave multiplication unit 150 having a simple configuration are used to detect capacitance with high accuracy from which the influence of external noise has been removed. A value can be obtained.
- the phase of the fundamental wave of the second square wave W2, W3 multiplied by the input signal Si in the second square wave multiplier U2, U3 is changed to the phase of the harmonic wave in the first square wave W1.
- the present invention is not limited to this example.
- the phase of the fundamental wave of the second square waves W2, W3 multiplied by the input signal Si in the second square wave multipliers U2, U3 is changed to the first square wave. You may make it become the same phase as the phase of the harmonic in W1.
- the signal combining unit 10 combines the signals so as to subtract the output signals Su2 and Su3 of the second square wave multipliers U2 and U3 from the output signal Su1 of the first square wave multiplier U1.
- the harmonic component can be canceled as in the sine wave multiplier shown in FIG.
- the signal components corresponding to the third harmonic and the fifth harmonic in the first square wave W1 are canceled by the signal components corresponding to the fundamental waves of the second square waves W2 and W3.
- the present invention is not limited to this example.
- the number of square wave multipliers may be three or more so that signal components corresponding to higher harmonics can be canceled.
- square wave multiplication processing and multiplication result synthesis processing are performed by analog circuits.
- these signal processing may be performed by digital signal processing.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Amplifiers (AREA)
Abstract
Description
上記正弦波乗算装置では、前記方形波乗算部を用いて正弦波(前記第1方形波の前記基本波)と前記入力信号との乗算を行うため、アナログ乗算器のようにトランジスタの温度特性の影響を受け難くなり、温度による特性の変動が少ない。また、前記方形波乗算部を用いることによって、アナログ乗算器のようにトランジスタの入出力非線形特性の影響を受け難くなるため、入力信号のレベルの範囲が広くなる。
更に、上記正弦波乗算装置では、前記方形波乗算部を用いることによって正弦波発生器を省略できることから、回路構成が簡易となる。 According to the above configuration, a signal component corresponding to a product of at least one harmonic of the first square wave and the input signal included in the output signal of the first square wave multiplier is the second square wave. The signal is canceled by a signal component corresponding to the product of the fundamental wave of the second square wave and the input signal included in the output signal of the wave multiplier. Therefore, in the signal resulting from the synthesis by the signal synthesis unit, the signal component corresponding to the product of the harmonic of the first square wave and the input signal is reduced, and the fundamental wave of the first square wave (the A signal component corresponding to a product of a sine wave having a predetermined frequency and the input signal becomes a dominant component.
In the sine wave multiplication device, the square wave multiplication unit is used to multiply the sine wave (the fundamental wave of the first square wave) and the input signal. Less susceptible to fluctuations, and changes in characteristics due to temperature are small. Further, the use of the square wave multiplication unit makes it difficult to be affected by the input / output nonlinear characteristics of the transistor as in the case of an analog multiplier, so that the range of the level of the input signal is widened.
Further, in the sine wave multiplication device, the sine wave generator can be omitted by using the square wave multiplication unit, so that the circuit configuration is simplified.
これにより、前記方形波乗算部では、前記入力信号に乗算する方形波の1周期中における一方の半周期と他方の半周期とで、前記入力信号と前記出力信号との比の絶対値が等しく、かつ、当該比の符号が反転するように前記出力信号が生成される。すなわち、前記入力信号に対する前記出力信号の比の絶対値を保ったまま、その正負の符号を方形波の半周期ごとに反転することで、前記入力信号と方形波の乗算が行われる。そのため、アナログ乗算器のようにトランジスタの温度特性や入出力非線形特性の影響を受け難くなる。 Preferably, the square wave multiplication unit generates an output signal proportional to the input signal in each of one half cycle and the other half cycle in one cycle of the square wave multiplied by the input signal, and The output signal may be generated such that the absolute value of the ratio between the input signal and the output signal is equal in one half cycle and the other half cycle, and the sign of the ratio is inverted.
Thereby, in the square wave multiplication unit, the absolute value of the ratio between the input signal and the output signal is the same in one half cycle and the other half cycle in one cycle of the square wave multiplied by the input signal. The output signal is generated so that the sign of the ratio is inverted. That is, the input signal and the square wave are multiplied by inverting the sign of each square wave half cycle while maintaining the absolute value of the ratio of the output signal to the input signal. Therefore, unlike an analog multiplier, it is difficult to be influenced by the temperature characteristics and input / output nonlinear characteristics of the transistor.
また、前記キャパシタの静電容量比は、温度や製造プロセスによるばらつきの影響を受け難いため、上記信号成分の相殺を精度よく行うことが可能となる。 According to the above configuration, the ratio of the charge output from the first square wave multiplication unit and the charge output from the second square wave multiplication unit in the charge output operation is equal to that of the first square wave multiplication unit. It has a value corresponding to the ratio between the capacitance of the capacitor and the capacitance of the capacitor of the second square wave multiplier. And the ratio of the capacitance is the amplitude of the fundamental wave of the first square wave and the amplitude of the harmonic wave of the first square wave having the same frequency as the fundamental wave of the second square wave. It has a value according to the ratio. Therefore, the signal output from the first square wave multiplication unit and the charge output from the second square wave multiplication unit are added together in the signal synthesis unit, so that the harmonics of the first square wave and the The signal component corresponding to the product of the input signal can be canceled by the signal component corresponding to the product of the fundamental wave of the second square wave and the input signal.
Further, since the capacitance ratio of the capacitor is hardly affected by variations due to temperature and manufacturing process, the signal components can be accurately canceled.
前記方形波乗算部は、第1キャパシタ及び第2キャパシタと、前記入力信号に乗算する前記方形波の1周期中における一方の半周期において、前記第1キャパシタの一端を前記入力ノードに接続するとともに前記第1キャパシタの他端を基準電位に接続する充電動作、及び、前記第1キャパシタの前記一端を前記出力ノードに接続するとともに前記第1キャパシタの前記他端を前記基準電位に接続する電荷出力動作を前記サンプリング周期で交互に反復する第1スイッチ部と、前記入力信号に乗算する前記方形波の1周期中における他方の半周期において、前記第2キャパシタの一端を前記入力ノードに接続するとともに前記第2キャパシタの他端を前記基準電位に接続する充電動作、及び、前記第2キャパシタの前記他端を前記出力ノードに接続するとともに前記第2キャパシタの前記一端を前記基準電位に接続する電荷出力動作を前記サンプリング周期で交互に反復する第2スイッチ部とを有してよい。
前記信号合成部は、一方の端子が前記出力ノードに接続された第3キャパシタと、前記出力ノードと前記基準電位との電圧差がゼロとなるように前記第3キャパシタの他方の端子の電圧を制御するアンプ回路と、前記複数の方形波乗算部において所定回数の前記電荷出力動作が行われる度に、前記第3キャパシタに蓄積される電荷を放電する放電回路とを有してよい。 Preferably, the sine wave multiplier may include an input node to which the input signal is input and an output node to which outputs of the plurality of square wave multipliers are connected in common.
The square wave multiplication unit connects one end of the first capacitor to the input node in one half cycle of the first capacitor and the second capacitor, and one cycle of the square wave multiplied by the input signal. A charge operation for connecting the other end of the first capacitor to a reference potential; and a charge output for connecting the one end of the first capacitor to the output node and for connecting the other end of the first capacitor to the reference potential. In the first switch unit that alternately repeats the operation in the sampling period, and in the other half cycle of the square wave that multiplies the input signal, one end of the second capacitor is connected to the input node. A charging operation for connecting the other end of the second capacitor to the reference potential; and the other end of the second capacitor connected to the output node. May have a second switch section for repeating the charge output operation for connecting said one end of said second capacitor to said reference potential alternately at the sampling period with connecting.
The signal synthesizer sets the voltage at the other terminal of the third capacitor so that a voltage difference between the third capacitor having one terminal connected to the output node and the output node and the reference potential is zero. An amplifier circuit to be controlled and a discharge circuit that discharges the charge accumulated in the third capacitor each time the charge output operation is performed a predetermined number of times in the plurality of square wave multipliers.
前記第1キャパシタの前記他端が前記基準電位に接続されてよい。
前記第2スイッチ部は、前記入力ノードと前記第2キャパシタの前記一端との間の電流経路に設けられた第3スイッチ素子と、前記第2キャパシタの前記他端と前記基準電位との間の電流経路に設けられた第4スイッチ素子と、前記第2キャパシタの前記他端と前記出力ノードとの間の電流経路に設けられた第5スイッチ素子と、前記第2キャパシタの前記一端と前記基準電位との間の電流経路に設けられた第6スイッチ素子とを含んでよい。
前記入力信号に乗算する前記方形波の1周期中における一方の半周期では、前記充電動作の際に前記第1スイッチ素子がオンするとともに他の前記スイッチ素子がオフし、前記電荷出力動作の際に前記第2スイッチ素子がオンするとともに他の前記スイッチ素子がオフしてよい。
前記入力信号に乗算する前記方形波の1周期中における他方の半周期では、前記充電動作の際に前記第3スイッチ素子及び前記第4スイッチ素子がオンするとともに他の前記スイッチ素子がオフし、前記電荷出力動作の際に前記第5スイッチ素子及び前記第6スイッチ素子がオンするとともに他の前記スイッチ素子がオフしてよい。 Preferably, the first switch unit includes a first switch element provided in a current path between the input node and the one end of the first capacitor, and the one end of the first capacitor and the output node. And a second switch element provided in a current path therebetween.
The other end of the first capacitor may be connected to the reference potential.
The second switch unit includes a third switch element provided in a current path between the input node and the one end of the second capacitor, and between the other end of the second capacitor and the reference potential. A fourth switch element provided in a current path, a fifth switch element provided in a current path between the other end of the second capacitor and the output node, the one end of the second capacitor, and the reference And a sixth switch element provided in a current path between the potential.
In one half cycle of the square wave multiplied by the input signal, the first switch element is turned on and the other switch elements are turned off during the charging operation, and the charge output operation is performed. In addition, the second switch element may be turned on and the other switch elements may be turned off.
In the other half cycle of the square wave multiplied by the input signal, the third switch element and the fourth switch element are turned on and the other switch elements are turned off during the charging operation. During the charge output operation, the fifth switch element and the sixth switch element may be turned on and the other switch elements may be turned off.
前記第1スイッチ部は、前記第4キャパシタの一端と前記入力ノードとの間の電流経路に設けられた第7スイッチ素子と、前記第4キャパシタの前記一端と前記基準電位との間の電流経路に設けられた第8スイッチ素子と、前記第4キャパシタの他端と前記基準電位との間の電流経路に設けられた第9スイッチ素子とを含んでよい。
前記第7スイッチ素子は、前記第1スイッチ素子と同じ条件でオンオフしてよい。
前記第8スイッチ素子及び前記第9スイッチ素子は、前記第2スイッチ素子と同じ条件でオンオフしてよい。 The square wave multiplication unit may include a fourth capacitor provided in a current path between the first switch element and the input node.
The first switch unit includes a seventh switch element provided in a current path between one end of the fourth capacitor and the input node, and a current path between the one end of the fourth capacitor and the reference potential. And an ninth switch element provided in a current path between the other end of the fourth capacitor and the reference potential.
The seventh switch element may be turned on / off under the same conditions as the first switch element.
The eighth switch element and the ninth switch element may be turned on / off under the same conditions as the second switch element.
これにより、前記信号合成部において生成される信号中の前記折り返し雑音が低減する。 Preferably, the sine wave multiplier is a noise component included in the input signal input to the plurality of square wave multipliers, from a frequency that is an integral multiple of the sampling frequency to the signal band of the input signal. A first low-pass filter that attenuates the noise component that may cause aliasing noise may be provided.
Thereby, the aliasing noise in the signal generated in the signal synthesis unit is reduced.
例えば、前記方形波乗算部は、前記入力信号に乗算する方形波の1周期における一方の半周期において、前記入力信号の電圧に所定の比率で比例した出力電流を生成し、当該1周期における他方の半周期において、前記反転入力信号の電圧に前記所定の比率で比例した出力電流を生成してよい。前記信号合成部は、前記複数の方形波乗算部から出力される前記出力電流の和に応じた信号を生成してよい。 Preferably, the square wave multiplication unit inputs the input signal and an inverted input signal in which the polarity of the input signal is inverted, and in one half cycle of one cycle of the square wave to multiply the input signal, the input An output signal proportional to the signal at a predetermined ratio may be generated, and an output signal proportional to the inverted input signal at the predetermined ratio may be generated in the other half cycle of the one cycle.
For example, the square wave multiplier generates an output current proportional to the voltage of the input signal at a predetermined ratio in one half cycle of the square wave multiplied by the input signal, and the other in the one cycle. In this half cycle, an output current proportional to the voltage of the inverted input signal at the predetermined ratio may be generated. The signal synthesis unit may generate a signal corresponding to the sum of the output currents output from the plurality of square wave multiplication units.
これにより、前記信号合成部において生成される信号において、前記第1方形波の前記高調波に対応した信号成分が低減する。 Preferably, the sine wave multiplication device has N patterns of the second squares corresponding to the first to Nth harmonics in order of decreasing frequency among the harmonics included in the first square wave. N harmonic wave multipliers for multiplying the input signal by a wave, and the harmonics included in the first square wave from signals output as a result of synthesis in the signal synthesis unit, the frequency being the frequency There may be a second low-pass filter that attenuates the (N + 1) th and higher harmonics in order of increasing.
Thereby, the signal component corresponding to the harmonics of the first square wave is reduced in the signal generated in the signal synthesis unit.
図4は、本発明の第1の実施形態に係る正弦波乗算装置の構成の一例を示す図である。図1に示す正弦波乗算装置は、それぞれ異なる周波数の方形波W1,W2,W3を入力信号Siに乗算する3つの方形波乗算部U1,U2,U3と、当該方形波乗算部U1,U2,U3の出力信号Su1,Su2,Su3を合成する信号合成部10を有する。以下、方形波乗算部U1~U3の任意の1つを「方形波乗算部U」と記し、出力信号Su1~Su3の任意の1つを「出力信号Su」と記し、方形波W1~W3の任意の1つを「方形波W」と記す。 <First Embodiment>
FIG. 4 is a diagram illustrating an example of the configuration of the sine wave multiplier according to the first embodiment of the present invention. The sine wave multiplier shown in FIG. 1 includes three square wave multipliers U1, U2, and U3 that multiply square signals W1, W2, and W3 having different frequencies by an input signal Si, and the square wave multipliers U1, U2, and U3. A
すなわち、第2方形波乗算部U2は、第1方形波W1における第3次高調波の位相を反転させた正弦波を基本波とする第2方形波W2を入力信号Siに乗算する。図4において示すように、この第2方形波W2の周波数は「3fs」、振幅は「A/3」である。
また、第2方形波乗算部U3は、第1方形波W1における第5次高調波の位相を反転させた正弦波を基本波とする第2方形波W3を入力信号Siに乗算する。図4において示すように、この第2方形波W3の周波数は「5fs」、振幅は「A/5」である。 Square wave multipliers U2 and U3 (hereinafter referred to as “second square wave multiplier U2” and “second square wave multiplier U3”) are used to generate one harmonic wave included in first square wave W1 having frequency fs. Square waves W2 and W3 (hereinafter referred to as “second square wave W2” and “second square wave W3”) having sine waves with inverted phases as fundamental waves are respectively multiplied by the input signal Si.
That is, the second square wave multiplication unit U2 multiplies the input signal Si by a second square wave W2 having a sine wave obtained by inverting the phase of the third harmonic in the first square wave W1 as a fundamental wave. As shown in FIG. 4, the frequency of the second square wave W2 is “3fs” and the amplitude is “A / 3”.
The second square wave multiplication unit U3 multiplies the input signal Si by a second square wave W3 having a sine wave obtained by inverting the phase of the fifth harmonic in the first square wave W1 as a fundamental wave. As shown in FIG. 4, the frequency of the second square wave W3 is “5fs” and the amplitude is “A / 5”.
次に、第2の実施形態として、図4に示す正弦波乗算装置のより詳細な構成の一例を説明する。 <Second Embodiment>
Next, an example of a more detailed configuration of the sine wave multiplier shown in FIG. 4 will be described as a second embodiment.
Cu1:Cu2 = 1:1/3 …(1) [Equation 1]
Cu1: Cu2 = 1: 1/3 (1)
Cu1:Cu3 = 1:1/5 …(2) [Equation 2]
Cu1: Cu3 = 1: 1/5 (2)
Cu1:Cu2:Cu3 = 1:1/3:1/5 = 15:5:3 …(3) [Equation 3]
Cu1: Cu2: Cu3 = 1: 1/3: 1/5 = 15: 5: 3 (3)
第1キャパシタC1の充電動作を行う場合、第1スイッチ部21は、第1キャパシタC1の一端を入力ノードNiに接続するとともに第1キャパシタC1の他端を基準電位に接続する。第1キャパシタC2の電荷出力動作を行う場合、第1スイッチ部21は、第1キャパシタC1の前記一端を出力ノードNcに接続するとともに第1キャパシタC1の前記他端を基準電位に接続する。第1スイッチ部21は、この充電動作と電荷出力動作を、サンプリング周期Tで交互に反復する。 The
When performing the charging operation of the first capacitor C1, the
第2キャパシタC2の充電動作を行う場合、第2スイッチ部22は、第2キャパシタC2の一端を入力ノードNiに接続するとともに第2キャパシタC2の他端を基準電位に接続する。第2キャパシタC2の電荷出力動作を行う場合、第2スイッチ部22は、第2キャパシタC2の前記他端を出力ノードNcに接続するとともに第2キャパシタC2の前記一端を基準電位に接続する。第2スイッチ部22は、この充電動作と電荷出力動作をサンプリング周期Tで交互に反復する。 The
When performing the charging operation of the second capacitor C2, the
第1スイッチ部21が動作する方形波Wの一方の半周期では、第1スイッチ素子SW1と第2スイッチ素子SW2が交互にオンする。すなわち、第1キャパシタC1の充電動作が行われる場合、第1スイッチ素子SW1がオンするとともに他のスイッチ素子がオフする。第2キャパシタC2の電荷出力動作が行われる場合、第2スイッチ素子SW2がオンするとともに他のスイッチ素子がオフする。
第2スイッチ部22が動作する方形波Wの他方の半周期では、第3スイッチ素子SW3及び第4スイッチ素子SW4のペアと第5スイッチ素子SW5及び第6スイッチ素子SW6のペアとが交互にオンする。すなわち、第2キャパシタC2の充電動作が行われる場合、第3スイッチ素子SW3及び第4スイッチ素子SW4のペアが共にオンするとともに他のスイッチ素子がオフする。第2キャパシタC2の電荷出力動作が行われる場合、第5スイッチ素子SW5及び第6スイッチ素子SW6のペアが共にオンするとともに他のスイッチ素子がオフする。 The switch elements of the
In one half cycle of the square wave W in which the
In the other half cycle of the square wave W in which the
次に、本発明の第3の実施形態について説明する。
第3の実施形態に係る正弦波乗算装置は、第2の実施形態に係る正弦波乗算装置における方形波乗算部U1~U3を、図8に示す方形波乗算部UA1~UA3に置き換えたものであり、他の構成は第2の実施形態に係る正弦波乗算装置と同じである。 <Third Embodiment>
Next, a third embodiment of the present invention will be described.
The sine wave multiplier according to the third embodiment is obtained by replacing the square wave multipliers U1 to U3 in the sine wave multiplier according to the second embodiment with square wave multipliers UA1 to UA3 shown in FIG. In other respects, the configuration is the same as that of the sine wave multiplier according to the second embodiment.
第4キャパシタC4は、第1スイッチ素子SW1と入力ノードNiとの間の電流経路に設けられる。第7スイッチ素子SW7は、第4キャパシタC4の一端と入力ノードNiとの間の電流経路に設けられる。第8スイッチ素子SW8は、第4キャパシタC4の前記一端と基準電位との間の電流経路に設けられる。第9スイッチ素子SW9は、第4キャパシタC4の他端と基準電位との間に設けられる。 The
The fourth capacitor C4 is provided in the current path between the first switch element SW1 and the input node Ni. The seventh switch element SW7 is provided in a current path between one end of the fourth capacitor C4 and the input node Ni. The eighth switch element SW8 is provided in a current path between the one end of the fourth capacitor C4 and a reference potential. The ninth switch element SW9 is provided between the other end of the fourth capacitor C4 and the reference potential.
図9において示すように、第7スイッチ素子SW7は、第1スイッチ素子SW1と同じ条件でオンオフする。また、第8スイッチ素子SW8及び第9スイッチ素子SW9は、第2スイッチ素子SW2と同じ条件でオンオフする。他のスイッチ素子の動作は、図7に示すタイミング図と同じである。 FIG. 9 is a timing chart showing the on / off states of the switch elements of the square wave multipliers (UA1 to UA3) and the
As shown in FIG. 9, the seventh switch element SW7 is turned on / off under the same conditions as the first switch element SW1. The eighth switch element SW8 and the ninth switch element SW9 are turned on / off under the same conditions as the second switch element SW2. The operation of the other switch elements is the same as the timing chart shown in FIG.
次に、本発明の第4の実施形態について説明する。
図10は、第4の実施形態に係る正弦波乗算装置の構成の一例を示す図である。図10に示す正弦波乗算装置は、第2及び第3の実施形態に係る正弦波乗算装置(図5)に第1ローパスフィルタ30を設けたものであり、他の構成は第2及び第3の実施形態に係る正弦波乗算装置と同じである。 <Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described.
FIG. 10 is a diagram illustrating an example of the configuration of the sine wave multiplication device according to the fourth embodiment. The sine wave multiplier shown in FIG. 10 is obtained by providing the first low-
次に、本発明の第5の実施形態について説明する。
図12は、第5の実施形態に係る正弦波乗算装置の構成の一例を示す図である。図12に示す正弦波乗算装置は、第2及び第3の実施形態に係る正弦波乗算装置(図5)にローパスフィルタ50を設け、入力信号Siを直流電圧VDDとしたものであり、他の構成は第2及び第3の実施形態に係る正弦波乗算装置と同じである。 <Fifth Embodiment>
Next, a fifth embodiment of the present invention will be described.
FIG. 12 is a diagram illustrating an example of the configuration of the sine wave multiplier according to the fifth embodiment. The sine wave multiplier shown in FIG. 12 has a low-
このように、本実施形態に係る正弦波乗算装置は、精度の高い正弦波発生回路として動作させることも可能である。 In the sine wave multiplier shown in FIG. 12, since the input signal Si is the DC voltage VDD, the output signal So is a signal obtained by multiplying the DC voltage VDD and the sine wave, that is, a sine wave. The sine wave multiplier shown in FIG. 10 converts the signal component of frequency fs into a direct current component. However, since the sine wave multiplier shown in FIG. 12 generates a signal of frequency fs from the direct current component, the input / output relationship. Is reversed. Therefore, the low-
Thus, the sine wave multiplication device according to the present embodiment can be operated as a highly accurate sine wave generation circuit.
次に、本発明の第6の実施形態について説明する。
図13は、第6の実施形態に係る正弦波乗算装置における方形波乗算部UB1~UB3の構成の一例を示す図である。第3の実施形態に係る正弦波乗算装置は、第2の実施形態に係る正弦波乗算装置における方形波乗算部U1~U3を、図13に示す方形波乗算部UB1~UB3に置き換えたものであり、他の構成は第2の実施形態に係る正弦波乗算装置と同じである。 <Sixth Embodiment>
Next, a sixth embodiment of the present invention will be described.
FIG. 13 is a diagram illustrating an example of the configuration of the square wave multipliers UB1 to UB3 in the sine wave multiplier according to the sixth embodiment. The sine wave multiplier according to the third embodiment is obtained by replacing the square wave multipliers U1 to U3 in the sine wave multiplier according to the second embodiment with square wave multipliers UB1 to UB3 shown in FIG. In other respects, the configuration is the same as that of the sine wave multiplier according to the second embodiment.
正転モードでは、第4スイッチ素子SW4が常にオン状態となる。正転モードの充電動作において、第3スイッチ素子SW3がオンし、第4スイッチ素子SW4を除く他のスイッチ素子がオフする。正転モードの電荷出力動作においては、第10スイッチ素子SW10がオンし、第4スイッチ素子SW4を除く他のスイッチ素子がオフする。
一方、反転モードでは、第10スイッチ素子SW10が常にオフ状態となる。反転モードの充電動作において、第3スイッチ素子SW3及び第4スイッチ素子SW4のペアがオンし、他のスイッチ素子がオフする。反転モードの電荷出力動作において、第5スイッチ素子SW5及び第6スイッチ素子SW6がオンし、他のスイッチ素子がオフする。この動作は、図6,図8における第2スイッチ部22と同じである。 FIG. 14 is a timing chart showing the on / off states of the switch elements of the square wave multipliers UB1 to UB3 and the
In the forward rotation mode, the fourth switch element SW4 is always on. In the charging operation in the forward rotation mode, the third switch element SW3 is turned on, and the other switch elements except for the fourth switch element SW4 are turned off. In the charge output operation in the forward rotation mode, the tenth switch element SW10 is turned on, and the other switch elements other than the fourth switch element SW4 are turned off.
On the other hand, in the inversion mode, the tenth switch element SW10 is always in the off state. In the charging operation in the inversion mode, the pair of the third switch element SW3 and the fourth switch element SW4 is turned on, and the other switch elements are turned off. In the charge output operation in the inversion mode, the fifth switch element SW5 and the sixth switch element SW6 are turned on, and the other switch elements are turned off. This operation is the same as that of the
次に、本発明の第7の実施形態について説明する。
図15は、第7の実施形態に係る正弦波乗算装置の構成の一例を示す図である。図15に示す正弦波乗算装置は、反転アンプ回路60と、方形波乗算部UD1~UD3と、信号合成部10Aを有する。 <Seventh Embodiment>
Next, a seventh embodiment of the present invention will be described.
FIG. 15 is a diagram illustrating an example of the configuration of the sine wave multiplication device according to the seventh embodiment. The sine wave multiplication device shown in FIG. 15 has an inverting
以下、本実施形態では、方形波乗算部UD1~UD3の任意の1つを「方形波乗算部UD」と記し、出力信号Sud1~Sud3の任意の1つを「出力信号Sud」と記し、方形波W1~W3の任意の1つを「方形波W」と記す。 The square wave multipliers UD1 to UD3 receive the input signal Si and the inverted input signal −Si, respectively, and in one half cycle of the square waves W1 to W3 that multiply the input signal Si, The output signals Sud1 to Sud3 proportional to the ratio are generated, and the output signals Sud1 to Sud3 proportional to the inverting input signal -Si at the predetermined ratio are generated in the other half cycle of the one cycle.
Hereinafter, in the present embodiment, any one of the square wave multipliers UD1 to UD3 is referred to as “square wave multiplier UD”, and any one of the output signals Sud1 to Sud3 is referred to as “output signal Sud”. An arbitrary one of the waves W1 to W3 is referred to as a “square wave W”.
スイッチ素子SW13は、抵抗R1の一端と、反転アンプ回路60の出力につながる入力ノードNiXとの間の電流経路に設けられる。スイッチ素子SW12は、抵抗R1の前記一端と入力ノードNiとの間の電流経路に設けられる。抵抗R1の他端は、出力ノードNcに接続される。方形波Wの1周期における一方の半周期においてスイッチ素子SW12がオン、スイッチ素子SW13がオフし、他方の半周期においてスイッチ素子SW12がオフ、スイッチ素子SW13がオンする。
以下、本実施形態では、スイッチ素子SW12がオン、スイッチ素子SW13がオフする方形波Wの半周期間の動作モードを「正転モード」と呼び、スイッチ素子SW12がオフ、スイッチ素子SW13がオンする方形波Wの他の半周期間の動作モードを「反転モード」と呼ぶ。 FIG. 16 is a diagram illustrating an example of the configuration of the square wave multiplication unit UD. A square wave multiplier UD shown in FIG. 16 includes a resistor R1, a switch element SW12, and a switch element SW13.
The switch element SW13 is provided in a current path between one end of the resistor R1 and the input node NiX connected to the output of the inverting
Hereinafter, in the present embodiment, the operation mode during the half cycle of the square wave W in which the switch element SW12 is turned on and the switch element SW13 is turned off is referred to as a “forward rotation mode”. The operation mode during the other half cycle of the wave W is called “inversion mode”.
方形波乗算部UD2,UD3(以下、「第2方形波乗算部U2」「第2方形波乗算部UD3」と記す。)は、周波数fsの第1方形波W1に含まれる第3次高調波,第5次高調波の位相を反転させた正弦波を基本波とする方形波W2、W3(以下、「第2方形波W2」「第2方形波W3」と記す。)をそれぞれ入力信号Siに乗算する。第2方形波W2の周波数は「3fs」、振幅は「A/3」であり、第2方形波W3の周波数は「5fs」、振幅は「A/5」である。 Square wave multiplier UD1 (hereinafter referred to as “first square wave multiplier UD1”) is a square wave W1 having a sine wave of frequency fs as a fundamental wave (hereinafter referred to as “first square wave W1”). Is multiplied by the input signal Si. The frequency of the first square wave W1 is “fs”, and the amplitude is “A”.
The square wave multipliers UD2 and UD3 (hereinafter referred to as “second square wave multiplier U2” and “second square wave multiplier UD3”) include third harmonics included in the first square wave W1 having the frequency fs. , Square waves W2 and W3 (hereinafter referred to as “second square wave W2” and “second square wave W3”) having sine waves obtained by inverting the phase of the fifth harmonic as fundamental waves, respectively. Multiply by. The frequency of the second square wave W2 is “3fs” and the amplitude is “A / 3”, the frequency of the second square wave W3 is “5fs”, and the amplitude is “A / 5”.
Yu1:Yu2:Yu3 = 15:5:3 …(4) [Equation 4]
Yu1: Yu2: Yu3 = 15: 5: 3 (4)
図17において示すように、第1方形波乗算部UD1において正転モードと反転モードからなる第1方形波W1の1サイクルの乗算が行われる間に、第2方形波乗算部UD2では第2方形波W2の3サイクルの乗算が行われ、第2方形波乗算部UD3では第2方形波W3の5サイクルの乗算が行われる。 FIG. 17 is a timing chart showing the on / off states of the switch elements of the square wave multipliers UD1 to UD3.
As shown in FIG. 17, while the first square wave multiplication unit UD1 performs one cycle multiplication of the first square wave W1 composed of the normal mode and the inversion mode, the second square wave multiplication unit UD2 performs the second square shape. The wave W2 is multiplied by 3 cycles, and the second square wave multiplier UD3 multiplies the second square wave W3 by 5 cycles.
次に、本発明の第8の実施形態に係る入力装置について、図18を参照して説明する。 <Eighth Embodiment>
Next, an input device according to an eighth embodiment of the invention will be described with reference to FIG.
Claims (12)
- 所定の周波数の正弦波を入力信号に乗算する正弦波乗算装置であって、
それぞれ異なる周波数の方形波を前記入力信号に乗算する複数の方形波乗算部と、
前記複数の方形波乗算部の出力信号を合成する信号合成部とを備え、
前記方形波は、最も周波数が低い正弦波である基本波と、前記基本波に対してそれぞれ整数倍の周波数を持つ正弦波である複数の高調波との和として近似可能であり、
前記複数の方形波乗算部は、1つの第1方形波乗算部と1つ又は複数の第2方形波乗算部とを含み、
前記第1方形波乗算部は、前記所定の周波数の正弦波を前記基本波とする第1方形波を前記入力信号に乗算し、
前記第2方形波乗算部は、前記第1方形波に含まれる1つの前記高調波と等しい正弦波若しくは当該1つの高調波の位相を反転させた正弦波を前記基本波とする第2方形波を前記入力信号に乗算し、
前記信号合成部は、前記第1方形波乗算部の出力信号に含まれる前記第1方形波の少なくとも1つの前記高調波と前記入力信号との積に応じた信号成分を、前記第2方形波乗算部の出力信号に含まれる前記第2方形波の前記基本波と前記入力信号との積に応じた信号成分よって相殺する
ことを特徴とする正弦波乗算装置。 A sine wave multiplier for multiplying an input signal by a sine wave of a predetermined frequency,
A plurality of square wave multipliers for multiplying the input signal by square waves of different frequencies,
A signal synthesis unit that synthesizes output signals of the plurality of square wave multiplication units,
The square wave can be approximated as the sum of a fundamental wave that is the lowest sine wave and a plurality of harmonics that are sine waves each having an integer multiple of the fundamental wave,
The plurality of square wave multiplication units include one first square wave multiplication unit and one or more second square wave multiplication units,
The first square wave multiplication unit multiplies the input signal by a first square wave having the sine wave of the predetermined frequency as the fundamental wave,
The second square wave multiplication unit is a second square wave having the fundamental wave as a sine wave equal to one harmonic included in the first square wave or a sine wave obtained by inverting the phase of the one harmonic. Multiplied by the input signal,
The signal synthesis unit converts a signal component corresponding to a product of at least one harmonic of the first square wave included in the output signal of the first square wave multiplication unit and the input signal into the second square wave. A sine wave multiplication device characterized by canceling with a signal component corresponding to a product of the fundamental wave of the second square wave and the input signal included in an output signal of a multiplication unit. - 前記方形波乗算部は、前記入力信号に乗算する方形波の1周期中における一方の半周期と他方の半周期のそれぞれにおいて、前記入力信号に比例した出力信号を生成するとともに、当該一方の半周期と当該他方の半周期とで、前記入力信号と前記出力信号との比の絶対値が等しく、かつ、当該比の符号が反転するように前記出力信号を生成する
ことを特徴とする請求項1に記載の正弦波乗算装置。 The square wave multiplication unit generates an output signal proportional to the input signal in each of one half cycle and the other half cycle in one cycle of the square wave multiplied by the input signal, and The output signal is generated so that the absolute value of the ratio between the input signal and the output signal is equal in the period and the other half period, and the sign of the ratio is inverted. The sine wave multiplication device according to 1. - 前記方形波乗算部は、前記入力信号に乗算する前記方形波の1周期中における一方の半周期と他方の半周期のそれぞれにおいて、前記入力信号の電圧に比例した電荷を蓄積する充電動作と、前記充電動作により蓄積した前記電荷を前記信号合成部へ出力する電荷出力動作とを所定のサンプリング周期で交互に反復するとともに、当該一方の半周期と当該他方の半周期とで、前記入力信号の電圧と前記充電動作により蓄積する電荷量との比が等しく、かつ、前記信号合成部へ出力する前記電荷の極性が反転するように前記充電動作及び前記電荷出力動作を行い、
前記信号合成部は、前記複数の方形波乗算部において所定回数の前記電荷出力動作が行われる度に、当該電荷出力動作によって前記複数の方形波乗算部から出力される前記電荷の和に応じた信号を生成する
ことを特徴とする請求項2に記載の正弦波乗算装置。 The square wave multiplying unit stores a charge proportional to the voltage of the input signal in each of one half cycle and the other half cycle in one cycle of the square wave multiplied by the input signal; The charge output operation of outputting the charge accumulated by the charging operation to the signal synthesizer is alternately repeated at a predetermined sampling period, and the input signal in the half cycle and the other half cycle is repeated. The charge operation and the charge output operation are performed so that the ratio of the voltage and the amount of charge accumulated by the charge operation is equal, and the polarity of the charge output to the signal synthesis unit is inverted,
The signal synthesis unit responds to the sum of the charges output from the plurality of square wave multiplication units by the charge output operation each time the charge output operation is performed a predetermined number of times in the plurality of square wave multiplication units. The sine wave multiplication device according to claim 2, wherein a signal is generated. - 前記第1方形波乗算部及び前記第2方形波乗算部は、前記充電動作において電荷を蓄積する少なくとも1つのキャパシタを有しており、
前記第1方形波乗算部が前記充電動作において電荷を蓄積する前記キャパシタの静電容量と、前記第2方形波乗算部が前記充電動作において電荷を蓄積する前記キャパシタの静電容量との比が、前記第1方形波の前記基本波の振幅と、前記第2方形波の前記基本波と等しい周波数を有する前記第1方形波の前記高調波の振幅との比に応じた値を有する
ことを特徴とする請求項3に記載の正弦波乗算装置。 The first square wave multiplication unit and the second square wave multiplication unit have at least one capacitor that accumulates electric charge in the charging operation,
A ratio of the capacitance of the capacitor in which the first square wave multiplication unit accumulates electric charge in the charging operation to the capacitance of the capacitor in which the second square wave multiplication unit accumulates electric charge in the charging operation is A value corresponding to a ratio between the amplitude of the fundamental wave of the first square wave and the amplitude of the harmonic wave of the first square wave having the same frequency as the fundamental wave of the second square wave. The sine wave multiplication device according to claim 3, wherein - 前記入力信号が入力される入力ノードと、
前記複数の方形波乗算部の出力が共通に接続される出力ノードとを備え、
前記方形波乗算部は、
第1キャパシタ及び第2キャパシタと、
前記入力信号に乗算する前記方形波の1周期中における一方の半周期において、前記第1キャパシタの一端を前記入力ノードに接続するとともに前記第1キャパシタの他端を基準電位に接続する充電動作、及び、前記第1キャパシタの前記一端を前記出力ノードに接続するとともに前記第1キャパシタの前記他端を前記基準電位に接続する電荷出力動作を前記サンプリング周期で交互に反復する第1スイッチ部と、
前記入力信号に乗算する前記方形波の1周期中における他方の半周期において、前記第2キャパシタの一端を前記入力ノードに接続するとともに前記第2キャパシタの他端を前記基準電位に接続する充電動作、及び、前記第2キャパシタの前記他端を前記出力ノードに接続するとともに前記第2キャパシタの前記一端を前記基準電位に接続する電荷出力動作を前記サンプリング周期で交互に反復する第2スイッチ部と有し、
前記信号合成部は、
一方の端子が前記出力ノードに接続された第3キャパシタと、
前記出力ノードと前記基準電位との電圧差がゼロとなるように前記第3キャパシタの他方の端子の電圧を制御するアンプ回路と、
前記複数の方形波乗算部において所定回数の前記電荷出力動作が行われる度に、前記第3キャパシタに蓄積される電荷を放電する放電回路とを有する
ことを特徴とする請求項3又は4に記載の正弦波乗算装置。 An input node to which the input signal is input;
An output node to which outputs of the plurality of square wave multipliers are connected in common,
The square wave multiplier is
A first capacitor and a second capacitor;
A charging operation of connecting one end of the first capacitor to the input node and connecting the other end of the first capacitor to a reference potential in one half cycle of the square wave multiplied by the input signal; And a first switch unit that alternately repeats the charge output operation of connecting the one end of the first capacitor to the output node and connecting the other end of the first capacitor to the reference potential in the sampling period;
Charging operation for connecting one end of the second capacitor to the input node and connecting the other end of the second capacitor to the reference potential in the other half cycle of the square wave multiplied by the input signal And a second switch unit that alternately repeats the charge output operation of connecting the other end of the second capacitor to the output node and connecting the one end of the second capacitor to the reference potential in the sampling period. Have
The signal synthesizer
A third capacitor having one terminal connected to the output node;
An amplifier circuit for controlling the voltage of the other terminal of the third capacitor so that the voltage difference between the output node and the reference potential becomes zero;
5. The discharge circuit according to claim 3, further comprising: a discharge circuit that discharges the charge accumulated in the third capacitor each time the charge output operation is performed a predetermined number of times in the plurality of square wave multiplication units. Sine wave multiplier. - 前記第1スイッチ部は、
前記入力ノードと前記第1キャパシタの前記一端との間の電流経路に設けられた第1スイッチ素子と、
前記第1キャパシタの前記一端と前記出力ノードとの間の電流経路に設けられた第2スイッチ素子とを含み、
前記第1キャパシタの前記他端が前記基準電位に接続されており、
前記第2スイッチ部は、
前記入力ノードと前記第2キャパシタの前記一端との間の電流経路に設けられた第3スイッチ素子と、
前記第2キャパシタの前記他端と前記基準電位との間の電流経路に設けられた第4スイッチ素子と、
前記第2キャパシタの前記他端と前記出力ノードとの間の電流経路に設けられた第5スイッチ素子と、
前記第2キャパシタの前記一端と前記基準電位との間の電流経路に設けられた第6スイッチ素子とを含み、
前記入力信号に乗算する前記方形波の1周期中における一方の半周期では、
前記充電動作の際に前記第1スイッチ素子がオンするとともに他の前記スイッチ素子がオフし、
前記電荷出力動作の際に前記第2スイッチ素子がオンするとともに他の前記スイッチ素子がオフし、
前記入力信号に乗算する前記方形波の1周期中における他方の半周期では、
前記充電動作の際に前記第3スイッチ素子及び前記第4スイッチ素子がオンするとともに他の前記スイッチ素子がオフし、
前記電荷出力動作の際に前記第5スイッチ素子及び前記第6スイッチ素子がオンするとともに他の前記スイッチ素子がオフする
ことを特徴とする請求項5に記載の正弦波乗算装置。 The first switch unit includes:
A first switch element provided in a current path between the input node and the one end of the first capacitor;
A second switch element provided in a current path between the one end of the first capacitor and the output node;
The other end of the first capacitor is connected to the reference potential;
The second switch unit is
A third switch element provided in a current path between the input node and the one end of the second capacitor;
A fourth switch element provided in a current path between the other end of the second capacitor and the reference potential;
A fifth switch element provided in a current path between the other end of the second capacitor and the output node;
A sixth switch element provided in a current path between the one end of the second capacitor and the reference potential;
In one half cycle of one cycle of the square wave multiplied by the input signal,
During the charging operation, the first switch element is turned on and the other switch elements are turned off,
In the charge output operation, the second switch element is turned on and the other switch elements are turned off.
In the other half cycle in one cycle of the square wave multiplied by the input signal,
The third switch element and the fourth switch element are turned on and the other switch elements are turned off during the charging operation,
6. The sine wave multiplication device according to claim 5, wherein, during the charge output operation, the fifth switch element and the sixth switch element are turned on and the other switch elements are turned off. - 前記方形波乗算部は、前記第1スイッチ素子と前記入力ノードとの電流経路に設けられた第4キャパシタを有し、
前記第1スイッチ部は、
前記第4キャパシタの一端と前記入力ノードとの間の電流経路に設けられた第7スイッチ素子と、
前記第4キャパシタの前記一端と前記基準電位との間の電流経路に設けられた第8スイッチ素子と、
前記第4キャパシタの他端と前記基準電位との間の電流経路に設けられた第9スイッチ素子とを含み、
前記第7スイッチ素子が前記第1スイッチ素子と同じ条件でオンオフし、
前記第8スイッチ素子及び前記第9スイッチ素子が前記第2スイッチ素子と同じ条件でオンオフする
ことを特徴とする請求項6に記載の正弦波乗算装置。 The square wave multiplier has a fourth capacitor provided in a current path between the first switch element and the input node,
The first switch unit includes:
A seventh switch element provided in a current path between one end of the fourth capacitor and the input node;
An eighth switch element provided in a current path between the one end of the fourth capacitor and the reference potential;
A ninth switch element provided in a current path between the other end of the fourth capacitor and the reference potential;
The seventh switch element is turned on and off under the same conditions as the first switch element;
The sine wave multiplication device according to claim 6, wherein the eighth switch element and the ninth switch element are turned on and off under the same conditions as the second switch element. - 前記複数の方形波乗算部に入力される前記入力信号に含まれたノイズ成分であって、前記サンプリング周波数の整数倍の周波数から前記入力信号の信号帯域へ折り返し雑音を生じ得る前記ノイズ成分を減衰させる第1ローパスフィルタを有する
ことを特徴とする請求項3乃至7の何れか一項に記載の正弦波乗算装置。 Attenuating the noise component included in the input signal input to the plurality of square wave multipliers, which may cause aliasing from a frequency that is an integral multiple of the sampling frequency to the signal band of the input signal. The sine wave multiplication device according to any one of claims 3 to 7, further comprising a first low-pass filter. - 前記方形波乗算部は、前記入力信号及び前記入力信号の極性が反転した反転入力信号をそれぞれ入力し、前記入力信号に乗算する方形波の1周期における一方の半周期において、前記入力信号に所定の比率で比例した出力信号を生成し、当該1周期における他方の半周期において、前記反転入力信号に前記所定の比率で比例した出力信号を生成する
ことを特徴とする請求項2に記載の正弦波乗算装置。 The square wave multiplication unit inputs the input signal and an inverted input signal in which the polarity of the input signal is inverted, respectively, and in one half cycle of one cycle of the square wave multiplied by the input signal, the input signal is predetermined. 3. The sine according to claim 2, wherein an output signal proportional to the ratio is generated, and an output signal proportional to the inverted input signal is generated in the other half cycle in the one period. Wave multiplier. - 前記方形波乗算部は、前記入力信号に乗算する方形波の1周期における一方の半周期において、前記入力信号の電圧に所定の比率で比例した出力電流を生成し、当該1周期における他方の半周期において、前記反転入力信号の電圧に前記所定の比率で比例した出力電流を生成し、
前記信号合成部は、前記複数の方形波乗算部から出力される前記出力電流の和に応じた信号を生成する
ことを特徴とする請求項9に記載の正弦波乗算装置。 The square wave multiplication unit generates an output current proportional to the voltage of the input signal at a predetermined ratio in one half cycle of a square wave multiplied by the input signal, and the other half in the one cycle. Generating an output current proportional to the voltage of the inverting input signal at the predetermined ratio in a period;
The sine wave multiplication device according to claim 9, wherein the signal synthesis unit generates a signal corresponding to a sum of the output currents output from the plurality of square wave multiplication units. - 前記第1方形波に含まれる前記高調波の中で、周波数が低い順における1番目からN番目までの前記高調波に対応したNパターンの前記第2方形波を前記入力信号に乗算するN個の前記方形波乗算部と、
前記信号合成部において合成の結果として出力される信号から、前記第1方形波に含まれる前記高調波であって、前記周波数が低い順における(N+1)番目以降の前記高調波を減衰させる第2ローパスフィルタを有する
ことを特徴とする請求項1乃至10の何れか一項に記載の正弦波乗算装置。 N of the harmonics included in the first square wave are multiplied by the input signal by N patterns of the second square waves corresponding to the first to Nth harmonics in order of decreasing frequency. The square wave multiplier of
A second that attenuates the harmonics included in the first square wave, the (N + 1) -th and higher harmonics in order of decreasing frequency, from a signal output as a result of synthesis in the signal synthesis unit; It has a low-pass filter. The sine wave multiplication apparatus as described in any one of Claims 1 thru | or 10 characterized by the above-mentioned. - 物体の近接に応じた情報を入力する入力装置であって、
前記物体の近接に応じて静電容量が変化するセンサ素子を含んだセンサ部と、
所定の周波数の正弦波を直流信号に乗算し、当該乗算の結果として前記所定の周波数の第1正弦波を出力する第1正弦波乗算部と、
前記第1正弦波に応じた正弦波の駆動電圧を前記センサ素子に印加し、前記駆動電圧の印加によって前記センサ素子に流れる電流に応じた検出信号を生成する検出信号生成部と、
前記所定の周波数の第2正弦波を前記検出信号に乗算する第2正弦波乗算部と、
前記第2正弦波乗算部の乗算結果の信号から直流成分を抽出するローパスフィルタとを備え、
前記第1正弦波乗算部及び前記第2正弦波乗算部は、請求項1乃至11の何れか一項に記載された正弦波乗算装置である
ことを特徴とする入力装置。 An input device for inputting information according to the proximity of an object,
A sensor unit including a sensor element whose capacitance changes according to the proximity of the object;
A first sine wave multiplier that multiplies a DC signal by a sine wave of a predetermined frequency and outputs the first sine wave of the predetermined frequency as a result of the multiplication;
A detection signal generation unit configured to apply a drive voltage of a sine wave corresponding to the first sine wave to the sensor element, and to generate a detection signal corresponding to a current flowing through the sensor element by the application of the drive voltage;
A second sine wave multiplier for multiplying the detection signal by a second sine wave of the predetermined frequency;
A low-pass filter that extracts a direct current component from the signal of the multiplication result of the second sine wave multiplier,
The input device according to claim 1, wherein the first sine wave multiplication unit and the second sine wave multiplication unit are the sine wave multiplication device according to claim 1.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP16779937.8A EP3285395A4 (en) | 2015-04-14 | 2016-04-01 | Sine wave multiplication device and input device having same |
CN201680021645.0A CN107534415A (en) | 2015-04-14 | 2016-04-01 | Sine wave phase quadrupler and the input unit with the sine wave phase quadrupler |
KR1020177029521A KR101952813B1 (en) | 2015-04-14 | 2016-04-01 | Sinusoidal multiplication device and input device having same |
JP2017512266A JP6438121B2 (en) | 2015-04-14 | 2016-04-01 | Sine wave multiplier and input device having the same |
US15/713,903 US10331409B2 (en) | 2015-04-14 | 2017-09-25 | Sine wave multiplication device and input device having the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015082584 | 2015-04-14 | ||
JP2015-082584 | 2015-04-14 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/713,903 Continuation US10331409B2 (en) | 2015-04-14 | 2017-09-25 | Sine wave multiplication device and input device having the same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016167146A1 true WO2016167146A1 (en) | 2016-10-20 |
Family
ID=57125821
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2016/060948 WO2016167146A1 (en) | 2015-04-14 | 2016-04-01 | Sine wave multiplication device and input device having same |
Country Status (6)
Country | Link |
---|---|
US (1) | US10331409B2 (en) |
EP (1) | EP3285395A4 (en) |
JP (1) | JP6438121B2 (en) |
KR (1) | KR101952813B1 (en) |
CN (1) | CN107534415A (en) |
WO (1) | WO2016167146A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3349092A4 (en) * | 2015-10-16 | 2018-10-24 | Alps Electric Co., Ltd. | Sine wave multiplier device and input device comprising same |
JPWO2017221590A1 (en) * | 2016-06-20 | 2019-04-11 | ソニー株式会社 | Communication device and communication system |
WO2020069745A1 (en) * | 2018-10-04 | 2020-04-09 | Telefonaktiebolaget Lm Ericsson (Publ) | Passive mixer circuit with improved voltage gain |
JP2020160887A (en) * | 2019-03-27 | 2020-10-01 | ソニー株式会社 | Computing device and product-sum computing system |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60229672A (en) * | 1984-04-27 | 1985-11-15 | Yaskawa Electric Mfg Co Ltd | Signal polarity switching circuit |
US4789837A (en) * | 1987-04-22 | 1988-12-06 | Sangamo Weston, Inc. | Switched capacitor mixer/multiplier |
JPH10335938A (en) * | 1997-06-03 | 1998-12-18 | Hioki Ee Corp | Waveform-generating device |
JP2003078353A (en) * | 2001-09-04 | 2003-03-14 | Alps Electric Co Ltd | Sine-wave generating circuit and for apparatus driving vibrator employing the sine-wave generating circuit |
JP2005536099A (en) * | 2002-08-08 | 2005-11-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Improved mixer having multiple local oscillators and system based thereon |
US20080194222A1 (en) * | 2007-02-14 | 2008-08-14 | Realtek Semiconductor Corp. | Mixing apparatus and method |
WO2010064450A1 (en) * | 2008-12-04 | 2010-06-10 | パナソニック株式会社 | Sampling circuit and receiver using same |
US20130169342A1 (en) * | 2010-09-17 | 2013-07-04 | Samsung Electronics Co. Ltd. | Device and method for removing harmonic components |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4295105A (en) * | 1980-02-07 | 1981-10-13 | Racal-Vadic, Inc. | Switched-capacitor modulator |
NL8302591A (en) * | 1983-07-20 | 1985-02-18 | Philips Nv | MULTIPLICATION CIRCUIT WITH SWITCHED CAPACITIES CIRCUITS. |
CN1080949C (en) * | 1996-10-08 | 2002-03-13 | 松下电器产业株式会社 | Power unit and voltage transformer |
JP2000315919A (en) | 1999-04-30 | 2000-11-14 | Mitsubishi Electric Corp | Mixer circuit |
JP2005091139A (en) * | 2003-09-17 | 2005-04-07 | Alps Electric Co Ltd | Capacity detecting sensor, fingerprint sensor, and capacity detecting method |
US7656931B2 (en) * | 2003-12-31 | 2010-02-02 | Ut-Battelle, Llc | Hybrid spread spectrum radio system |
JP4411529B2 (en) * | 2004-08-05 | 2010-02-10 | 株式会社デンソー | Vibration type angular velocity sensor |
JP4662826B2 (en) * | 2005-08-05 | 2011-03-30 | 三洋電機株式会社 | Switch control circuit, ΔΣ modulation circuit, and ΔΣ modulation AD converter |
WO2008050630A1 (en) * | 2006-10-23 | 2008-05-02 | Panasonic Corporation | Sampling filter device and radio communication device |
US9455757B2 (en) * | 2012-07-19 | 2016-09-27 | The Trustees Of Columbia University In The City Of New York | Circuits and methods for performing harmonic rejection mixing |
US8792847B2 (en) * | 2012-07-27 | 2014-07-29 | Qualcomm Incorporated | Linearity in passive mixer circuits |
-
2016
- 2016-04-01 WO PCT/JP2016/060948 patent/WO2016167146A1/en active Application Filing
- 2016-04-01 KR KR1020177029521A patent/KR101952813B1/en active IP Right Grant
- 2016-04-01 EP EP16779937.8A patent/EP3285395A4/en not_active Withdrawn
- 2016-04-01 JP JP2017512266A patent/JP6438121B2/en not_active Expired - Fee Related
- 2016-04-01 CN CN201680021645.0A patent/CN107534415A/en active Pending
-
2017
- 2017-09-25 US US15/713,903 patent/US10331409B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60229672A (en) * | 1984-04-27 | 1985-11-15 | Yaskawa Electric Mfg Co Ltd | Signal polarity switching circuit |
US4789837A (en) * | 1987-04-22 | 1988-12-06 | Sangamo Weston, Inc. | Switched capacitor mixer/multiplier |
JPH10335938A (en) * | 1997-06-03 | 1998-12-18 | Hioki Ee Corp | Waveform-generating device |
JP2003078353A (en) * | 2001-09-04 | 2003-03-14 | Alps Electric Co Ltd | Sine-wave generating circuit and for apparatus driving vibrator employing the sine-wave generating circuit |
JP2005536099A (en) * | 2002-08-08 | 2005-11-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Improved mixer having multiple local oscillators and system based thereon |
US20080194222A1 (en) * | 2007-02-14 | 2008-08-14 | Realtek Semiconductor Corp. | Mixing apparatus and method |
WO2010064450A1 (en) * | 2008-12-04 | 2010-06-10 | パナソニック株式会社 | Sampling circuit and receiver using same |
US20130169342A1 (en) * | 2010-09-17 | 2013-07-04 | Samsung Electronics Co. Ltd. | Device and method for removing harmonic components |
Non-Patent Citations (1)
Title |
---|
See also references of EP3285395A4 * |
Also Published As
Publication number | Publication date |
---|---|
CN107534415A (en) | 2018-01-02 |
JP6438121B2 (en) | 2018-12-12 |
EP3285395A1 (en) | 2018-02-21 |
US20180012045A1 (en) | 2018-01-11 |
KR20170127554A (en) | 2017-11-21 |
KR101952813B1 (en) | 2019-02-27 |
EP3285395A4 (en) | 2018-10-10 |
US10331409B2 (en) | 2019-06-25 |
JPWO2016167146A1 (en) | 2018-01-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9459298B2 (en) | Method and apparatus for sensing capacitance value and converting it into digital format | |
JP6438121B2 (en) | Sine wave multiplier and input device having the same | |
JP5474707B2 (en) | Detection circuit and voltage detection device for voltage detection device | |
CN102064802B (en) | Low-power consumption and low-distortion signal generator based on direct digital frequency synthetic technology | |
Kaçar et al. | Novel grounded parallel inductance simulators realization using a minimum number of active and passive components | |
Wang et al. | High-accuracy circuits for on-chip capacitive ratio testing and sensor readout | |
JP3519242B2 (en) | Analog signal processor and correlation calculator using the same | |
JP2010148044A (en) | Filter circuit and communication device | |
JP6387469B2 (en) | Sine wave multiplier and input device having the same | |
US9383860B2 (en) | Capacitance processing circuit and a MEMS device | |
JP6419674B2 (en) | Sine wave multiplier and input device having the same | |
JP6419675B2 (en) | Analog-to-digital converter | |
RU2589771C1 (en) | Capacitance-voltage measuring transducer | |
Muratore et al. | A capacitive sensor interface for high-resolution acquisitions in hostile environments | |
JP5224287B2 (en) | Integration circuit using switched capacitor circuit, low-pass filter, and electronic equipment | |
JP2003168976A (en) | Offset correcting device for a/d converter, and watt meter | |
Butyrlagin et al. | Discrete-Analog Low-Pass Filter Using Switched Capacitors With Resistive Pole Frequency Control | |
Singh et al. | Differential Lossy Integrator using FTFNTA | |
RU2218599C1 (en) | Method for random interval-by-interval voltage integration | |
Gagliardi et al. | A 3-decade-frequency-range Sinewave Synthesizer with Analog Piecewise-linear Interpolation | |
SU798880A1 (en) | Four-square multiplying device | |
Trofimenkoff et al. | VFC with pulsewidth-to-period ratio proportional to input voltage | |
Yuan | On the periodicity of network functions of periodically switched linear and nonlinear circuits | |
Lin et al. | A robust linear triangle wave generator for ADC testing |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 16779937 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2017512266 Country of ref document: JP Kind code of ref document: A |
|
REEP | Request for entry into the european phase |
Ref document number: 2016779937 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 20177029521 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |