WO2016179113A1

WO2016179113A1 - Super-thin channel transistor structure, fabrication, and applications

Info

Publication number: WO2016179113A1
Application number: PCT/US2016/030461
Authority: WO
Inventors: Rimma Pirogova; Viktor Koldiaev
Original assignee: Finscale Inc.
Priority date: 2015-05-07
Filing date: 2016-05-02
Publication date: 2016-11-10
Also published as: TW201707151A

Abstract

Taught herein are transistor devices that utilize super-thin channels supported by dielectric bodies embedded in a semiconductor substrate. The super-thin channel is not subjected to a high-temp anneal process, and thus is not high doped. Rather, the source and drain form Schottky junctions with the channel. The lack of a high-temp anneal enables the transistors to be built on top of one another in a tiered structure without melting the lower tiers during fabrication. The ability to fabricate transistors in a tiered structure makes available a number of novel devices and architectuires.

Description

SUPER-THIN CHANNEL TRANSISTOR STRUCTURE,

FABRICATION, AND APPLICATIONS

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 62/158,109 entitled " Vertical Gate CCD Imaging Semiconductor Devices and Methods of Their Fabrication Based on Vertical Super-Thin Body Semiconductor on Dielectric Wall" filed May 8, 2015, U.S. Provisional Patent Application No. 62/158,164 entitled " Semiconductor Logic and Memory Stackable Devices Made of Vertical Super-Thin Body Semiconductor on Dielectric Wall and Methods of Their Fabrication" filed May 7, 2015; U.S. Provisional Patent Application No. 62/158,853 entitled "Vertical Gate CMOS IS Semiconductor Devices and Methods of Their Fabrication" filed May 8, 2015; and U.S. Provisional Patent Application No. 62/159,472 entitled " Advanced Semiconductor Devices made of Vertical Super-Thin Body Semiconductor on Dielectric Wall and Methods of Their Fabrication " filed May 11, 2015. Each of the above referenced applications are incorporated by reference in their entirety. INCORPORATION BY REFERENCE

[0002] The following applications and patents are incorporated by reference in their entirety:

[0003] US8796085 B2 08/2014 Koldiaev et al.

[0004] US2014/0103414 A1 04/2014 Koldiaev et al.

[0005] US8796085 B2 08/2014 Koldiaev et al. TECHNICAL FIELD

[0006] The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly to advanced 3D FinFET device designs and methods of their fabrication based on further development of the concept of Vertical Super Thin Body Field Effect Transistor (VSTB-FET) device made of Semiconductor-On-STI-Wall structure. [0007] The present invention is generally related to the field of semiconductor devices and methods of their fabrication and more particularly to the three-dimensional logic and non-volatile memoiy devices and other similar devices stackable in plurality of tiers designed and fabricated with adoption of Fin-based device architectures and related fabrication methods. [0008] The present invention is generally related to the field of semiconductor devices and methods of their fabrication and more particularly to the CMOS Image Sensor area of designing and fabricating with adoption of vertical Fin-based device architectures and related fabrication methods. [0009] The present invention is related to the field of semiconductor integrated circuit manufacturing, and more particularly to a universal set of devices and methods of their fabrication usable in the Charge Coupled Device Image Sensors (CCD IS) made of Vertical Super Thin Body (VSTB) based Vertical Gate CCD structures and VSTB-FET based periphery circuitry providing a significantly higher imager performance. BACKGROUND

[0010] A cross-section of a standard planar MOSFET device, which is widely used in the semiconductor industry, is shown in Fig. 1A (Prior art). The MOSFET includes the single crystalline silicon Substrate 200 doped accordingly, the heavily doped layers of the Source 500, the Drain 600 connected through the Schottky junction (diode) to the metal Source/Drain 510 made typically of metal silicide material which is connected to the Source/Drain low resistive contact layer 560, the Gate dielectric stack or a single layer 700, the Spacers 550, and the conductive Gate electrode stack or single layer 800. Source 500 and Drain 600 structural details, such as a raised Source/Drain epitaxial layer, LDD layers, and so on are not shown for simplicity of the MOSFET schematic representation. STI layers 300 for isolating two MOSFETs to the left and the right sides of the drawing are shown but the STI layers in the direction perpendicular to the cross-sectional drawing are not shown.

[0011] The Schottky MOSFET device design which is under researching in the semiconductor industr is shown in Fig, IB (Prior art). The MOSFET includes the single crystalline silicon Substrate 200 doped accordingly; the Gate dielectric stack or single layer 700; the Spacers 550, the conductive Gate electrode stack or single layer 800; the heavily doped layers of the Source 500 and the Drain 600 electrodes connected at the top to the metal Source/Drain 510, made typically of metal silicide materials, through the Schottky junction (diode); the Source/Drain low resistive contact layer 560 connected at the its bottom to the metal Source/Drain, having the inversion layer, located along the gate dielectric - substrate interface, connected to the metal Source/Drain layer 510. The metal Source/Drain layer 510 is extended under the gate dielectric to be overlapped with the channel near its ends so that the metal Source/Drain material is in direct touch with the gate dielectric along the gate - substrate interface over the overlap distance. Source 500 and Drain 600 structural details, such as a raised Source/Drain epitaxial layer, LDD layers, and so on are not shown for simplicity of the MOSFET schematic representation. STI layers 300 isolating two MOSFETs on the left and the right sides are shown. The typical metal Source/Drain are formed from metal silicides like PtSi, NiSi, and the like, since no metal can stay stable in metallic form in contact with the silicon. Metal nitrides are typically not suitable for the metal Source Drain due to their higher work functions than needed for n-channel MOSFET. The key feature of the Schottky MOSFET is the Schottky energy barrier between the Fermi level of the metal layer 510 and the semiconductor channel Fermi level which is determined by the substrate channel doping and modulated by the gate potential. The Schottky MOSFET CMOS technology is not yet in the mass production due to this and some other issues. The p-channel Schottky MOSFET is typically performing rather acceptable whereas the n-channel Schottky MOSFET has typically a low performance, a high leakage current, and a high V_th and drive current variability. There are three basic reasons as to why n-channel Schottky MOSFET is not performing. (1) Due to a high substrate channel doping under the gate, as it is typical for the planar CMOS technology of small node numbers, the surface potential is set rather high due to the high doping so that to make a low V_t for the high performance applications, very low work function metals are needed for making such a Schottky junction being about 4 eV. There is a limited choice for low work function materials, which are compatible with the silicon process integration technology and form silicides. Even for this limited set of materials there is an effect called "Metal Induced Interfacial Traps" formation mechanism which is stronger for the lower work function materials and it is this effect that has detrimental impact on the Schottky junction quality and stability as the fundamental physical reason, (2) The device architecture is such that the metal silicide layer is placed under the gate dielectric within the overlap distance so that it touches the gate dielectric and contaminates the gate with metal contaminations, which reduce the gate dielectric reliability reducing TDDB below the specification. (3) Typical metals used for the Schottky barrier formations are silicides, which have an effect of the doping redistribution during the silicide formation with dopant segregation from a rather highly doped silicon substrate to the metallurgical junction vicinity. This effect is poorly understood due to typically low temperature dopant redistribution resulting in an uncontrollable Fermi level shift. Thus the work function engineering for metal Source/Drain and their processing are important issues to be solved to fuither improve the device performance with the scaling. This issue has been resolved for the shorter channel lengths in this invention. Another important aspect of the work function engineering in scaling MOSFETs is related to the Gate work function engineering and processing which is especially important for non-planar MOSFET such as the Tri-Gate where no successful attempts were made to implement the metal Source/Drain yet. Similar metal Source/Drain architectures were under research for both Partially Depleted (PD) and Fully Depleted (FD) SOI. Despite it is promising solution for the Source/Drain parasitic resistance reduction there is little success so far.

[0012] Fig, 2 (Prior Art) illustrates the basic 2D features of 3D MOSFET design based on Fin-FET device concept known as Tri-Gate MOSFET which has important scaling issue related to the 2D effects in the work function distribution along the channel for Tri-Gate type of device concepts which is getting important with channel length reduction. A horizontal cross-section at about mid-depth of Tri-Gate Fin is schematically drawn to show some principle layers of the Tri- Gate MOSFET and 2D features of the metal gate stack structure determining the work function non-uniformity along the channel. The Tri-Gate consists of the Fin 100 having the gate dielectric layers 700 on both sides, the metal work function layers 703 on both sides, and the gate electrode filling-in layer 800 being the typical structure across the gate for double gate devices. Along the gate length direction the LDD layers at the Source side 522 and at the Drain side 622 are shown as well as the spacer layer 550, and Source/Drain layer 500 and 600, correspondingly. All details of the multilayered structure of the Spacer 550 and other features are not shown to simplify the picture. The key feature of the structure related to 2D effects in the work function metal gate stack determining the work function non-uniformity along the channel is the same as explained below for Fig. 5 (Prior Art). This issue has been resolved for the shorter channel lengths in this invention,

[0013] There are two main CMOS devices for mass production in technology nodes below 20nm: (1) Tri-Gate, a variation of the bulk vertical Fin Double Gate MOSFET (although it is called a three-gate structure, in a critical consideration the device is actually of the Double Gate type), and (2) planar Fully-Depleted SOI (FD-SOI) MOSFET fabricated on thin Buried Oxide (BOX) as the planar Single Gate device. The device density is constantly increasing due to scaling and it is clear from the critical analysis of the device scaling physics and latest publications that the device density scaling is getting close to the limit. There are a few basic root causes for the scaling limit: (i) Scaling the Fin or UTB thickness; (ii) Source/Drain are heavily doped for the main CMOS devices in the mass production which makes the parasitic resistance rising up when scaling the Source/Drain sizes, (iii) the metal gate work function stack thickness, which is about 6nm or so, cannot be made thinner than this due to the fundamental physical reasons of the Fermi level settling in a multi-layered structure and 2D effect of the Fermi level settling results in the non-uniform distribution of the work function at the comer edges of the gate length which becomes a critical scaling limiting factor for the gate length approaching the double size of the stack thickness. Actually for a single work function integration scheme, the theoretical limit is about 3nm to 4nm which significantly mitigates the scaling challenges for next nodes with the channel length in a range from 14nm to lOnm but the scaling challenges come back for future technology node with the gate and channel length below lOnm. Using the VSTB-FET device design constmctive layers one can solve the challenge to increase the device density and to integrate VSTB-FET based devices into CMOS or BiCMOS technologies for the technology nodes below lOnm. The invention solves all these scaling challenges. In fact these device design inventions can be used backward for nodes above 20nm by using a backscaling methodology.

[0014] Main issues for using any metal Source Drain designs for Tri-Gate and FD-SOI type of devices come from the processing features described below. Fabrication of an ultra-thin body (UTB) of 6 nm to 2 nm on SOI, as required for FD-SOL with the required thickness uniformity across a 300 mm (or 450 mm in future) wafer is not possible. If a thicker and cheaper SOI substrate of 20 nm and more is used as the starting material, a key fabrication step is needed to make the SOI thinner. The only solution known by today is making SOI thinner by oxidation. This step is good for rather uniform thinning of SOI, but it has some dramatic effects on the quality of SOI in terms of mobility degradation, extensive extended defects formation, device leakage, and reliability deterioration. Especially vulnerable is the bottom SOI interface with the BOX. The physical mechanisms causing these effects are described as follows. Oxidation of c-Si is accompanied by high-rate generation of interstitial Si atoms (Si-I), This has been confirmed many years ago by direct observation of oxidation-enhanced boron diffusion, because Boron diffusion is only facilitated by Si-I. The other phenomenon is Oxygen injection into the c-Si at a level which can bring the Oxygen concentration in c-Si to the limit of its solubility. This has been confirmed by direct observation of the saturation of c-Si substrate with 018 isotopes, when 018 isotopes were used for c-Si oxidation, and those isotopes are easy to detect using Secondary Ion Mass Spectrometry (SIMS) and other material analysis techniques, because more than 99% of all naturally occurring oxygen exists as the 016 isotope which is easily available as a contaminant at concentrations in a range from lel8cm-3 to 3el8cm-3 in the standard Czochralski silicon (Cz-Si) wafer. The excess Si-I and O results in their interaction through the nucleation and growth (precipitation) of extended defects in the bulk c-Si and the especially active nucleation occurs at the c-Si - a-Si02 interfaces. Oxidation Stacking Fault (OSF) formation is well observed and is a very well-known direct confirmation of this mechanism. Thus the thinning by oxidation is a harmful process, as has been observed in many studies in terms of mobility degradation and leakage current increase, and these effects should be expected if the thinning by oxidation is used for SOI thinning. Actually Fin-on-SOI thinning by oxidation does also indeed result in poor device performance for the same reasons. FinFET on SOI is not yet proven to be manufacturable for a number of reasons including those explained above and observed by many unsuccessful efforts to implement it in mass production. Bulk-FinFET (also known as Tri-Gate) with a modest aspect ratio of the Fin width to height is implemented in mass production at the 22nm and 14nm node and now has become the mainstream architecture in R&D activity across the industry, where scaling of this device concept is under scrupulous attention. For the technology nodes at and below 10 nm it seems to be rather difficult to scale the bulk-FinFET as a Tri-Gate structure to make a highly manufacturable device, since a thin Fin of 6 nm or less is needed. A very thin Fin below 6 nm with a practical aspect ratio is difficult to fabricate due to the Fin's mechanical fragility and mechanical instability, and for such a thin Fin the quantum confi nement effects of the inversion layer formation suggest little merit in having a double gate, let alone a third gate. Thus making a Tri-Gate transistor scalable brings tremendous obstacles for achieving its acceptable manufacturability. It is worthwhile to note that the initial Fin thickness for 22nm node Tri-Gate is 22nm, and this the Fin thickness becomes 8 nm at the mid-height of the final stmcture by the end of fabrication process through a thinning-by-oxidation process. Moreover, the initial Fin thickness for 1.4nm node is about 14nm, and this Fin thickness becomes ~8 nm at the mid-height by the end of fabrication process through a thinning-by-oxidation process again. But how can the performance still be good enough for mass production? The reason is that the Tri-Gate Fin stands on bulk c-Si and it allows for Si-I and O excess to sink by diffusion into the substrate where they are efficiently gettered and do not produce extended defects density above the critical concentration. Two observations support this statement: first of all High-Resolution Transmission Electron Microscopy images (HR-TEMs) do show some extended defect density and the published electrical data do show excessive device leakage. Moreover, it is known that the Tri-Gate is fabricated on the epitaxial wafers with an epitaxial layer thickness much thicker than the Fin height. It is known that the standard epitaxial layer has an O contamination concentration at or below lei 6 cm -3. Whereas the standard Czochralski c-Si has about lel8 cm-3 to 3el8 cm-3 that is almost at the saturation level at the typical high temperature range used for c-Si oxidation so that the extra O coming from the oxidation is immediately clusterized resulting in the extended defects. Thus epitaxial wafers are the material choice of necessity to offset the defect nucleation and growth during fabrication because of their very low initial O contamination level. These Mgh defect density and high leakage effects coming from the Tri-Gate process integration are prohibitive features for having high performance and low noise transistor devices. Two other very important innovative features, which are distinguishable for 14nm node vs. 22nm node, have been developed and implemented in to the mass production by Intel are: (i) the trapezoidal pedestal of the almost rectangular Fin which takes about 10% of the total Fin height; (ii) the appropriate type of doping of the sub-Fin area from solid state sources having likely P doping for p-MOSFET from PSG and B doping for n-MOSFET from BSG. The trapezoidal pedestal likely improves the mechanical stability of the Fin. But this feature makes a higher sub-V_t leakage due to significantly wider Fin thickness at the Fin bottom. To reduce the leakage, a sub-Fin doping to block the leakage path is suggested. But the deposition of the PSG and BSG glass on the Fins and successive removal of the glass layers from the Fins above the bottom pedestal level results in a Fin surface roughness development and the channel mobility degradation. Even though the final drive current per the device foot-print is acceptable for the mass production device it indicates some scaling limitations for the Tri-Gate device concept. Another important issue is that the Fin thinning by a long thermal oxidation, dopant drive-in from the glasses, and dopant drive-in from the selectively grown epitaxial layers in to the Fin Source/Drain are the high temperature steps which are very difficult scale down in terms of the thermal budget (TB) as well as it prohibits using multi-tiers vertical stackable integration due to needs for the high TB. The metal Source/Drain formed by silicidation of a Source/Drain layer saturated with extended defects due to the SOI or Fin thinning-by-oxidation process cannot be successful due to pipe-like defects formation by decorating the extended defects with metal atoms coming from the silicide layer thus prohibiting usage of the metal Source/Drain concept for Tri-Gate type of devices. The pipe-like defects are responsible for a very high Source/Drain leakage current and low yield. The suggested inventions are free of these negative effects and provide high performance, low leakage, high density, and great scalability.

[0015] Fig. 3 (Prior Art) shows a 3D illustration of all the principle layers of the generic VSTB-FET for broad applications. Some parts are removed for clarity of the locations of the most important layers. The VSTB-FET is a MOSFET that can be fabricated on a bulk semiconductor substrate or on SOI substrate (not shown). The VSTB-FET is to be used in the fully depleted (FD) mode of VSTB-FET operation where the body's electrical connection to the bulk wafer substrate is essential, as illustrated in Fig. 3 (Prior Art) and Fig. 4 (Prior Art). The VSTB-FET device shown in Fig. 3 (Prior Art), Fig. 4 (Prior Art), and Fig. 5 (Prior Art) is a semiconductor device comprising a semiconducting low-doped vertical super-thin body 100 (VSTB, also called Fin) connected to a vertical wall of a dielectric body 300, such as the STI, to the bulk semiconductor substrate at the bottom side 106, the isolation cap 101 at the top side 107, and the gate stack (GS) having the gate dielectric layer 700 or the gate dielectric stack (GDS) including a high-k layer 700 and a gate electrode consisting of a metal gate stack (MGS) 703 and the gate electrode filling (GEF) 800. The gate electrode is connected to the VSTB surface 105 opposite to the dielectric body 300. A dielectric layer 400 isolates GS from the substrate 200 and reduces the gate-to-substrate capacitance. If desired, the substrate 200 at the bottom of the gate trench 202 can be appropriately doped by ion implantation under the isolation 400 or by a dopant drive-in from the isolation layer 400 if it is made of PSG or BSG glass resulting in an appropriate doping of the sub-VSTB region. Source 500 and Drain 600 (Source/Drain) are formed in the dielectric body 300 connected to the VSTB on opposite sides of the gate resulting in the VSTB-FET. The VSTB (Fin) 100 is formed attached to the STI 300 with a hard mask (cap 101) self-aligned to the STI hard mask edge by a "spacer formation" process allowing very tight control of the body thickness and its mechanical stability. After the gate trench is filled with a dielectric material such as TEOS or HDP Si02 or the like in the volume where the GS is to be formed later but before the gate stack formation ("Gate last approach"), the Source and Drain are formed in the STI layer near VSTB. The Source and Drain are formed adjacent to the VSTB wall by etching trenches/holes vertically into the STI and foiming a thin heavily in-situ appropriately doped layer by a selective epitaxial growth (SEG) of c-Si layer or by a deposition of a poly-Si layer followed by an anneal to drive-in doping from the c-Si SEG layer or poly-Si layer into Source/Drain regions of the VSTB 502 and 602. The heavily doped SEG c-Si or poly-Si layer is covered with a low-resistivity materials stack (typically a barrier layer and a metal layer), such as appropriate silieides or/and inert metal or metal nitrides, and the rest of the volume filled in with an inert conductive material (such as Tungsten) then finished with surface planaiization by using chemical-mechanical polishing (CMP). Such a metal stack forms the Schottky junction to the highly doped Source/Drain areas but does not constitute the metal Source/Drain and no significant effect of the Source/Drain metal work function on the VSTB-FET Vi_h is expected for such a design. If desired, a recess in the Source/Drain filling can be formed and then filled with a dielectric (such as SiN and the like) that is selectively etchable with respect to Si 02 and the like. Both "Gate last" and "Gate first" approaches can be easily implemented depending on the applications and lithography capabilities available. Single or multiple VSTB devices can be fabricated within a single active area using VSTB isolation by iso-plugs 900 combined with gate electrode isolation by iso-trenches 902 or simply using some extra cut-masks to remove the VSTB hard mask (or VSTB cap) where the VSTB is not needed. For high-radiati on- tolerant applications or other applications where individual devices must be electrically isolated from one another and the substrate, the body can be easily made as a VSTB SOI MOSFET by- using initial SOI wafers having a thick SOI layer with the current flowing horizontally from Source to Drain in the VSTB channel or vertically with Source fabricated at the bottom and Drain fabricated at the VSTB top. Also the device can be made as a set of nanowires on an isolating wall of the dielectric body such as the STI wall to be a nanowire-based VSTB-nWi-FET SOI device. [0016] Fig. 5 (Prior Art) illustrates an important feature to be discussed separately. The work function metal gate stack has the important structural feature which limits the scalability of such gate electrode architecture. The typical physical thickness of the gate dielectric in the horizontal direction is about 2 nm because it is constituted from only the high-k layer. Presence of two high-k layers in the horizontal direction at the Source and Drain sides makes it 4nm of channel length reduction. This 2D effect of the high-k deposition process is not difficult to overcome by making the mask for the gate by 4nm larger unless the 2D deposition provides a not sharp 90° internal corner but rather thicker high-k around the comer due to the surface diffusion of the high~k constituting atoms. If so it makes a non-uniform V_& distribution along the channel and makes the process less manufacturable. The work function metal gate stack is about 5nm to 8nm and consists of the following layers (i) an adhesive layer to the high-k layer, which is typically TiN of ~lnm thickness; (ii) an metal etch stop layer to protect the TiN and Hf02 layers from damaging when dual work functions scheme is used and at least one time the work function layer is to be etched away which is typically made of TaN of ~lnm thickness; (iii) a work function metal material or a composite which is typically made of TiAlN-alloys or similar to this alloy having the thickness of about 3nm; (iv) The work function protective layer which reduces the gate electrode fiiling-in material effects on the work function of the work function layer which is about Iran of TiN or the like materials. The 2D effects of the gate dielectric and gate metal stack at the gate corner are indicated by the dashed ellipse in Fig. 5 (Prior Art). If the gate channel length is about 20nm and longer these effects are of minor concern. But when the channel length is less than 14 nm the 2D work function distribution along the channel is getting an issue of the primary concern.

[0017] The standard MOSFET device design which is widely used in the semiconductor industry is shown in Fig. 1A (Prior art). The MOSFET includes the single crystalline silicon Substrate 200 doped accordingly, the Source 500, the Drain 600, the silicided contact 510 to Source Drain (SD), the contact 560, the Gate dielectric stack or single layer 700, the Spacers 550, and the conductive Gate stack or single layer 800. Source 500 and Drain 600 structural details, such as a raised SD epitaxial layer, LDD layers, and so on are not shown for simplicity of the MOSFET schematic representation. The STI layers 300 for isolating two MOSFETs to the left and the right sides of the drawing are shown but the STI layers in the direction perpendicular to the cross- sectional drawing are also not shown. In order to bring a memory capability to the standard MOSFET the gate dielectric stack is replaced by a memory stack 705 as shown in Fig. 9 (Prior art). The memory stack 705 can be made of (i) a dielectric stack having a charge trap (CT) containing dielectric media, for example, Si3N4 or the like; (ii) a stack of "the first gate dielectric - conducting floating gate (FG) - second inter-gate dielectric", or (iii) a stack having a ferroelectric layer. All memory stacks can be polarized / depolarized by applying a high program or erase voltage which sets their charge states. The charge states are either a high negative or positive charge which determines a distinguishable threshold voltage of the MOSFET which can be sensed by applying a reading voltage thus making such a device to be a MOS Field Effect Memory Transistor (MOSFEMT), The retention time for these negatively or positively polarized charge states is rather long, being up to 10 years which makes them suitable for Non- Volatile Memory ( VM). Gate conductive layer 800 in Fig. 9 (Prior art) is typically made of low resistance metallic materials, being typically a p+-doped or n+-doped polycrystalline Silicon (poly-Si) silicided accordingly which can be different from the Gate conductive layer 800 in Fig. 1 A (Prior art) in the standard MOSFET when a different optimal work function for a MOSFEMT is necessary.

[0018] NAM) Flash array is fabricated from multiple rows where a row is a series of cells made of the MOSFEMT with one Source and one Drain per row, with no Sources and Drains in between the MOSFEMTs in the row as shown in Fig. 10 (Prior art). The columns in the NAND Flash array are fabricated along Word-Lines (WL) 912 which can select a cell in each row for program/erase/read while other WLs have a high voltage applied to enable addressable access to the selected cells. Each of the adjacent rows are isolated from one another by using STI located in front of and behind the row shown in Fig. 10 (Prior art). The long channel from Source 500 to the Drain 600 of the multi-gate row structure in Fig. 10 (Prior art) is the Bit-Line (BL). A select transistor per row is often used placed in series with the memory row. Sometimes a doped area is fonned under the inter-cell isolation layer 550 to reduce the total parasitic resistance along the row when reading function is activated. Often the channel area under the memory layer 705 is moderately doped to set the initial Vui to the required level and to reduce the charge state disturb when programming, erasing, and reading the neighboring cells, [0019] A Vertical 3D stackable NAND array with a horizontal WL outside and a vertical BL inside of the rod-like (or cylinder-like) BL channel layer 150 made of poly- Si with an optional dielectric concentric rod inside (not show) is known and illustrated in Fig. 11 (Prior art). The memory gate stack 705 surrounds the BL poly-Si conductive vertical rod-like layer, constituting a Gate-Ail-Around device concept, made in a self-aligned manner with all Word-Lines. [0020] A Vertical 3D stackable NAND array with a Vertical Word-Line 912 outside and a Horizontal Bit-Line (BL) inside 151 is illustrated in Fig. 12 (Prior art), constituting a Double Gate device concept, because the Gate 912 is placed on two sides of the BL 151 semiconducting bar. [0021] Fig. 13(a) (Prior Art) shows an experimental Transmission Electron Microscopy (TEM) cross- sectional view made through the Bit Line (BL) along the Word-Line (WL) of the 8- layer 3D-Vertical Gate of a particular Vertical 3D stackable NAND array with Vertical WLs. Fig. 13(b) (Prior Art) shows a TEM image of the actual SONONOS memory structure: all 5 dielectric layers are marked by numbers. The key difference with respect to the Fig. 12 (Prior art) device architecture is that the Double Gates are connected to the WLs on the top (marked by text: "Poly-Si gate" and "WSi_x") whereas in Fig. 12 (Prior art) the WLs are connected to the Double Gates at the bottom. The BL poly-Si bar thickness is about 30nm and the isolation between the bars is also about 30nm as indicated by black bold vertical lines. The BL bar shape is indicated by the dashed line rectangles and one can see that the top bar width is noticeably smaller vs. the bottom one. Each device is a Double-Gate Thin-Film-Transistor (TFT) having a Barrier Engineered Silicon-Oxide- Nitride-Oxide-Siiieon (BE-SONOS) charge-trapping memory device, marked by "BE-SONOS" on both sides of the BL as a single poly-Si "bar" or "wire". The real BE-SONOS is actually a SONONOS memory structure having the Barrier Engineered structure made of an Oxide-Nitride- Oxide triple layer. Even though the term "wire" is often used for the bar with sizes of 30nm by 30nm or so it is actually the bar because the sizes are much greater than the inversion layer thickness being 4nm, the size needed to make the bar behave electrically like a wire.

[0022] Fig. 6 (Prior Art) shows a 3D illustration of all the principle layers of the generic VSTB-FET for broad applications. Some parts are removed for clarity of the locations of the most important layers. The VSTB-FET is a MOSFET that can be fabricated on a bulk semiconductor substrate or on SOI substrate (not shown). The VSTB-FET is to be used in the fully depleted (FD) mode of VSTB-FET operation where the body's electrical connection to the bulk wafer substrate is essential, as illustrated in Fig. 6 (Prior Art) and Fig. 7 (Prior Art). The VSTB-FET device illustrated in Fig. 6 (Prior Art), Fig. 7 (Prior Art), and Fig. 8 (Prior Art) is a semiconductor device comprising a semiconducting low-doped vertical super-thin body 100 (VSTB, also called Fin) connected to a vertical wall of a dielectric body 300, such as the STI, also having connection to the bulk semiconductor substrate at the bottom side 106, the isolation at the top side 107, and the gate stack (GS) consisting of the gate dielectric 700 or gate dielectric stack (GDS) 701+702, metal gate stack (MGS) 703+704, and gate electrode filling (GEF) 800 on the same or opposite side of the dielectric body (STI side) VSTB surface 105. A dielectric layer 400 isolates GS from the substrate 200. IT desired, the bottom of the gate trench 401/202 can be appropriately doped under the isolation 400 resulting in an appropriate doping of the sub-VSTB region. Source 500 and Drain 600 (SD) are formed in the dielectric body connected to the VSTB on the same or opposite sides of the gate resulting in the VSTB-FET, The VSTB (Fin) 100 is formed with a hard mask self-aligned to the STI hard mask edge by a "spacer formation" process allowing very tight control of the body thickness. Source and Drain are formed before the gate stack formation ("Gate last approach") by using dummy dielectric filling (such as Si02 or the like) in the volume where the GS is to be formed. In the preferable embodiment, the Source and Drain are made by etching trenches/holes vertically into the STI adjacent to the VSTB surface 104 and forming in the trenches/holes a thin heavily in-situ appropriate type doped layer by a selective epitaxial growth (SEG) of c-Si layer or by a deposition of a poly-Si layer followed by an anneal to drive-in doping from the c-Si SEG layer or poly-Si layer into SD regions of the VSTB 502 and 602. The heavily doped SEG c-Si or poly-Si layer is covered with a low-resistivity materials stack (typically a barrier layer and a metal layer), such as appropriate silicides or/and inert metal or metal nitrides, and the rest of the volume filled in with an inert conductive material (such as Tungsten) then finished with surface planarization by using chemical-mechanical polishing (CMP), If desired, a recess in the SD filling can be formed and then filled with a dielectric (such as SiN and the like) that is selectively etchabie with respect to Si 02 and the like. Both "Gate last" and "Gate first" approaches can be also easily implemented depending on the applications and lithography capabilities available. Single or multiple VSTB devices can be fabricated within a single active area using VSTB isolation by iso-plugs 900 combined with gate electrode isolation by iso-trenches 902 or simply using some extra cut-masks to remove VSTB where it is not needed. For high-radiation-tolerant applications or other applications where individual devices must be electrically isolated from one another and the substrate, the body can be easily made as a VSTB SOI MOSFET by using initial SOI wafers having a thick SOI layer with the current flowing horizontally from Source to Drain in the VSTB channel or vertically with Source fabricated at the bottom and Drain fabricated at the VSTB top. Also the device can be made as a set of nanowires on an isolating wall of the dielectric body such as the STI wall to be a nanowire-based VSTB-nWi-FET SOI device.

[0023] Fig. 14 (Prior Art) to Fig. 16 (Prior Art) show a generic layout view and some cross- sectional views along the Word-Line (WL) of a NAND Flash column with 2 bits per super-cell fabricated using the VSTB-FET design, with the optional virtual Sources/Drains (SDs) 530 formed on one side and along of VSTB BL 100 to make lower resistance connections along the VSTB- FEMT BL 100. If a ferroelectric dielectric stack (such as SrTiOS and the like) or a trap-based memory stack (TA OS, SONOS and the like) is formed as the gate memory stack 705, then the virtual SDs 530 are typically not needed. Since the FG thickness is nowadays scaled down to a range from 5nm to lOnm vs. 50nm to lOOnm in previous generations, the virtual SDs are also typically not needed. The BL voltages applied to the Source 500 through interconnects 910 and to the Drain 600 through interconnects 911 and the WLs are protected by a layer 951. Also in both former cases the memory stack 705 can be continuously extended under the WL as shown in Fig.

15 (Prior Art ). If the Floating Gate (FG) is used in the memory stack then the FG and the inter-gate dielectric are to be better formed by using the spacer process to fabricate those layers only inside the

WL trench as the VSTB (Fin) spacers shown in Fig. 16 (Prior Art), FG isolation between neighboring WL NAND Flash cells is to be accomplished using the iso-trench 902, cutting through the memory stack and also, if desired, the virtual SD can be made with a lower resistance connection along the VSTB by high doping of those portions of VSTB column against the iso- trenches formed in the gate area from material for example like Phosphor Silicate Glass (PSG) deposited and followed by an anneal to drive-in P dopants into the VSTB virtual SD areas. By repeating this column to the left and to the right a NAND Flash array is formed with 2 bits per a super-cell.

[0024] Among many reasons why the Tri-Gate and FD-SOI are not implemented into Flash memory mass production the primary reason is the high leakage due to extended defects coming from the process integration features summarized in this section. Fabrication of a super-thin body of 6 nm to 2 nm on SOI, as required for FD-SOI, with the required thickness uniformity across a 300 mm (or 450 mm in future) wafer is not possible. If a thicker and cheaper SOI substrate of 20 nm and more is used as the starting material, a key fabrication step is needed to make the SOI thinner. The only solution known by today is making SOI thinner by oxidation. This step is good for rather uniform thinning of SOI, but it has some dramatic effects on the quality of SOI in terms of mobility degradation, extensive extended defects formation, device leakage, and reliability deterioration. Especially vulnerable is the bottom SOI interface to the BOX. The physical mechanisms causing these effects are described as follows. Oxidation of c-Si is accompanied by high-rate generation of interstitial Si atoms. This has been confirmed many years ago by direct observation of oxidation- enhanced Boron diffusion, because Boron diffusion is only facilitated by silicon interstitials (Si-I). The other phenomenon is Oxygen injection into the c-Si at a level which can bring the Oxygen concentration in c-Si to the limit of its solubility. This has been confirmed by direct observation of the saturation of c-Si substrate with 018 isotopes, when 018 isotopes were used for c-Si oxidation, and those isotopes are easy to detect using Secondary Ion Mass Spectrometry (SIMS) and other material analysis techniques, because more than 99% of all naturally occurring oxygen exists as the

016 isotope. The excess Si-I and O results in their interaction through the nucleation and growth (precipitation) of extended defects in the bulk c-Si and the especially active nucleation occurs at the c-Si - a-Si02 interfaces. Oxidation Stacking Fault (OSF) formation is a very well-known direct confirmation of this mechanism. Thus the thinning by oxidation is a harmful process, as has been observed in many studies in terms of mobility degradation and leakage current increase, and these effects should be expected if the thinning by oxidation is used for SOI thinning. Actually Fin-on- SOI thinning by oxidation does also indeed result in poor device performance for the same reasons. FinFET on SOI is not yet proven to be manufacturable for a number of reasons including those explained above and observed by many unsuccessful efforts to implement it in the mass production. Bulk-FinFET (also known as Tri-Gate) with a modest aspect ratio of the Fin width to height is implemented in mass production at the 22nm and 14nm node and now has become the mainstream architecture in R&D activity across the industry, where scaling of this device concept is under scrupulous attention. For the technology nodes at and below lOnm it seems to be rather difficult to scale the bulk-FinFET as a Tri-Gate structure to make a highly manufacturable device, since a thin Fin of 6 nm or less is needed. A very thin Fin below 6 nm with a practical aspect ratio is difficult to fabricate due to the Fin's mechanical fragility and stability and for such a thin Fin the quantum confinement effects of the inversion layer formation suggest little merit in having a double gate, let alone a third gate. Thus making a Tri-Gate transistor scalable brings tremendous obstacles for achieving its acceptable manufacturability. It is worthwhile to note that the initial Fin thickness for the Tri-Gate 22nm node is 22nm, and this Fin thickness becomes 8nm at the mid-height of the final structure by the end of fabrication process through a thinning-by-oxidation process. But how can the performance still be good enough for mass production? The reason is that the Tri-Gate Fin stands on bulk c-Si and it allows for Si-I and O excess to diffuse into the substrate where they are efficiently gettered and do not produce extended defects density above the critical concentration. Two observations support this statement: first of all High-Resolution Transmission Electron Microscopy images (HR-TEMs) do show some extended defect density and the published electrical data do show excessive device leakage. Moreover, it is known that the Tri-Gate is fabricated on the epitaxial wafers with the epi layer thickness about 2 micrometers. It is known that the standard epi layer has an O contamination concentration at or below lei 6 cm-3. Whereas the standard Czochralski c-Si has about lei 8 cm-3 to 3el8 cm-3 that is almost at the saturation level at the typical high temperature range used for c-Si oxidation so that the extra O coming from the oxidation is immediately clusterized resulting in the extended defects. Thus epitaxial wafers are the material choice of necessity to offset the defect formation during fabrication because of their very low initial O contamination level. [0025] A recently invented semiconductor device comprises a semiconducting low-doped Vertical Super-Thin Body (VSTB) formed on a dielectric body wall, such as the STI wall, as an isolating substrate having the VSTB body connection to the bulk semiconductor wafer on the bottom side, to isolation cap on the top side, to the Source and Drain on STI side, to the gate dielectric stack and gate electrode stack on the side opposite the STI- VSTB interface (or, if desired, on the same side as Source/Drain), resulting in a Field Effect Transistor (VSTB-FET). The VSTB body is made self-aligned to the STI hard mask edge allowing a very tight control of the VSTB body thickness. Source and Drain are made by etching trenches/holes vertically in the isolating wall on either VSTB side (like in the STI for a particular embodiment) connected on the isolating wall side to the VSTB semiconductor body, and filling them with a heavily doped SEG layer of c~Si or with a deposited poly-Si appropriately doped to p+ or n+ types and covered with a low-resistivity material or materials stack including any appropriate silicides, metal nitride barrier layers or/and metal. The device is very flexible in accommodating the Schottky barrier Source/Drain in a very efficient way. A Tunneling MOSFET is also easy to form taking advantage of the Source/Drain formation method in the holes/trenches etched in the isolating wall such as STI wherein using appropriate materials. A skilled-in-the-art specialist can engineer and form the Source/Drain from materials having appropriate work functions and tunneling barriers as well as barrier materials to prevent any chemical interaction of the VSTB semiconductor material with the Source/Drain forming materials, if desired. To this extent any heterogeneous junctions can be formed as the VSTB-FET Source Drain stack providing appropriate switching characteristics of the VSTB FET. "Gate first" or "Gate last" approaches can be easily implemented depending on applications and lithography capabilities available. Single or many VSTB-FET devices can be fabricated in a single active area with VSTB body isolation between devices by iso-plugs combined with gate electrode isolation by iso-trenches or simply using cut masks to remove the hard mask for forming VSTB and removing VSTB wherever it is not needed, ff desired, for high radiation hardness applications, or other applications where individual devices must be electrically isolated from one another and the substrate, the VSTB body can be easily made as a VSTB SOI MOSFET on a thick SOI substrate. The current can flow horizontally with Source and Drain at the VSTB left and right sides or vertically with Source and Drain at the VSTB bottom and top respectively. If desired, a device can also be made having a set of nanowire MOSFETs on the insulating wall such as the STI wall resulting in a VSTB-nWi-FET as a nanowire-based device. The high performance (HP) which is sors (μΡ) and SoCs need to have embedded DRAM (eDRAM) and embedded SRAM. Low Power (LP) and Ultra-Low Power (ULP) SoC products designed to enable smartphones and other mobile devices have a low leakage specification at or below 0.1 nA/um. Programmable SoC (so-called pSoC) and some other products need to have an embedded Flash memory of NOR or/and NAND type. Those listed products and many standalone memory products such as DRAM, NOR and NAND Flash (floating gate, trap-based, and ferroelectric-based), SRAM and others stand alone or embedded semiconductor products can be fabricated using VSTB-FET as the basic building device and basic fabrication method.

[0026] The continuous trend in increasing the Flash device density has resulted in usage 3D stack of Flash arrays. The absence of the doping in VSTB results in absence of the threshold voltage (V_th) variability related to the random dopant fluctuation (RDF) which is the main component of V_& variability in the standard CMOS technology based on the highly doped channel. VSTB-FET and VSTB-FEMT device concepts are easily fabricated in any 3D stacks as the multi- tiers architecture. The low variability, low leakage, and low noise bring VSTB-FET and VSTB- FEMT to be suitable for the 3D integration in a few major architectures invented and described below for N AND and NOR Flash to be used for the HP/LP/ULP ULSI, microprocessors, SRAM, DRAM, Analog IC, RF and Mix-Signal IC to be split in to the tiers by a hierarchy of the specifications: the higher the performance needed the lower the tier is to be used for making the IC. Thus the semiconductor industry needs an innovation in designing those devices if possible using a single unified device concept and the VSTB-FET concept provides it for a broader usage in the semiconductor industry.

[0027] Photosensitive devices can be a part of SoC products and arrays of the photosensitive devices can be a part of the CMOS Image Sensor (CMOS IS) of digital photography chips. The typical generic CMOS IS pixel with four switching transistors is widely used in the practice and is illustrated in Fig. 17 (Prior Art) as a hybrid representation with using the cross-sectional presentation of the Photodiode (PD) 089 and Floating Diode (FD) 083 and an electrical equivalent circuitry of the four switching transistors. By opening MOSFET' s T_x and R_x the PD 089 is charged to a certain high voltage during the pre-charge cycle. Then the light is turned on the PD and the PD starts generating electron-hole pairs where the electrons are accumulated by the PD. Before reading a PD charge state the FD 083 is charged through the MOSFET R_x to a higher than the PD voltage. After turning T_x on, the charge accumulated in the PD is taken from the PD to the FD and transformed in to a potential linearly corresponding to the charge taken from the PD. The FD potential goes through the Source follower D_x and when the pixel is selected by the select MOSFET S_x the signal goes through V_0l!t line to the Analog-Digital Conversion (ADC) circuitry. A layout illustration of a CMOS IS pixel with two PD's and common for both PD's switching circuitry is shown in Fig. 18 (Prior Art). From a design point of view the three conductive layers are used for connecting the PD to the external world. Poly-Si layers 082 and Metal- 1 layers 081 are used for internal connections and for making horizontal interconnects ("bit lines") to the ADC and pixel driving IC. Whereas Metal-2 layers are used for making the vertical interconnects ("word-line") as marked in Fig. 8 (Prior Art). Also wherever it is possible the active area of Sources and Drains 080 is used as the interconnection between Sources and Drains. All pixels are isolated by the STI 300. There are two ke performance parameters for such a IS pixel: the minimal charge Q_asii at the lowest light irradiation intensity and the maximal charge Q_max at the highest light intensity which can be integrated by the PD for a fixed accumulation (integration) time. Both performance parameters are limited by the CMOS IS design and process integration quality. The noise floor of the T_x and D_x and the dark current of the PD limit Qmm, whereas Q_m^ is limited by the PD capacitance and pre-charge voltage. The PD is to have both PD capacitance plates being low doped to reduce the dark current which is limited by the Shockley-Read-Hall (SRH) generation mechanism strongly dependent on the doping level. Due to this low doping of the n-plate of the n- p-photodiode the pre-charge voltage is limited by the total depletion effects of the PD quasi -neutral layer. Thus the dynamic range of the pixel which is the ratio of the to the Q_mm is determined by the pixel design and the trap concentration in the PD within the Space Charge Region (SCR) determining the dark current (leakage). There are a lot of efforts and patented solutions to increase the PD capacitance and reduce the dark current and the noise floor of the MOSFET's.

[0028] An alternative approach to the planar CMOS IS PD to accumulate the charge, to address the PD, and to transfer the charge from the PD to a charge-to-voltage transformation diode is an approach based on a Charge Coupled Device (CCD) where the CCD photosensitive device is complemented with CCD rows for the charge retention and transfer. A cross-section view of a three-phase CCD with a schematic of its functioning is illustrated in Fig. 19 (Prior Art). The CCD basically is a chain of MOS-Capacitors (MOS-C) made on a semiconductor substrate 200 and having the gate dielectric 701 and the even gates 821 made of the first poly-Si and the odd gates 822 made of the second poly-Si with a thin lateral isolation 820 between the MOS-C s being next to each other. The first MOS-C under phase is actually the MOS-photodiode (MOS-PD). The MOS-PD under phase Vi is strongly biased to create thick SCR 051 and when the light is turned on it starts accumulating a photo-generated charge in the SCR proportional to the light intensity and accumulation (integration) time. After the integration time (frame time) is over a higher voltage is applied to the phase V₂ to transfer the charge to under the phase V? gate 052 accompanied by gradual Vi voltage decrease and then step-like decrease of V₂ to the level of holding no more than the saturation charge under V?. By turning the next gate of the phase V to a higher voltage the charge is transferred as another step to the right-hand direction. The SCRs under the gates V₃ 053 are designed to isolate the transfer process from a next CCD device. By doing so many times the charges integrated under all Vj gates during an irradiation cycle, are transferred to the very right- hand gate where it goes to the transformation in to the voltage and goes to the ADC to turn the analog charge signal in to the digital form. The fundamental disadvantages of the planar CCD concept are: 1. The light goes through poly-silicon gate and its intensity is partially decayed due to the parasitic light absorption in poly-Si, especially the blue light which has a very small penetration length; 2. The total charge is limited by the MOS-diode capacitance which must be maximized by a design for achieving the larger dynamic range as the key PD performance parameter. But this CCD mechanism of transferring the charge from the MOS-diode in to the Floating Diode (FD) can be utilized instead of using T_x transistor as it is shown in the inventions described below.

[0029] Fig. 6 (Prior Art) shows 3D illustration of all the principle layers of the generic VSTB-FET for broad applications. Some layers and parts are removed for clarity of the illustrations of the most important layers. The VSTB-FET is a MOSFET on a bulk semiconductor. The VSTB- FET is to be used in the fully depleted (FD) mode of VSTB-FET operation where the body electrical connection to the wafer substrate is essential, as illustrated in Fig, 6 (Prior Art) and Fig. 7 (Prior Art). The VSTB-FET device in the Fig. 6 (Prior Art), Fig. 7 (Prior Art) and Fig. 8 (Prior Art) is a semiconductor device comprising a semi conducting low doped vertical super-thin body 100 (VSTB a.k.a. Fin) connected to a vertical wall of a dielectric body 300, such as the STL having the connection to the bulk semiconductor substrate at the bottom side 106, isolation at the top side 107, and the gate stack (GS) consisting of the gate dielectric 700 or gate dielectric stack (GDS) 701+702, metal gate stack (MGS) 703+704, and gate electrode filling (GEF) 800 on the same or opposite to the dielectric body (STI side) VSTB surface 105. A dielectric layer 400 isolates GS from the substrate 200. If desired, the bottom of the gate trench 401/202 can be appropriately doped under the isolation 400 resulting in an appropriate doping of the sub- VSTB area. Source 500 and Drain 600 (SD) are fonned in the dielectric body connected to the VSTB on the same or opposite sides of the gate resulting in VSTB-FET. The VSTB (Fin) body 100 is formed with a self-aligned to the STI hard mask fonned at the STI hard mask edge by "spacer formation" process allowing a very tight control of the body thickness. Source and Drain are fonned before the gate stack formation ("Gate last approach") by using dummy dielectric filling (such as Si02 or the like) in the volume where the GS is going to be. In the preferable embodiment, the Source and Drain are made by etching trenches/holes vertically in the STI adjacent at the STI side to the VSTB surface 104 and depositing in to the trenches/holes a thin selectively epitaxially grown and heavily in-situ appropriately doped c~Si layer or a thin heavily appropriately doped poly-Si layer followed by an anneal to driven-in doping from the c-Si epi or poly-Si layer into SD regions of VSTB 502 and 602. Doped epi c-Si or poly-Si is covered with low resistivity materials stack (typically a barrier layer and a metal layer) like any appropriate siiicides or/and inert metal or metal nitrides, and the rest of the volume filled in with an inert conductive material (such as Tungsten), and finished with the surface planarized by- using chemical -mechanical polishing (CMP), If desired, a recess of the SD filling can be filled with a dielectric (such as SiN and the like) selective in etch to Si02 and the like. The device is very flexible in accommodating the Schottky barrier Source/Drain in a very efficient and original way being placed by a distance equal to a VSTB thickness or so away from the gate without having the Schottky junction under the gate dielectric. "Gate first approach" can be also easily implemented depending on applications and lithography capabilities available. Single or multiple VSTB devices can be fabricated in a single active area with VSTB isolation by iso-plugs 900 combined with gate electrode isolation by iso-trenches 902 or simply using some extra cut-masks to remove VSTB where it is not needed. For a high radiation hardness applications the body can be easily made as a VSTB SOI MOSFET by using initial SOI wafers with a thick SOI layer with the current flowing horizontally from Source to Drain in the VSTB channel or vertically with Source fabricated at the bottom and Drain fabricated at the VSTB top.

[0030] This recently invented semiconductor device comprises a semiconducting low doped Vertical Super-Thin Body (VSTB) formed on an dielectric body wail such as the STI-waii as an isolating substrate having the VSTB body connection to the bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, the Source and Drain on STI side, the gate dielectric stack, and gate electrode stack on the opposite to the STI side surface (or on the same as Source/Drain side on one or opposite side of VSTB), resulting in a Field Effect Transistor (VSTB- FET). The VSTB body is made self-aligned to the STI hard mask edge allowing a very tight control of the VSTB body thickness. Source and Drain are made by etching trenches/holes vertically in the isolating wall on either VSTB side (for example, in the STI for a particular embodiment) connecting in the isolating wall side to the VSTB semiconductor body and filling it with a heavily doped selectively epitaxially grown c-Si or with a deposited poly-Si both appropriately doped to p+ or n+ types and covered with a low resistive material or materials stack including any appropriate siiicides, metal nitride barrier layers or/and metal. The device is very flexible in accommodating the Schottky barrier Source/Drain in a very efficient way. A Tunneling MOSFET is also easy to form taking the advantage of the Source/Drain formation method in the holes / trenches etched in the isolating wall such as STI wherein using appropriate materials a skilled in the art specialist can engineer and form the Source/Drain from materials having appropriate work functions and tunneling barriers as well as barrier materials to prevent any chemical interaction of the VSTB semiconductor material with the Source/Drain forming materials, if desired. To this extent any heterogeneous junctions can be formed as the VSTB-FET Source/Drain stack providing an appropriate switching characteristics of the VSTB FET. "Gate first" or "Gate last" approaches can be easily implemented depending on applications. Single or many VSTB-FET devices can be fabricated in a single active area with VSTB body isolation between devices by iso-plugs combined with gate electrode isolation by iso-trenches or simply using cut masks to remove the hard mask for forming VSTB and removing VSTB wherever it is not needed. If desired, for high radiation hardness applications the VSTB body can be easily made as a VSTB SOI MOSFET on a thick SOI The current can flow horizontally with Source and Drain at the VSTB left and right sides or vertically with Source and Drain at the VSTB bottom and top correspondingly. If desired, a device can also be made as a set of nanowire MOSFET's on the insulating wall such as the STI wall resulting in a nanowire-based VSTB-nWi-FET device. Low Power (LP) and Ultra-Low Power (IJLP) SoC products are taking more market shares in the mobile semiconductor device sector which have a low leakage specification to be at and below 0.1 ηΑ/μηι. Those listed products can be fabricated using VSTB-FET as the basic building device and basic fabrication method. The absence of the doping in VSTB results in absence of the threshold voltage (V_th) variability related to the random dopant fluctuation (RDF) which is the main component of V_th variability in the standard CMOS technology based on the highly doped substrate. Low \½, variability makes VSTB-FET to be suitable for all the HP ULSI, Analog IC, RF and Mix-Signal IC, CMOS IS (Image Sensors), and SoC applications. Thus the semiconductor industry needs an innovation in designing those devices if possible using a single unified device concept like the VSTB-FET concept for a broader usage in the semiconductor industry, [0031] A photosensitive device based on a planar Charge Coupled Device (CCD) is an alternative device to the planar CMOS IS and become less in usage after CMOS IS has been invented. In the CCD IS the CCD's are used as the photosensitive devices as well as integrated devices for the charge retention and charge transfer to the Analog to Digital Converter (ADC). Lately a new wave of interest to the CCD IS has come to overcome some CMOS IS fundamental disadvantages recognized by today. A cross-section view of a three-phase CCD IS pixel with a schematic of its functioning in a three phase configuration is illustrated in Fig. 20 (Prior Art). The CCD is basically a chain of plurality of long width MOS-Capacitors (MOS-C) made on a semiconductor substrate 200 and having the gate dielectric 701 and the gates 821 made of the first poly-Si and gates 822 made of the second poly-Si with a thin lateral isolation 820 between the MOS-C's being next to each other. The first MOS-C under phase \'Ί is actually the MOS- photodiode (MOS-PD). The planar MOS-PD under phase Vi is strongly biased to create thick SCR 051 and when the light is turned on it starts accumulating at the interface in the inversion layer a photo-generated charge in the SCR proportional to the intensity and accumulation (integration) time. After the integration time (frame time) is over a higher voltage is applied to the phase V₂ gate to transfer the charge to the inversion layer under the phase V₂ gate 052 accompanied with a gradual Vi voltage decrease at the Vi pulse end and then step-like decrease of V₂ to the level of holding no more than the saturation inversion charge under V₂. After a while of retention of the charge under the phase V₂ the charge is transferred as another step to the right-hand direction by turning the next gate of phase V₃ to a higher voltage and gradual decrease of V₂ at the end of the pulse V₂. The SCR under gate V₃ 053 is designed to isolate the charge transfer process to or from a next CCD device. By doing so many times, the charges, integrated under all Vi gates during an illumination (irradiation) cycle, are transferred to the very right-hand gate where it goes to the transformation in to the voltage by charging a diode and goes to the ADC to turn the analog charge signal in to the digital form. The fundamental disadvantages of the planar CCD IS concept are following. 1. The light goes through poly-silicon gate 822 and its intensity is partially decayed due to the light absorption in poly-Si, especially the blue light which has a very small characteristic penetration depth, 2. The total charge is limited by the MOS-diode capacitance which must be maximized by a design area for achieving a larger dynamic range as the key PD performance parameter which makes the PD scaling limited.

[0032] Planar CCD's were the first photo-sensitive devices used for making image sensors. The principle drawback of the planar CCD was a low transparency of the photo-sensitive CCD gates made typically of poly-Si which were thin enough to let the light penetrate through the conductive gates in to the planar MOS-PD. For the red color the light absorption characteristic length is rather large (about 1 μηι for about 1 μηι wave length in c-Si or poly-Si) but for the blue light this parameter is about lOx less and a large portion of the light is absorbed in poly-Si gate. To avoid this parasitic absorption in the top planar gate a backside illumination was invented where a thin c-Si substrate is in use. But the problem of the parasitic absorption is not totally resolved. For example, for a typical c-Si wafer thickness of 30 μιη (thinned at the end of the fabrication process) and for the visible light wave length of 700 nm only 0.1% of the total number of the generated electron-hole pairs reaches the CCD-top interface which makes the sensible lowest light illumination intensity to be very large reducing the sensor dynamic range. An embodiment of the invention is the vertical gate CCD image sensor where the non-transparent gate is moved aside and made vertically buried thus providing the MOS-capacitance structure with open top entrance for the light to be absorbed at the full scale without any losses to overcome the basic drawback of the planar CCD imagers. Electron-hole pairs are generated across the entire area of the SCR and the electrons are drifting laterally and collected in the inversion layer of the MOS-capacitance having a high gate voltage whereas the holes are diffusing vertically down and collected by the grounded substrate.

SUMMARY

[0033] The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly to advanced designs of MOSFET devices and methods of their fabrication usable in the CMOS technologies for fabricating a plurality of IC types and System-on-Chip (SoC) designs made of the basic structures including (i) a crystalline or polycrystalline Vertical Super-Thin Body (VSTB) Semiconductor on a Vertical Dielectric Wall of a Shallow or Deep Trench Isolation (hereafter referred to as STI) or a Thick Dielectric Layer (TDL) and an inter- VSTB dummy isolation layer; (ii) the VSTB Protective Cap placed between the corresponding Protective Caps of the STI or the TDL and the inter- VSTB isolation layer cap, having them mutually selectively etchable, having the TDL formed on the inter-tier dielectric layer or, if desired, on a stack of a bottom quasi-substrate(s) made of a moderately to heavy doped polycrystalline semiconductor like poly- Si and an inter-tier dielectric layer(s); and (iii) having the Gate and Source/Drain formed on the same or opposite sides of the VSTB where Source/Drain are formed from metallic layers constituting the Schottky junction placed remotely from the gate-to- channel interface but close enough to affect the device V^ through the Schottky junction metal work function. The advanced set of devices includes: (a) a plurality of CMOS devices that includes Vertical Super Thin Body Field Effect Transistor having Schottky junction Source and Drain placed remotely from the Gate Dielectric (called sVSTB-FET) to control the threshold voltage of the devices by the appropriately designed work functions (W_f) of the Source/Drain optimized together with the work functions of the gate electrodes; (b) MOSFETs called universal VSTB MOSFET or uVSTB-FET having for both n-MOSFET and p-MOSFET the same design and material compositions of the remote Schottky Source/Drain having the same W_f and the same design and material compositions of gates having the same W_f so that its functioning as n-MOSFET or p-MOSFET depends on the signs of the applied voltages; (c) Two VSTB-FETs being n- MOSFET and p-MOSFET as complementary VSTB-FETs (called cVSTB-FET) are formed in the same gate area trench having the common gates for both types of transistors of a CMOS inverter which can have the same or different W_f's metal gate stacks for both types of MOSFETs formed on the crystalline substrate or the quasi-substrate fabricated from the crystalline or/and polycrystalline layer as a tier having the low or non-doped VSTB on the STI or/and TDL vertical wall connected at the bottom to the moderate to heavy doped substrate/well or quasi-substrate constituting a tiered VSTB-FET (t VSTB-FET) having the Source/Drain formed on one side of the VSTB and the Gate formed on opposite side of VSTB or, if desired, having the Source/Drain and the Gate formed on the same side of the VSTB called dual VSTB-FET (dVSTB-FET). If desired, bulk semiconductor (silicon) wafers or silicon-on-insulator (SOI) wafers with a thick SOI layer can be used for all types of products with no change of the product masks but fabricating different products for bulk or SOI specifications, because the VSTB-based device concepts are very flexible in using bulk or SOI wafers with no product mask redesign.

[0034] Source and Drain are heavily doped for the main CMOS devices in the mass production which makes the parasitic resistance rising up when scaling the Source/Drain sizes. In fact, the usage of the metal silicide contact to the heavily doped Source Drain layers, the method which was the main working horse for many CMOS generations, is getting more complex and it is not used any more for the Tri-Gate types of FinFETs. Forming Source/Drain from some low resistive metals and placing the metal Source/Drain closer to the channel is the best idea to reduce the parasitic resistance. The Schottky MOSFET is the architecture which is intended to reduce the parasitic Source/Drain resistance. Unfortunately, as it is described in the prior art section, placing a metal Source/Drain as the Schottky junction touching the gate-to-channel interface has resulted in many issues including the reliability which were not resolved. No successful attempts made in bringing the Schottky junction to the FinFET structures are observed. Only VSTB-FET can easily and naturally adopt the idea for future devices.

[0035] The metal gate work function stack thickness, which is about 6nm or so, cannot be made thinner due to the fundamental physical reasons of the Fermi level settling in a multi-layered structure resulting in 2D effect of the Fermi level settling at the gate edges. The Thomas-Fermi quantum screening length in metals is about Inm. Thus a material layer thickness, which is capable to have its own Fermi level, is settled at about 3nm which is about three quantum screening lengths of Inm. The multi!ayered structure is needed to integrate the dual work function metal gate integration scheme as it is discussed above. Only VSTB-FET device concept can be easily and naturally modified to mitigate or to remove these detrimental 2D effects for future devices as invented and described in this patent. [0036] A recently invented semiconductor device comprises a semiconducting low-doped Vertical Super-Thin Body (VSTB) formed on a dielectric body wall, such as the STI wall, as an isolating substrate having the VSTB body connection to the bulk semiconductor wafer on the bottom side, to an isolation cap on the top side, to the Source and Drain on the STI side, to the gate dielectric stack and gate electrode stack on the side opposite the STI- VSTB interface, resulting in a Field Effect Transistor (VSTB-FET). The device is very suitable for fabricating a low resistive metal Source/Drain by adopting a Schottky junction Source/Drain remotely placed from the gate- to-channel interface having no negative effects on the gate dielectric reliability. A Tunneling MOSFET is also easy to form taking advantage of the Source/Drain formation method in the holes/trenches etched in the dielectric body wherein using appropriate materials. When the Schottky junction is located remote from the gate-channel interface on the opposite VSTB wall to the gate VSTB wail but very close to the inversion layer, the Schottky material work function starts significantly affecting the V_t and this means for ν_ώ adjustment is a new knob for \½, engineering as discussed below. If desired, a skilled-in-the-art specialist can engineer and form the Source Drain from materials having appropriate work functions and tunneling barriers as well as barrier materials to prevent any chemical interaction of the VSTB semiconductor material with the Source/Drain forming materials. To this extent any heterogeneous junctions ca be formed as the VSTB-FET Source/Drain stack providing appropriate switching characteristics of the VSTB-FET. "Gate first" or "Gate last" approaches ca be easily implemented depending on applications and lithography capabilities available. Single or many VSTB-FET devices can be fabricated in a single active area with VSTB body isolation between devices by iso-plugs combined with the gate electrode isolation by iso-trenches or simply using cut masks to remove the hard mask for forming VSTB and removing VSTB wherever it is not needed. If desired, for high radiation hardness applications, or other applications where individual devices must be electrically decoupled from one another and the substrate, the VSTB body can be easily made as a VSTB SOI MOSFET on a thick SOI substrate. The current can flow horizontally with Source and Drain at the VSTB left and right sides or vertically with Source and Drain at the VSTB bottom and top respectively. If desired, a device can also be made as a single nanowire or a set of nanowires MOSFETs on the insulating wall such as the STI wall resulting in a nanowire-based VSTB-nWi-FET device. The following products can be made with advanced VSTB-FET described here: (i) the high performance (HP) products like microprocessors (μΡ) and SoCs having embedded DRAM (eD AM), embedded SRAM, and / or embedded Flash (typically NOR but could be NAND); (ii) Low Power (LP) and Ultra-Low Power (ULP) SoC products designed to enable smartphones and other mobile devices having a low leakage specification at or below 0.1 ηΑ/μηι; (iii) Analog / RF and many other ASIC products. The absence of doping in the advanced VSTB-FET channel results in absence of the threshold voltage (Vjh) variability related to the random dopant fluctuation which is the main component of V_t variability in the standard CMOS technology because of using highly doped substrate. Low V_th variability enables the advanced VSTB-FET to be suitable for all FEP !JLSI, microprocessors, SRAM, DRAM, Flash, analog IC, RF and mixed-signal ICs, CMOS IS (Image Sensors), and SoC applications. Thus the semiconductor industry needs an innovation to implement those devices, preferably using a single unified device concept like the VSTB-FET for a broad usage in the semiconductor industry. A plurality of tiers can be formed where in the first tier the crystalline substrate can be used whereas in upper tiers the crystalline or poly-crystalline (like poly-Si) quasi- substrate of lOnm to lOOOnm thickness and Thick Dielectric Layer (TDL) having the TDL thickness in a range from lOnm to 3000nm or so depending on product specifications, can be used to form a low or non-doped VSTB connected to the moderate or heavy doped quasi -substrate or isolated substrate like in the SOI process having thick SOI layer in a range from lOnm to lOOOnm. The usage of the Schottky junction based Source/Drain electrodes placed remote from the channel - gate interface reduces the TB dramatically and opens up a process integration path of using "Gate last" and "Gate First" processes interchangeable easily and introduces a novel integration scheme like "the gate dielectric formation first and metal gate last" in a simple way. Also forming multi- tiers IC using a simple process integration due to no needs in high temperatures for tiers processing becomes very attractive. [0037] The present invention is related to a set of universal devices usable in the common SoC platform made of VSTB semiconductor on Dielectric-Wall structures and methods of their fabrication. The set includes: sVSTB-FET, u VSTB-FET, cVSTB-FET, dVSTB-FET and others similar to those device architectures.

[0038] The present invention is related to a universal set of devices usable in the SoCs and other ULSI and made of VSTB Semiconductor on Dielectric-Wail structures and methods of their fabrication. The set includes specifically the Vertically Stackable NAND (VS-NA D) Flash Array of Single Gate FEMT (VSTB-FEMT) by adopting a tier-by-tier or some total vertical integration concepts,

[0039] There are three main CMOS devices in mass production for technology nodes at and below 20nm: (i) Tri-Gate, as variation of the bulk vertical Fin Double Gate MOSFET (although it is called a three-gate structure, in a critical consideration the device is actually of the Double Gate type) with non-doped channel; (ii) the standard planar MOSFET with heavily doped channel (iii) planar Fully Depleted SOI (FD-SOI) MOSFET fabricated on thin Buried Oxide (BOX) as the planar, non-doped channel Single Gate device. By today there is no known CMOS manufacturable technology integrating any Flash NAND or NOR cell with non-doped channel devices integrated into Tri-Gate or FD-SOI technology nodes at or below 20nm. The CMOS technology with the heavily doped channels comes to the end of scaling for Flash memory applications due to excessively high doping resulting in high leakage, high noise and high threshold voltage (V_t ) mismatch because of the random dopant fluctuations which make any ^'NVM cell perform poorly in Program, Erase, Disturb, and Retention operational conditions. Due to the same reasons the Sense Amplifiers (SensAmps) and some other critical periphery integrated circuits have low performance. Using the VSTB-FET device design constructive layers one can solve the challenges to design and to integrate into CMOS technologies many different types of NVMs with non-doped channels in single and multi-tier architectures for the technology nodes at and below 20nm. This invention solves these challenges. The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly to a universal set of devices and methods of their fabrication usable in the stand-alone NAND or NOR Flash arrays and in System-on-Chip (SoC) designs having embedded NAND or NOR Flash arrays made of the basic structures (i) crystalline, poiycrystal!ine, or amorphous Vertical Super-Thin Body (VSTB) Semiconductor attached on one side to a Vertical Dielectric Wall of a Shallow or Deep Trench Isolation (hereafter referred to as STI) or a Thick Dielectric Layer (TDL) and attached on the opposite side to the dummy dielectric formed on the inter-tier dielectric layers; and (ii) crystalline, polycrystalline, or amorphous VSTB attached on one side to a Vertical Dielectric Wall of an STI or TDL and attached on the opposite si-xle to the dummy dielectric formed on the quasi-substrate made of a moderately to highly doped polycrystalline semiconductor layer of 10 nanometers (nm) to lOOOnm thickness, like poly-Si, where the VSTB is electrically connected to the quasi-substrate, and where both of the basic structures are formed by having the VSTB Protective Cap placed between the STI or TDL Protective Caps, and having these protective caps be mutually selectively etchabie. The universal set of devices includes: (a) a VSTB-FET and an Integrated Circuit (IC) based on the VSTB-FET made as a tier and fabricated from the polycrystalline VSTB on the TDL vertical wall having the Source and Drain (SD) formed on one side of VSTB and the Gate formed on opposite side of VSTB or, if desired, having the SD and the Gate formed on the same side of the VSTB where, if desired, the IC can be a tier of a memory like Vertically Stackable Static Random Access Memory (VS-SRAM) or eDRAM placed on the top of the IC made of c-Si on the lowest level (tier) of the plurality of the tiers of IC; (b) a tier of a Vertically Stackable NAND (VS-NAND) or/and VS-NOR Flash Array of Field Effect Memory Transistors (VSTB-FEMT) formed of the Single Gate NVM cells having the dielectric gate stack formed as the memory stack based on Charge Trap media, isolated Floating Gate, or Ferroelectrics where if desired a plurality of the VSTB-FEMT based tiers can be fabricated as a vertical stack of the electrically isolated tiers having the horizontal bit lines and horizontal Word-Line (WL) in a tier; and (c) a multi-tier NAM) Flash vertically integrated with the horizontal bit lines and vertical WLs comprising the Single Gate NVM ceil 3D array. STI depth can be in a range from lOOOnm to lOnm or so depending on product specifications. If desired, bulk semiconductor (silicon) base wafers or Silicon -On- I sulator (SOI) wafers with a thick SOI layer in a range from lOnm to 300nm can be used interchangeably for all types of products with no change required to the product masks in order to fabricate different products for bulk or SOI specifications, because the VSTB-based device concepts are very adaptable for using either bulk or SOI wafers without requiring a product mask redesign.

[0040] The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly the invention is related to a universal set of devices usable in the Common Platform SoC's and CMOS Imagers made of VSTB Semiconductor on Dielectric- Wall structures and methods of their fabrication. The set includes: CMOS IS pixel array made of a MOS-PD with V ertical Gate (VG-MOS-PD) complemented with the switching transistors (T_x, R_x, D_x, and S_x) fabricated having the standard planar MOSFET's or, if desired, VSTB-FET's or Vertical or Planar Gate CCD structures for charge transfer from the VG-MOS-PD to the FD. The universal set of devices and methods of their fabrication usable in the CMOS Image Sensors (CMOS IS) having a Vertical Gate MOS-Photo-Diode instead of a buried planar p-n-j unction diode formed from the basic structures: (i) crystalline or polyciystalline Semiconductor Vertical Super- Thin Body (VSTB) on a Vertical Dielectric Wall of a Shallow or Deep Trench Isolation (hereafter referred as STI) or a Thick Dielectric Layer (TDL) and (ii) crystalline or polyciystalline VSTB Semiconductor formed under the VSTB Protective Cap placed between the STI or TDL Protective Cap and the Vertical Thick Body (VTB or Bar) Protective Cap having the STI or TDL placed on the bulk or SOI semiconductor substrate. The universal set of devices comprises a few different designs of CMOS IS arrays made of MOS-Photo Diodes with Vertical Gate (VG-MOS-PD) complemented with the switching Transistors in a pixel (T_x, R_x, D_x, S_x and the like) fabricated as the standard planar MOSFET's or VSTB-FET's utilizing the basic structures for fabricating the devices. The STI depth can be in a range from lOnm to lOOOnm or so depending on product specifications. If desired, bulk semiconductor (silicon) wafers or SOI wafers with a thick SOI layer in a range from lOnm to lOOOnm can be used for all type of products with no change of the product masks but fabricating different products for bulk or SOI specifications, because the VSTB-based device concepts are very flexible in using bulk or SOI wafer with no a product mask redesign. In case of using a crystalline or poly crystal line SOI a low resistive electrical connection of the SOI bottom layer portion to an outside contact is needed to avoid the floating body effects when the VG-MOS-PD functions having electron-hole generation by the light absorption.

[0041] The present invention is related to the field of semiconductor integrated circuit manufacturing, and more particularly to a universal set of devices and methods of their fabrication usable in the Charge Coupled Device Image Sensors (CCD IS). The universal set of devices includes different types of the CCD IS pixel array made of Vertical Gate MOS-Photo Diodes (VG- MOS-PD) for the light sensing and Vertical Gates Charge Coupled Devices (VG-CCD) for the charge retention and transfer to the charge-to-voltage converter and to the Analog to Digital Converter (ADC).

[0042] Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.

BRIEF DESCRIPTION OF THE DRAWINGS [0043] (lists, updated with new figure numbers)

[0044] Fig. 1A (Prior art). A cross-section of a standard planar MOSFET. Details of Source and Drain structure, such as LDD-layers, a possibly epitaxial raised Source/Drain layers, and so on are not shown for simplicity of MOSFET schematic representation.

[0045] Fig. IB (Prior art). A cross-section of a planar Schottky MOSFET having the Schottky junction between the inversion channel and the Source/Drain metallic layer placed to be extended under the gate edge.

[0046] Fig. 2 (Prior art). Schematic views of a horizontal cross-section at about mid-depth of Tri-Gate Fin to illustrate some principle layers of the Tri-Gate MOSFET and 2D features of the metal gate stack structure determining the work function non-uniformity along the channel. [0047] Fig. 3 (Prior art). A 3D illustration of all the principle layers of the VSTB-FET for broad applications. Some parts are removed for clarity of the locations of the most important layers.

[0048] Fig. 4 (Prior art). Schematic views of a vertical cross-section at the gate-to-source overlap area to illustrate some principle l ayers of the VSTB-FET. [0049] Fig. 5 (Prior art). Schematic views of a horizontal cross-section at about mid-depth of VSTB to illustrate some principle layers of the VSTB-FET and 2D features of the metal gate stack determining the work function (encircled by the dashed ellipse).

[0050] Fig. 6 (Prior art). A 3D illustration of all the principle layers of a VSTB-FET for broad applications. Some parts are removed for clarity of the locations of the most important layers.

[0051] Fig. 7 (Prior art). A Cross-sectional vertical schematic view of the VSTB-FET ihrough the gate-to-source overlap area.

[0052] Fig. 8 (Prior art), A Cross-sectional horizontal schematic view of the VSTB-FET through the horizontal cross-section at the mid-depth of VSTB to illustrate all the principle layers of the VSTB-FET,

[0053] Fig, 9 (Prior art). A cross-section of a standard planar memory device: MOSFEMT.

[0054] Fig, 10 (Prior art). A cross-section of a NAND Flash row of a Flash array fabricated as a series of the MOSFEMT with common Source and Drain with no Sources and Drains between the MOSFEMT in a row. [0055] Fig. 11 (Prior art). A 3D illustration of a Vertical 3D stackable NAND array with a Horizontal Word-Line outside and a vertical Bit-Line inside. The cell is the Gate-Ail-Around MOSFEMT.

[0056] Fig. 12 (Prior art). A 3D illustration of a Vertical 3D stackable N AND array with a Vertical Word-Line outside and a Horizontal Bit-Line inside. The ceil is the Double Gate MOSFEMT,

[0057] Fig. 13 (Prior art). A TEM cross-section of two Columns of a fabricated N AND Flash array as a Vertical 3D stackable NAND array having 8 Programmable Layers (PL1 to PL8) with a Vertical Word-Line outside of a Horizontal Bit-Line being inside (a). The cell is the Double Gate MOSFEMT with the memory stack: BE-SONOS (or SONONOS) types as indicated by layers from J to 5 in (b).

[0058] Fig. 14 (Prior art), A generic layout view of a NAND Flash column having two Bit- Lines in a single trench with 2 bits per super-cell fabricated using VSTB-FEMT concept.

[0059] Fig. 15 (Prior art), A cross-section view of a super-cell along the Word-Line of a NAND Flash column with 2 bits per super-cell fabricated using VSTB-FET concept having the memory stack left on the top of the isolation layers. [0060] Fig. 16 (Prior art). A cross-section view of a super-cell along the Word-Line of a NAND Flash column with 2 bits per super-cell fabricated using VSTB-FET design having the memory stack removed from the top of the isolation layers and the bottom of the trench by "spacer like process", [0061] Fig. 17 (Prior art). A schematic hybrid representation of a generic CMOS IS pixel with the cross-sectional presentation of the PD and FD and an electrical equivalent circuitry of the four switching transistors.

[0062] Fig. 18 (Prior art). A layout view of a CMOS IS pixel with two PD's and common for both PD's switching circuitry. [0063] Fig. 19 (Prior art). A cross-section view of a three-phase CCD and a schematic of its functioning in a light generated charge accumulation mode and a charge transfer mode.

[0064] Fig. 20 (Prior art). A cross-section view of a three-phase planar CCD IS and a schematic of its functioning in the charge accumulation mode of the charge generated by the light under phase Y-_h charge retention mode under phase V₂ and the charge transfer mode from the phase Vi to the phase V₂.

[0065] Fig, 21 A. Cross-sectional view of VSTB-FET at about middle of the Source/Drain - to - Gate overlap length of the VSTB having the Schottky junction Source-Drain (metal Source/Drain VSTB-FET) placed on the VSTB surface that does not touch the Gate-VSTB interface in the low or non-doped Source-Drain regions. [0066] Fig. 21B. Schematic views of a horizontal cross-section at about Fin mid-depth of VSTB-FET to illustrate some principle layers of the s VSTB-FET illustrating the remote placement of the Schottky contact to the VSTB formed as an ultrathin layer of metal nitride based Schottky junction made of TiN and materials like this connected to the Source/Drain filiing-in layer made of a low resistive metal or alloy. [0067] Fig. 22, Schematic views of a horizontal cross-section at about Fin mid-depth of VSTB-FET to illustrate some principle layers of the s VSTB-FET illustrating the remote placement of the Schottky contact to the VSTB fonned as a metal silicide layer consuming about a half of the VTSB thickness and made of WSi2, NiSi, and the like connected to the Source/Drain fil!ing-in layer made of a low resistive metal or alloy. [0068] Fig. 23. Cross-sectional view of VSTB-FET at about mid-height of the VSTB having no 2D metal work function effects formed by a ultra-thin Schottky junction Source-Drain layer placed on the VSTB surface in the low or non-doped Source-Drain regions that does not touch the Gate-VSTB interface.

[0069] Fig. 24. A cross-sectional view of a CMOS inverter in a single gate trench having the single work functions architecture with the common gate metal work function layer for p-channel and n-channel MOSFETs called uVSTB-FET device architecture having in the crystalline substrate one VSTB connected to the p-doped layer (or p-well) and another VSTB connected to the n-doped layer (or n-well) thus defining n-MOSFET or p-MOSFET by being connected to the p-doped "substrate" layer or the n-doped "substrate" layer, correspondingly.

[0070] Fig. 25. A cross-sectional view of a CMOS inverter in a single gate trench having the dual work functions architecture with different gate metal work function layers for p-channel and n- channel MOSFETs.

[0071] Fig. 26. A cross-sectional view of a stackable architecture having, as an example, a cVSTB-FET in the bottom crystalline substrate and the tiered tVSTB-FET in a tier being isolated from the bottom tier by an isolation layer. [0072] Fig, 27. A 3D view of all the principle layers of the dVSTB-FET for broad applications is schematically illustrated adopting the Gate first method. Some parts are removed for clarity of the locations of the most important layers.

[0073] Fig. 28. A 3D view of all the principle layers of the dVSTB-FET for broad applications is schematically illustrated adopting the Gate last metliod. Some parts are removed for clarity of the locations of the most important layers.

[0074] Fig. 29. 2D cross-sectional view of key layers across the gate area, as indicated by line 29-29 in Fig. 27, of the dVSTB-FET is schematically shown being similar for both the Gate last and Gate first methods of fabrication.

[0075] Fig. 30. 2D cross-sectional view of key layers across the Source/Drain area, as indicated by line 30-30 in Fig. 27, of the dVSTB-FET is schematically shown being similar for both the Gate last and Gate first methods of fabrication.

[0076] Fig. 31. dVSTB-FET horizontal cross-sections at about a half of the VSTB height for the Gate First method illustrating the key layers as they appeal" for a top view observer.

[0077] Fig. 32. dVSTB-FET horizontal cross-sections at about a half of the VSTB height for the Gate Last method as they appear for a top view observer. [0078] Fig. 33. Process flow step-by-step to form the Gate and Source/Drain for the Gate first method during the dVSTB-FET fabrication.

[0079] Fig. 34A to Fig. 341. Cross-sectional views corresponding the layer formations in step-by-step process flow description of a process flow to form the Gate and Source/Drain for the Gate first method of dVSTB-FET fabrication.

[0080] Fig. 35. Process flow to form the Gate and Source/Drain for the Gate last method of dVSTB-FET fabrication.

[0081] Fig. 36A to Fig. 36H. Cross-sectional views corresponding the layer formations in step-by-step process flow description of a process flow to form the Gate and Source/Drain for the Gate last method of dVSTB-FET fabrication.

[0082] Fig, 37, A cross-sectional view of a tier basic structure for fabricating the multi- stackable architectures of any VSTB-based devices formed as a stackabie Integrated Circuit Layer (ICL) on an isolator fonned in the tier comprising a multi-layered stack of the key layers of a tier bottom isolation layer and a TDL having a VSTB formed in the tier. VSTB can be form, for instance, from a crystalline, polycrystalline or amorphous semiconductor (like silicon) for fabricating a VSTB-FET based ICL and memory.

[0083] Fig. 38. A cross-sectional view of a tier basic structure for fabricating the stackabie architectures of any VSTB-based devices formed in the tier compri sing a multi-layered stack of the key layers of a tier bottom isolation layer, a semiconducting low resistivity layer (or the quasi - substrate), and TDL having a VSTB formed in the tier.

[0084] Fig, 39. A cross-sectional view of a Flash-array tier of the multi -stackabie architecture with Horizontal Bit-Lines and Horizontal Word-Lines fabricated with using a semiconductor VSTB. Source and Drain as well as the Select transistors for a BL are located in front and behind the cross-section drawn and not shown here, [0085] Fig. 40. A cross-sectional view of a 3D NAND Flash memory stack architecture made of a plurality of ICL' s being the isolated Flash-array tiers in this particular embodiment with horizontal Bit-Lines and horizontal Word-Lines in Flash-array tiers stacked vertically. The first layer in the stack is made of c-Si substrate whereas the other layers on the top can be made of the Flash array tiers fabricated as the ICL's having the poly-Si VSTB-FET and VSTB-FEMT. [0086] Fig. 41. A. The very top view of the multi -stackabie architecture with Horizontal Bit- Lines (BL) and Horizontal Word-Lines (WL) in Flash-array layers. "Horizontal" means both directions within a tier and no WL or BL going vertically across the tiers as suggested in this invention shown in Fig. 40.

[0087] Fig. 4 IB. A top view of the multi-stackabie architecture with Horizontal Bit-Lines (BL) and Horizontal Word-Lines in Flash-array layers. A few key layers are made visible by showing the WL schematically by bold arrows and indicating where the BL VSTB strips top, Memory Stack top, and the Word-Line electrode to the memory stack are located as shown in Fig. 40.

[0088] Fig. 42. A schematics of Process integration flow for a Flash-array tier formation with poly-Si VSTB and the memory stack fabrication resulting in VSTB-FEMT for a stackable Flash-array tier.

[0089] Fig. 43. Continuation of Fig. 42 of the schematics of Process Integration flow for a Flash-array tier formation with poly-Si VSTB and the memory stack fabrication resulting in VSTB- FEMT for a stackable Flash-array tier.

[0090] Fig. 44. A cross- section of the stackable Flash-array tier with poly-Si VSTB after the process step of etching the Dummy dielectric in the trench to form inter-Word-Line isolation (iso- trench) being after the process step 108 in Fig. 43.

[0091] Fig. 45. A schematics of Process Integration flow of the Source/Drain's and Source/Drain contacts formation of the stackable Flash-array tier layers with poly-Si VSTB,

[0092] Fig. 46. A cross-sectional view along the Source/Drain's and Source/Drain contacts of the stackable Flash-array tier layers with poly-Si VSTB after the process step ΓΠ in Fig. 45.

[0093] Fig. 47. A cross-sectional view of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell having the two Horizontal Bit-Lines per one Vertical Bit-Line which is connected to the periphery IC above the top tier.

[0094] Fig. 48. A cross-sectional view of schematics of Process Integration flow of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell illustrating formation of the multi-layered sandwich.

[0095] Fig. 49. . A cross-sectional view of schematics of Process Integration flow of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell illustrating formation of the deep trench in the multi-layered sandwich by anisotropic etching. [0096] Fig. 50. A cross-sectional view of schematics of Process Integration flow of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell illustrating formation of the shallow niches (trenches) in the multi-layered sandwich by lateral isotropic selective etching.

[0097] Fig. 51. A cross-sectional view of schematics of Process Integration flow of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell illustrating formation of the VSTB Bit-Lines in the niches by deposition on the VSTB material (poly-Si, for example) and etch back (like in "spacer formation process").

[0098] Fig. 52, A cross-sectional view of schematics of Process Integration flow of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell illustrating formation of the Memory stack on the VSTB wall s, on the top, and on the tren ch bottom by deposition of the dielectric stack, for example BE-SONQS and the like structures.

[0099] Fig. 53. A cross-sectional view of schematics of Process Integration flow of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell illustrating formation of the Control Gate stack on the Memory stack walls and on the structure top followed by CMP to pianarize the structure. [0100] Fig. 54. A top layout view of schematics of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell illustrating the placement of the iso-trenches by etching the Memory stack between the vertical Word-Lines followed by a dielectric deposition like PSG or TEOS followed by CMP to pianarize the structure,

[0101] Fig. 55. A cross-sectional view of two adjacent NVM cells of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell illustrating the placement of the iso-trenches on the top surface of the Memory stack (a) or on the top of the VSTB Bit-Line surface (b) being two options for forming the devices.

[0102] Fig. 56. A cross-sectional view of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell having the two Horizontal Bit-Lines per one Vertical Bit-Line which is connected to the periphery IC in the very bottom tier formed in c-Si substrate.

[0103] Fig. 57. A cross-sectional view of schematics of Process Integration flow of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell illustrating formation of the Memory stack on the VSTB walls only by exploring "spacer formation process" by deposition of the dielectric stack, for example BE-SONOS and the like or FG-based structures followed by the etch back. [0104] Fig. 58, A cross-sectional view of schematics of Process Integration flow of a vertically integrated multi-tiers NAND Flash array with a Single Gate VSTB-FEMT cell illustrating formation of the Vertical Word-Lines on the Memory stack walls by deposition of the gate electrode material or a material stack followed by CMP for planarizing the surface, [0105] Fig. 59. A cross-sectional view of the Basic Building Structure for Gate Based Devices (BBS-GBD) such as Vertical Gate MOS-PD and the Vertical Gate CCD, having the crystalline semiconductor body in a shape of a semiconductor bar with its protective caps, the STI isolation and its cap,

[0106] Fig, 60. A cross-sectional view of a Vertical Gate MOS-Diode (VG-MOS-Diode) structure attached to the STI with the thin gate electrode and the gate dielectric formed in a narrow trench anisotropicaily selectively etched in the semiconductor bar after removing the VSTB cap,

[0107] Fig. 61. A layout view of a VSTB-based CMOS IS pixel of a particular embodiment having the pixel switching circuitry (PSC) transistors made of VSTB-FET's with two separate T_x VSTB-FET's and the planar PD's and the FD. [0108] Fig, 62, A detailed layout view of the VSTB-FET T_x of the CMOS IS pixel shown in Fig. 61.

[0109] Fig. 63. A layout view of two VSTB-FET T_x fabricated in a single gate area with an iso-trench based isolation of the T_x transistors,

[0110] Fig. 64, A layout view of a CMOS IS pixel embodiment having planar MOSFET's and Vertical Gate MOS-PD's (VG-MOS-PD).

[0111] Fig. 65 and Fig. 66. A layout view and a cross-sectional view of the VG-MOS-PD, the transistor T_x and the FD to illustrate the electrical connection of the VG-MOS-PD channel to the FD by the T_x channel when the T_x gate overlaps over the VG-MOS-PD space charge region.

[0112] Fig. 67. A layout view of the CMOS IS pixel embodiment having ail PSC MOSFET' s fabricated as VSTB-FET' s and the PD fabricated as the VG-MOS-PD.

[0113] Fig. 68, A detailed layout view of a photosensitive part of a CMOS IS pixel embodiment having the VG-MOS-PD and a vertical gate CCD replacing the planar T_x MOSFET,

[0114] Fig, 69, A cross-sectional view of a VG-MOS-PD as the photosensitive part of a CMOS-IS pixel embodiment on SOI wafer. [0115] Fig. 70, A cross-sectional view of the Basic Building Structure 1 (BBS-1) for fabricating the Vertical Gate CCD IS having the STI isolation and a crystalline semiconductor V ertical Thick Body (VTB) in a shape of a bar with its protective cap on the top.

[0116] Fig. 71. A top layout view of the three phase vertical gate CCD IS (VG-CCD IS) pixel structure where CCD strings are made on the vertical walls of neighboring c-Si bars arranged as columns, having the common poly-Si gates, placed between c-Si bars and isolated by the STI from neighboring CCD strings, and the photo-sensitive devices made as VG-MOS-PD with a top surface free of a gate material to allow the light to penetrate in to the VG-MOS-PD.

[0117] Fig. 72. A cross-sectional view along the V₃ interconnects of the VG-CCD IS pixel structure shown in Fig. 71.

[0118] Fig. 73. A cross-sectional view along the VG-MOS-PD row of the VG-CCD IS pixel array shown in Fig. 71.

[0119] Fig. 74. A cross-sectional view along the V₃ interconnects of the VG-CCD IS array shown in Fig. 71 having poly-Si gates replaced by a gate stack to reduce series resistance. [0120] Fig. 75. A cross-sectional view along the CCD gates column of the VG-CCD IS pixel array shown in Fig. 71.

[0121] Fig, 76. A cross-sectional view of the Basic Building Structure 2 (BBS-2) for the Vertical Gate CCD IS having the crystalline semiconductor Vertical Thick Body (VTB) in a shape of a bar having two protective caps and the STI isolation with its protective cap, [0122] Fig. 77. A layout view of the VG-CCD IS pixel structure with the thin inter-gate dielectric isolation and a small parasitic capacitance between the gates and highly conductive V₂ and _? interconnects where two photo-sensitive devices are VG-MOS-PD' s having the common gate and STI isolations from neighboring VG-MOS-PD columns with open top to allow the light to penetrate in to VG-MOS-PD without a parasitic absorption. [0123] Fig. 78. A cross-sectional view along the 78-78 section on the top view of the vertical gate CCD IS pixel structure illustrated in Fig. 77.

[0124] Fig. 79. A cross-sectional view along the 79-79 section on the top view of the vertical gate CCD IS pixel structure illustrated in Fig. 77.

[0125] Fig, 80. A cross-sectional view along the 80-80 section of the vertical gate CCD IS pixel structure illustrated in Fig. 77. [0126] Fig. 81. A cross-sectional view along the 81-81 section indicated in Fig. 80 of the vertical gate CCD IS pixel structure.

[0127] Fig. 82. A layout view of the dense VG-CCD IS structure where the SCR of the VG- MOS-PD's of two neighboring CCD strings having the common gates and the open top to allow the light to penetrate in to VG-MOS-PD are made in the same c-Si bar.

[0128] Fig. 83. A cross-sectional view along the 83-83 section of the VG-CCD IS structure illustrated in Fig. 82.

DETAILED DESCRIPTION

I. ADVANCED SEMICONDUCTOR DEVICES MADE OF VERTICAL SUPER-THIN BODY SEMICONDUCTOR ON DIELECTRIC WALL AND METHODS OF THEIR FABRICATION

[0129] Described herein are different types of VSTB-FETs and methods of their fabrication. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to other skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practice without specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0130] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation, [0131] A method of fabrication of the Basic Building Structure (BBS) of the VSTB-FET referring to Fig. 4 (Prior Art) is as follows: (i) depositing layers of the STI hard mask on the semiconductor substrate; (ii) patterning the STI hard mask with a litho step; (iii) anisotropic etching the STI hard mask layers; (iv) fabricating the STI; (vi) recessing the STI; (v) filling in the recess with the STI cap 301 dielectric, (vi) removing the STI hard mask; (vii) forming the VSTB cap 101 in the standard spacer process on the STI hard mask edge walls; (viii) c-Si anisotropic etching using the STI cap 301 and the VSTB cap 101 as the hard mask, (ix) filling in the trench with a gate trench dielectric like TEOS 400; (x) recessing the gate trench dielectric, (xi) filling in the recess with the protective cap 45 dielectric.

[0132] The implementation of the invention described herein uses the Schottky junction Source/Drain VSTB-FET devices having the Schottky junction placed remotely on the Source- Drain side of the V STB with or without raised Source-Drain semiconductor layer formed by SEG for epitaxial c-Si or by deposition for poly-Si and separated by a distance equal to a VSTB thickness or so away from the VSTB interface with the gate without having the Schottky junction touching the gate dielectric, see Fig. 21A and Fig. 21B. This Source/Drain architecture can significantly reduce the parasitic resistance. The Schottky junction metal work function (W<) actually affects the VSTB-FET V_th and this feature of the novel advanced VSTB-FET design can be used for the V_th engineering as an extra knob for designing multi-V_th ICs. The remote Schottky junction formed in the Source Drain process as a part 5 0 of the low-doped VSTB 100 length and contacted by the metal Source/Drain metal 500/600 as key low resistive layers can be considered as a stand alone Schottky diode that can be widely used in Schottky-enhanced IC designs, where the Schottky devices are used for flexibility in an electrical adjustment of VSTB-FET' s V_thS in some products by connecting one or more such Schottky diodes in series to the Source, Thus Schottky diode as a standalone device can be used in the Schottky VLSI circuitry design. The series resistance of the Schottky junction, when VSTB-FET is on, is very low due to formation of the strong inversion layer 511 in the VSTB 100 between the Gate dielectric stack 700 and the remote Schottky junction located at the interface between the VSTB 100 and the layer 510 because the mobile charge carrier concentration in the inversion layer is very high being about 3el9cm^"3 and more. It is worthwhile to note that the VSTB thickness, providing this low resistive mechanism, must be of the same thickness as the quantum inversion layer thickness or close to it in a range from 6nm to 2nm or so. The maximal temperature needed for the doping activation and diffusion toward the channel-source and channel-drain junctions to place them under the gate is not necessarily any more, thus providing a low temperature process integration flow for the first time by using this device design. The VSTB-FET with the Source-Drain formed using the remote Schottky junction results in a new device architecture called sVSTB-FET. Absence of high temperature anneals during the sVSTB-FET fabrication makes them suitable and easily integrated into the multi-tier IC architectures. The "Gate First" integration scheme can now be easy to implement for the new device designs with no the 2D work function effects. Above all the s VSTB-FET has a strong benefit related to the absence of the Source random dopant fluctuations (RDF) effect and Vui variability associated with this phenomenon where it is one of the major mechanisms of the V_th variability for any non-doped channel devices. Also the sVSTB-FET has negligible or no DIBL due to little penetration of the Drain electric field towards the Source Schottky barrier plane which is orthogonal to the channel electric field coming from the Drain. Another beneficial feature of the sVSTB-FET is that, the mid-gap work function metals and alloys are defined as metals/alloys having the work function in a range from 4.4eV to 4.6eV in a rigorous definition and in an engineering definition the range is from 4.3eV to 4.7eV. The manufacturability of the mid-gap metal Schottky junctions is rather high because of a negligible effect of the so called Metal Induced Interfacial Trap formation which is especially strong for the metals with work function below 4.3eV resulting in Fermi level pinning effect at the interface and poor control over the Schottky barrier. Another feature of the sVSTB-FET is that, it can be argued, based on the Schottky junction physics, accounting for the quantum confinement of the inversion layer as the semiconductor side of the junction that the mobile charge concentration at the semiconductor side is variable and gets increased with the gate voltage. This effect makes the sVSTB-FET switching characteristic in Log(I_d)-Vg metric significantly steeper so that the Subthreshold Slope (SS) parameter is expected to be much less than the theoretical minimal limit of ~60mV/decade as for the standard MOSFET. The direct tunneling of the carriers from the remote Schottky junction metal Fermi level to the zero and upper sub-bands of the inversion layer results in a very low contact specific resistivity and the total parasitic resistance enhancing the drive current.

[0133] To reduce the Source/Drain parasitic resistance further, the metal Source/Drain, based on the remote Schottky junction, can be brought even closer to the interface between the gate dielectric and the channel by using metal silicide based materials 512 as it is illustrated in Fig. 22. This design is similar to the device design shown in Figs. 21A-B from the functioning point of view but it has a different process flow of fabricating it. After the Source/Drain holes etching and exposing the VSTB 100 surface to the SEG of a low or non-doped ultra-thin c-Si layer or deposition of a low or non-doped ultra-thin poly-Si layer, an ultra-thin metal layer in a thickness range from lnm to lOnm is deposited like Ni, Co, W, Ti, Mo, or their alloys and the like followed by a low temperature anneal to form the metal silicide followed by a ultra-thin layer deposition of a barrier layer like TiN to prevent any chemical interaction between the metal silicide and a metal layer deposited after in to the rest of the Source/Drain hole area followed by CMP to finish the Source/Drain formation process. The barrier layer is not shown in Fig. 22 for simplicity of the picture which would be a thin layer along the perimeter of the Source/Drain areas 500 and 600. If desired, the metal silicide 512 formation can be made at the expense of the portion of the VSTB thickness by depositing a metal layer for the silicide formation a bit thicker that SEG layer or poly- Si thickness. For different metals listed above there is a unique ratio of the silicide thickness formed to the metal thickness deposited so that an engineer, experienced in the art, can select the right metal thickness and SEG / poly- Si layer thickness to produce the silicide thickness which is placed remote from the gate dielectric to the channel interface by at least 2nm to 4nm or so. [0134] A "Gate First" integration scheme is most preferable to fabricate the VSTB-FET with no 2D work function effect. Fig. 23 illustrates a cross-sectional view of a particular embodiment of the VSTB-FET with no 2D work function effect. Fig. 21A helps understand the vertical cross- sectional view of the device shown in Fig. 23. A integration process flow "A" has the following steps partially similar to a method of fabrication of the Basic Building Structure (BBS) in this particular embodiment: (i) deposition of the STI hard mask layers on the semiconductor substrate; (ii) a Litho step for patterning the STI hard mask; (iii) anisotropic etching of the STI hard mask layers; (iv) forming the VSTB hard mask being the VSTB cap 101 in the standard spacer formation process on the STI hard mask edge walls, (v) fabricating the STI isolation 300; (vi) recessing the STI; (vii) filling in the recess with the STI cap dielectric 301; (viii) removing the STI hard mask; (ix) anisotropic etching of c-Si to form the gate trench followed by an ion implantation steps of appropriate dopant type for doping the sub-Fin regions 202 by n-type dopant for p-MOSFET and p-type dopant for n-MOSFET, followed by the thermal anneal for doping activation and redistribution towards the STFs VSTB interface; (x) deposition of HDP or TEOS Si 02 materials or the like to fill-in a gate trench by a dielectric, followed by CMP to planarize the surface; (xi) recess of the gate trench dielectri c leaving a certain dielectric thickness 400 in a range from 3nm to 50nm at the bottom of the trench to reduce the gate-to-substrate capacitance; (xii) formation process of a gate dielectric stack 700 including an interfacial oxide formation by, for example, a thermal oxidation and a high-k layer deposition; (xiii) a deposition of the gate work function material stack with a required work functions, for example, in case of the dual gate work functions integration scheme, assuming p-MOSFET (n-MOSFET) gate work function metal is deposited first, a Litho step is applied and a removal of the first gate work function metal is performed in the n-MOSFET (p-MOSFET) gate area followed by the n-MOSFET (p-MOSFET) gate work function metal deposition and the barrier layer deposition, to prevent the work function change by the gate metal filling-in layer, followed by the metal filling-in layer 800 deposition (if the volume permits) followed by the CMP pianarization step with the STI cap 301 as the etch stop layer; (xiv) deposition of poly- Si layer, (xv) a litho step for gate patterning followed by poly-Si etching and a photoresist removing; (xvi) selective anisotropic etching of the gate electrode metals with the etch stop layer being the high-k gate dielectric layer; (xvii) deposition of the inter-gate dielectric layer 902 typically formed from a SiC02 or material like this having a high etch selectivity to the poly- Si, Si02, SiN, A1203, and so on used in the Source/Drain formation areas followed by CMP for planarization till the top of poly-Si; (xviii) recess of the isolation layer 902 and deposition of the cap SiN layer in the recess followed by CMP; (xix) a litho step to pattern and to open the Source/Drain areas / holes followed by selective anisotropic etching of the SiN cap layer, the inter-gate dielectric layer 902, occurring over Source/Drain areas, the STI cap 301, and the STI dielectric 300 with stopping at a depth being 5% shallower than the gate metal depth having the poly-Si dummy gate and the VSTB cap 101 serve as a hard mask to self-align Source/Drain to the gate and to the VSTB, followed by a photoresist removing; (xx) a deposition of the metal layer or a composite or a metal stack 510 being about a mid-gap work function material to form the Schottky junction and the metal stack deposition to fill in Source/Drain 500 and 600 followed by the CMP; (xxi) recess of the Source/Drain metals till the top of the STI cap 301; (xxii) a dielectric spacer formation which can be made of SiCON and the like iower-k dielectrics in the recess wall including the dummy poly-Si wall on one side of the recess area; (xxiii) filing in the recess with TEOS Si02 by blanket Si02 deposition followed by CMP; (xxiv) removal of dummy gate poly-Si by a selective etch followed by the gate metal dielectric cap etch if it is pre-formed there as optional step; (xxv) the metal stack deposition to fill the gate trench having this gate trenches as metal-0 local interconnect followed by the CMP, followed by the metal stack cap formation, if desired; (xxvi) Source Drain recess formation by removal of the dielectric from the top Source/Drain areas made typically of TEOS Si02 by selective etch; (xxvii) the metal stack deposition to fill the Source/Drain recess followed by the CMP till the top of the layer 902 or its cap followed by the protective layer (cap) formation by the standard set of steps: recess, deposition, CMP, (xxviii) deposition of an interlayer dielectric stack for forming the contacts to the Source/Drain and Gate in it. In case of a not perfect etch depth control by etching time, a slight mismatch of the Source Drain depth being deeper than the gate depth might result in a weaker electrostatic control of the gate over the VSTB channel but having the sub-Fin doping layer 202 this issue is significantly mitigated or even removed,

[0135] An alternative integration flow "B" can be suggested being slightly different as compared to a previously described flow "A" referencing to Fig. 23. The first group of steps is the same as previously described process integration flow "A". After the gate metal stack is formed another integration process can be used as follows: (a) recess of the metal gate stack and cap layer formation by a cap dielectric deposition followed by the CMP (not shown in Fig, 21 A for simplicity); (b) deposition of the interlayer dielectric stack typically formed from a Si02 and SiN layers; (c) Litho step for gate patterning and etching the gate trench in the interlayer dielectric stack followed by the dummy gate fill with a material being selectively non-etched serving as a cap layer when etching the interlayer dielectric stack, gate metal stack cap, and gate metal stack itself like poly-silicon or the like and CMP for plananzation the surface; (d) Litho step for patterning the inter- gate isolation areas 902 having the litho openings slightly overlapped (by 5% to 10% of the critical sizes) with the gate dummy layers and VSTB caps / STI caps followed by the interlayer dielectric stack etching, selective etching of the gate cap for having self-alignment to the gate area, followed by the selective anisotropic gate metal stack 800 and 703 etching away with the stopping layer being the high-k gate dielectric layer; (e) deposition of the integrate isolation layer 902 followed by CMP for planarization; (f) recess of the inter-gate isolation layer 902 followed by a deposition of the cap dielectric layer which can be made of the same material as the gate metal stack cap or the VSTB cap layer; (g) the Source/Drain formation module which is almost the same as in the previous integration process "A" with the final step of forming a recess of the Source/Drain metal stack 510 and 500/600 areas and depositing Source/Drain dielectric cap layer followed by CMP for planarization (this step is optional for protecting the Source/Drain metal material from the oxidation and moisture absorption during the next processing steps if the Source/Drain metal material of choice is sensitive to it like W and some others (the cap layer is also helpful for the self-aligned gate contact formation later on); (h) selective etching of the dummy gate trench material followed by gate spacer formation by deposition/etch of a spacer dielectric layer followed by the etching of the gate metal stack cap followed by the metal layer interconnect deposition being metal-zero interconnect; (i) the metal dielectric cap formation by the metal interconnect recess followed by the dielectric cap material deposition followed by CMP for the planarization; (j) deposition of a dielectric layer or stack for the contact formation between the Source/Drain and Gate layers and the metal- 1 interconnects. A specialist experienced in the art can suggest some other process integration flows, using the flows "A" and "B" as examples of the basic processes, but it cannot likely constitute inventions.

[0136] A particular embodiment of the sVSTB-FET invention having the simplest design and process integration can have a wide usage because of having the same design and material compositions of n-channel VSTB-FET and p-channel VSTB-FET called a universal VSTB-FET (uVSTB-FET). The uVSTB-FET has the remote Schottky Source/Drain layer 510 formed from the mid-gap W_f material and the Gate electrode layer 703 formed from the mid-gap W_f material as well for both n-channel and p-channel. Due to mid-gate Wf usage, uVSTB-FET has V_th in a range from the standard to high magnitude and can be used in a low power and ultra low power high performance applications and/or analog RF CMOS and SoC applications, hi a CMOS technology the uVSTB-FETs having the common low doped VSTB are functioning as the n-ehannel MOSFET with the positive Gate voltage and Vs=0 and/or as the p-channel MOSFET with the "negative" Gate voltage at Vs=^::V_dd. The VSTB of the uVSTB-FETs can be fabricated both from the low doped n-substrate and from the low doped p-substrate. The p-channel uVSTB-FET can be fabricated on the low p-doped substrate 200 having a moderately to high n-doped buried layer 202 under the p- channel at the bottom of the VSTB and the n-channel uVSTB-FET can be fabricated on the low n- doped substrate 200 having a moderately to high p-doped buried layer 202 under the n-channel at the bottom of the VSTB, see Fig. 24. The n-channel and p-channel uVSTB-FETs can be made simultaneously using the same processes that will give a significant manufacturing simplification. The remote Schottky Source/Drain can be formed in many different ways as illustrated in Fig. 2 IB, Fig. 22, and Fig. 23. As for a generic process integration flow for fabrication of these types of devices it is rather straightforward and obvious how to form them from the description given above by the flow "A" and "B". The design provides the highest device density architecture. Thus all MOSFET' s in a CMOS technology are made the same and the functions as n-channel or p-channel MOSFET depend on the Gate voltage sign and on whether V_s=0 or

having Drains placed in between of two cVSTB-FETs, provided an n-well or n-doped layer for p-channel MOSFETs in the p-doped bulk wafer or in a deep p-well or p-doped deep layer is formed in a deep n-well for n~ channel MOSFETs or vise versa. The truly same design and manufacturing process are applied for n-channel and p-channel uVSTB-FETs if SOI wafer or an isolated tier of stackable CMOS IC is used. The mid-gap W_f materials being 4.5 eV for the remote Schottky Sources and Drains and for the Gates provide a standard V_¾ (HP applications). If the common W_f is made slightly by 0.1 eV to 0.2eV higher than mid-gap Wf then a high V^ n-channel can be made suitable for ULP application and a ultra-low . If the common W_f is made slightly by 0.1 eV to 0.2eV lower than mid-gap W_f then a low n-channel / high V_th p-channel can be made which is ideally suitable for the Analog / RF applications. Thus there many ways of engineering V_th, for example, having the mid-gap gate W_f provides a knob for adjusting a Vt_h shift by the remote Schottky Source-Drain W_f down or up to move V_fe in opposite directions: if W_f is up then the n-channel V_th is up and the p-channel V^ is down and vise versa. Another knob to design V_th is having the mid-gap Source-Drain W_f and manipulating V_th by the Gate stacks W_f for n-channel and p-channel. For more advanced CMOS technological capabilities four W_f can be designed by an appropriate material composition having two W_f for the remote Schottky Source-Drains and two W_f for the Gates of n-channel and p~ channel sVSTB-FETs, which provides the most flexible set of V _h's for SoC applications. The remote Schottky Source/Drain can be formed in many different ways as illustrated in Fig. 21B, Fig. 22, and Fig. 23. [0137] A very manufacturable way of engineering a few V<_h in the same die, which is important for SoC, can be made by adjusting the VSTB thickness through engineering the VSTB cap width. The physical phenomenon standing behind this method is that: it is recently established that the semiconductor energy gap E₈ depends on the Fin thickness if the thickness is below 4nm. It is also known that the higher the E_g the higher the V_th of a MOSFET is going to be. For example, for Fin thickness 4 nm the E_g=l .l eV for the c-Si vs. E_g=T.5eV for the Fin thickness of about 2.5nm. Though the exact function of Ε₈{¾) needs to be characterized more accurately the phenomenon itself is established firmly and can be used in an empirical approach for V_th engineering. In the process integration flow "A" and "B" described above a set of the VSTB hard masks (caps) widths has to be fabricated in a different way. There are two ways of making the set suggested to patent in here. Way 1 : the widest VSTB hard mask is formed first followed by a Litho step to open the areas where a narrower VSTB hard mask is needed, followed by a trimming of the widest hard mask. Then another Litho step is applied to open other areas for further trimming of the VSTB hard masks and so on. Way 2: the widest VSTB hard mask is formed first be making the laminated spacer at the STI hard mask edge walls having the thinnest spacer covered by a few layers formed from different dielectric materials, for example, the stack: Si02, A1203, Ta_xSiO_y, SIN or something like this. A widely spread Atomic Layer Deposition (ALD) method is ideal for such processing. Then applying Lithography steps, the top SiN layer is removed, so that the trimming is done in a very controllable approach, where a thinner VSTB is needed and then Ta_xSiOy layer is removed and so on. The trimming process is a very gentle step to trim material basically by 0.25nm to 0.5nm discrete increments or so. This is because for any typical material the mono-atomic layer thickness is just about 0.25nm. For these processing specs an Atomic Layer Etch (ALE) process is the most suitable and it is coming to the industry for a wide usage. It is understood that the real hard mask widths have to be a bit wider that any targeted VSTB thicknesses accounting for a silicon budget for the VSTB surface cleaning, oxidation for the interfacial oxide formation, and, for example, for using an oxidation-etch method for a surface roughness reduction, and other processing needs consuming the silicon.

[0138] The highest density of MOSFET devices can be achieved by forming n-channel VSTB-FET and p-channel VSTB-FET in a single gate trench having the common gate constituting the u VSTB-FET inverter as illustrated in Fig. 24 where a cross-sectional view of the inverter is shown. The CMOS inverter comprises two low or non-doped VSTBs 100 attached to two STIs having the gate trench in between the VSTB having the cap 101 on the VSTB tops in between the STI and gate caps. One p-channei VSTB is connected to the crystalline substrate 200 and isolated from an n-channel VSTB by a moderate to heavy doped layer or well 202 or vise versa. The uVSTB-FET inverter has the common gate electrode comprising of layers 703 as the work function layer or stack and the gate metal 800 having the Schottky junction based metal Source/Drains remotely formed on the STI sides of the VSTB being the opposite sides of the gate. The uVSTB- FET inverter has one common Drain attached to the VSTB in the STIs 300 in two opposite sides but electrically connected through Source-Drain metal-zero interconnection, one Source for n- channel and another Source for the p-channel having all Source/Drain formed identical for certain applications as discussed above thus providing even higher device density. An interlayer dielectric 950 is deposited on the top of the inverter to isolate the uVSTB-FET inverter tier formed in the crystalline substrate from the uVSTB-FET inverter formed in an upper tier as discussed below. The substrate is the single crystalline substrate but, if desired, the uVSTB-FET inverter can be formed on SOI wafer substrate with no needs for any p-type or n-type doped wells/layers 202 at all, providing indistinguishable n-channel and p-channel uVSTB-FETs except for the ground line connected to the n-channel uVSTB-FET Source and V_dd line connected to the p-channel uVSTB- FET Source having their VSTBs functioning in the floating body mode. If desired, the remote Schottky Source/Drain design can be formed in many different ways as illustrated in Fig. 2 IB, Fig. 22, and Fig. 23. As for a generic process integration flow for fabrication of these types of devices it- is rather straightforward and obvious how to form them from the description given above. Thus a CMOS inverter as a u VSTB-FET inverter architecture in a single gate trench having the single work functions architecture with the common gate metal and Source/Drain metal work function layers for p-channel and n-channel MOSFETs is invented so that its functioning as n-MOSFET or p-MOSFET depends on the signs of the applied voltages. Of course, only n-MOSFETs or only p- MOSFETs can be formed in the same gate area trench having in the crystalline substrate a VSTB connected to the p-doped layer (or p-well) and another VSTB connected to the n-doped layer (or n- well) thus defining n-MOSFET and p-MOSFET.

[0139] To achieve a high device density and a greater flexibility in the Λ½ engineering by having different appropriate gate work function metals / metal alloys or metal / metal alloys stack, a dual gate VSTB-FET architecture is invented and Fig. 25 illustrates a cross-sectional view of a CMOS inverter using two complimentary sVSTB-FETs fabricated in a single gate trench. The CMOS inverter consists of the n-channel and p-channei VSTB-FET in a single trench and compri ses two low or non-doped VSTB 100 having the cap 101 at the top having the VSTB formed on the STI 300 opposite vertical wails and connected to the crystalline substrate 200, a moderate to heavy doped layer or well 202 separating the channel of one transistor from the substrate, a common gate electrode comprising two different gate work function metal layers 703 and 706 and the common gate high conductive layer 800, and the metal Source/Drain formed at the STI sides of the VSTB opposite to the gate sides made of the Schottky junctions placed remotely from the gate- to-VSTB interface (remote Schottky Source/Drains). The Source/Drain work functions (Schottky barrier heights) for n-channel VSTB-FET and p-channel VSTB-FET can be different or the same, if a simpler process integration desired. An interlayer dielectric 950 is deposited on the top of the inverter. The moderate to heavy doped layer or well 202 has n-type doping, if it is under the p- channel VSTB-FET, and separates the channel of the p-channel VSTB-FETs from the p-substrate or p-well and has p-type doping, if it is under the n-channei VSTB-FET, and separates the channel of the n-channel s VSTB-FETs from n-substrate or n-well. If desired, the inverter can be formed on SOI wafer with no needs for any p-type doped or n-type doped layers like 202.

[0140] In order to further increase the device density, a stackable architecture of the device placement is invented having a plurality of tiers where every tier has an integrated circuit of any function or/and some specific functions like SRAM, NAND Flash, and/or NOR Flash memory and the like. Fig. 26 illustrates a cross-sectional view of a stackable CMOS inverters architecture having, as a particular embodiment example, the u VSTB-FETs in the bottom crystalline substrate and the tiered uVSTB-FETs in a tier being isolated from the bottom by an isolation layer 950. The CMOS inverters comprise (i) two low or non-doped VSTBs 100 having the caps 101 at the VSTBs top both formed on the STI 300 or/and TDL 360 vertical walls and connected to the crystalline substrate 200 or to a quasi-substrate 122 made of the crystalline or/and polycrystalline layer as a tier isolated from the bottom tier and from a tier above shown ones by the inter-tier dielectric layer 950, (ii) a moderate to heavy doped layers or wells 202/204 and 203 separating the corresponding channels of transistors in the substrates accordingly, (iii) a common gate electrode having the gate work function metal / metal alloy layer 703 or their stacks and the common gate high conductive layer 800, and (iv) the remote Schottky Source/Drains formed in the STI or TDL sides of the VSTB opposite to the gate sides. The moderate to heavy doped layer or well 202 has n-type doping to separate the channel of the p-channel s VSTB-FETs from the p-substrate and has p-type doping to separate the channel of the n-channel s VSTB-FETs from n-substrate. A tier substrate is a moderate to heavily doped quasi-substrate deposited on the inter-tier isolation layer 950 having one VSTB 100 connected the p-doped layer 204 (or p-well) and another VSTB connected to the n-doped layer (or n-well) thus defining n-channel and p-channel of the u VSTB-FET. If desired, the quasi- substrate can be omitted resulting in the tier device designs similar to the SOI VSTB-FET architectures in a tier. If desired, silicon-on-insulator (SOI) wafers with a thick SOI layer in a range from lOnm to lOOOnm can be used instead of bulk semiconductor (silicon) wafers for all types of products with no change of the product masks and with no needs for any p-type doped or n-type doped layers 202, 203 and 204. STI or TDL thickness can be in a range from lOnm to 3000nm or so depending on product specifications and process capabilities. [0141] The layer numbers are mainly kept the same as for the basic VSTB-FET in the crystalline substrate in order to easily understand the structure even though they are made in the tier. If desired, the dual work function gate metal stacks, like shown in Fig. 25, can be used for the multi- tiers architectures in everv tier like those illustrated in Fig. 26. Thus a stackabie architecture having, as an example, a plurality of the cVSTB-FET devices and c VSTB-FET inverters or u VSTB-FET devices and u VSTB-FET inverters in the bottom crystalline substrate and the VSTB-FET devices and VSTB-FET inverters using both architectures of cVSTB-FET and / or uVSTB-FETs in a tier (tVSTB-FET) being isolated from the bottom by an isolation layer 950 where the tVSTB-FET has all the key functional vertical layers formed in the tier semiconductor (crystalline, polycrystalline, or amorphous) layer of the quasi -substrate 122 and / or in the TDL to form the VSTB Fins 100 are illustrated in Fig. 26. The quasi-substrate 122 ca be in-situ-doped during deposition or by ion implantation/anneal steps after the layer 122 deposition with one type of doping and then the doping layer 204 is doped after the trench is formed in the TDL by the opposite type of doping than the initial doping type of the layer 122, to compensate the initial doping and to set the opposite doping type. Forming such a dual-type doped quasi-substrate with corresponding contacts to those layers and connecting them to V_ss and V_dd correspondingly makes the tier tVSTB-FET inverter functions as the bulk CMOS inverter.

[0142] The VSTB layers are made of polycrystalline silicon or other semiconductors like Ge or III-V and the like and they are formed by using the spacer formation process module on the vertical walls of the TDL edges after the trench is formed in the TDL by a Lithography step and etching step. For a particular embodiment, the tVSTB-FET is formed by the following set of process integration steps: (i) the TDL or TDL and TDL cap deposition followed by a Lithography and trench etching steps, (ii) the VSTB is made of polycrystalline silicon or other semiconductors by using the spacer formation process module on the TDL's vertical walls, (iii) a doping layer 204 is formed by making a lithography step followed by the dopant atom ion implantation and anneal to activate the doping atoms in the layer 204; (iv) deposition of a dummy gate isolation layer made, for example, of TEOS Si02 or materials like this, followed by CMP for planarization followed by the dummy gate isolation cap formation by a recess of the layer followed by the cap material deposition and planarization step by CMP; (v) recess of the poly-Si VTSB top in a depth range from 2nm to 20nm foll owed by deposition of the VSTB cap material 101 made of a dielectric like A1203 or a stack of interfacial layer of Si02, ultra-thin SiN layer, and A1203 layer to reduce the density of the interfacial traps (D_i}) and to compensate for the native positive charge in SiN and negative charge in A1203 or a similar stack like this, followed by the planarization step by CMP; (vi) if the "Gate first" integration scheme is adopted then the standard process steps to form VSTB- FET follows. Note that steps (i ) and (v) can be done in the reverse order. If the "Gate last" integration scheme is adopted then the following steps, similar to the standard series of steps, are necessary: (a) a deposition of a interlayer dielectric or a stack on the top of the structure formed after (v) step is made; (b) the fonnation of the gate trench in the interlayer dielectric by the Lithography step followed by the poly-Si dummy gate formation by poly-Si deposition followed by the planarization; (c) 2DSA Litho step followed by the remote Schottky Source/Drain formation simil ar to the "Gate first" process, (d) selective rem oval of the dummy gate, selective etching of the dummy gate dielectric cap; (e) anisotropic etching of the dummy gate dielectric leaving at the gate trench bottom a dielectric layer 400; (f) fonnation of the Gate metal stack followed by CMP till the top of the interlayer dielectric layer. It is necessary to note that the TDL cap, VSTB cap, and the dummy gate isolation layer cap are to be made of dielectric materials mutually selectively etchable.

[0143] A tier substrate can be formed using two methods: 1. VSTB is formed by the spacer process on the TDL wall and 2. VSTB is formed on the STI wall formed in a very thick semiconductor quasi-substrate. The method 1 includes the following detailed steps: (i) after the bottom tier in the crystalline substrate is formed and planarized, a deposition of an inter-tier isolation layer 950 is done; (ii) deposition of the quasi-substrate made of a thin poly-crystalline material like poly-Si in thickness range from 3nm to 30nm or so, having a dopant type provided by the in-situ doping process during deposition where the in-situ doping helps deposit a more uniform in thickness layer with larger grain sizes; (iii) formation of a doping layer 204, being doped with the opposite type of doping than the quasi-substrate deposited initially, by doing a Lithography step and an ion implantation step followed by an anneal; (iv) the TDL or TDL and TDL cap layer stack deposition in a thickness range from lOnm to 300nm or more with optional TDL cap in a thickness range from 2nm to 20nm; (v) a Lithography step to open the gate trench areas and etching the TDL with etch stop at the quasi-substrate poly-Si layer; (vi) VSTB layers formation from a poly-Si or other semiconductors on the vertical wall of TDL in the gate area trench by a spacer formation process having the VSTB electrically and physically connected to the quasi-substrate; (vii) the set of processes to form the VSTB-FETs as described above. It should be noted that for a more controllable grain size growth a deposition temperature is typically low, so that an amorphous or nano-crystalline silicon layer is formed followed by a moderately high temperature anneal to grow a poly-crystalline morphology of the Si layer (poly-Si). In this case a moderate in-situ doping helps grow a larger grain size poly- Si layer which is beneficial for the carrier mobility in the quasi- substrate. The method 2, where VSTB is formed on the STI wall formed in a very thick semiconductor quasi-substrate, includes the following detailed steps: (i) after the bottom tier in the crystalline substrate is formed and planarized, an inter-tier isolation layer 950 is deposited; (ii) deposition of the thick poly-Si layer as a bi-layer on the top of the inter-tier dielectric 950 having the bottom layer portion in a thickness range from 3nm to 30nm being moderately to highly in-situ doped and the top layer portion in a thickness range from lOnm to 300nm which is an undoped layer or a moderate to lower doped layer for large grain size formation during a following anneal; (Hi) the STI formation in the quasi-substrate at the depth of about the low doped quasi-substrate layer; (iv) all the others steps similar to the VSTB-FET process integration scheme on the crystalline bulk substrate to form the tVSTB-FET including a VSTB formation step, the Gate, and the Source/Drain. It should be noted that the grain sizes in poly-crystallization process is typically limited by the film thickness so that the thicker the layer the larger the grain size is formed and the larger the earner mobility in VSTB-FET channel is expected. Thus for a controllable large grain size growth it is beneficial to use the method 2 to form the quasi-substrate. It is highly desirable to grow a crystalline semiconductor layer for a tier but by today there is no cost effective method to do it but if such a method would be found the device design concept described here can easily accommodate this method in to the tVSTB-FET device fabrication methods. The method 2 can be modified by having the thickness of the bottom layer portion (moderate to heavy doped one) of the quasi-substrate to be zero. In this case the integration scheme is similar to the SOI VSTB-FET formation process as described above.

[0144] An expert experienced in art can foresee many different types of integration methods of these basic devices and their basic modules (like the remote Schottky Source/Drain module, or a single or a dual work functions scheme for the gate metal stack module) to form a plurality of device types and device combinations.

[0145] A way to increase the device density is to place the Gate and Source/Drain in the same trench, at the expense of the high intrinsic parasitic Source Drain-to-Gate capacitance, which is to the contrary of the typical VSTB-FET designs where the Source/Drain are formed / placed on one side of the VSTB (Fin) and the Gate on the opposite side resulting in almost zero intrinsic Source/Drain-to-Gate parasitic capacitance. One might notice that this new device concept is very similar to the Tri-Gate MOSFET, which is true with respect to a rather large intrinsic parasitic capacitance, but the new VSTB-FET device having double isolated channels architecture called dVSTB-FET is significantly different from the Tri-Gate or double-gate Fin-type device design by having two isolated VSTBs (Fins) attached to / hold by their respective STL dielectric layers with the common gate so that the Fin thickness can be made with any practically doable aspect ratio and thickness with no penalty for the Fin mechanical stability, to the contrary of the Double Gate or Tri-Gate where the Fin mechanical stability brings the scaling limits for below the 14nm nodes.

[0146] The proposed dVSTB-FET device concept can be realized using both "Gate first" and "Gate last" methods of MOSFET fabrication as it is illustrated in Fig. 27 and Fig. 28 by showing 3D schematic views of the dVSTB-FETs. Described herein are novel vertical super-thin body (VSTB) field effect transistor (FET) structures having two channels (double channel) (dVSTB-FET). In an embodiment of the present invention, the dVSTB-FET is a semiconductor on bulk c-Si transistor. The dVSTB-FET is ideal for use in fully depleted VSTB transistor applications where the body electri cal connection to the wafer substrate is essential if some floating body effects are not beneficial for the Integrated Circuit functioning. If desired, it is possible to use a SOI wafer with a thick SOI to fabricate the dVSTB-FET to provide high radiation hardness or some other specific requirements like noise reduction through enhancing the substrate decoupling.

[0147] Fig. 27 and Fig. 29 to Fig. 31 illustrate the structure of the dVSTB-FET 001 fabricated using the "Gate first approach" when the source and the drain (Source/Drain) are formed after a gate formation is completed when a thermal budget needed for a Source/Drain dopant drive- in and an activation is acceptable for the formed gate. The transistor comprises two semiconducting VSTBs 100 formed in the bulk semiconductor substrate 200 having a VSTB cap 101 on the top and attached to a adjacent vertical wall of a dielectric body 300 having a dielectric STI cap 301 on the top surface, the gate 900 having the lower part placed between and adjacent to VSTB vertical walls and the upper part placed on the dielectric STI cap 301, a source 500 and a drain 600 formed on opposite sides of the gate between and adjacent to the VSTB vertical walls, a source diffusion region 502 and a drain diffusion region 602 and two channels being parts of the VSTBs, a first trench dielectric 400 separating the source 500, the drain 600 and the gate 900 from the substrate 200. A spacer 433 formed on walls of the upper part of the gate 900 separates the upper part of the gate from the source and the drain. The second trench dielectric 432 placed in the trench on the first trench dielectric 400 top isolates the Source and the Drain from other transistors and the trench dielectric 432 under the spacers 433 isolates the source and the drain from the gate. The VSTB part above the dielectri c layer 400 is low doped and the VSTB part below the top of the dielectric layer 400 (sub-Fin region) belongs to the moderate to high doped diffusion region 401 of the substrate 200 at the bottom of the trench. The upper parts of the gate and the source and the drain surrounded by an interiayer dielectric stack 102 formed on the top surface of the dielectric STI cap 301 and the second trench dielectric 432. The gate 900 consists of a gate dielectric stack (GDS) 700 and a gate electrode 706. In the embodiment of the present invention the half of the channel width W_g 2 is equal to the VSTB height minus the thickness ¾ of the gate-to-substrate isolation 400. This device design mitigates the 2D work function effects in the metal gate fabrication process if the work function layer is a stack and rather thick being more than 5nm.

[0148] Fig, 28, Fig. 29, Fig. 30 and Fig, 32 illustrate the dVSTB-FET 002 fabricated using the "Gate last approach" when the source and the drain are formed before the gate formation if a thermal budget needed for a Source/Drain dopant drive-in and an activation is not acceptable for the pre-formed gate. The transistor comprises two semiconducting VSTBs 100 formed from the bulk semiconductor substrate 200 having a VSTB cap 01 on the top and attached to a adjacent vertical wall of a dielectric body 300 having a dielectric STI cap 301 on the top surface, a gate 900 having the lower part placed between and adjacent to VSTB vertical walls and the upper part placed on the dielectric STI cap 301, a source 500 and a drain 600 formed on opposite sides of the gate between and adjacent to the VSTB vertical walls, a source diffusion region 502 and a drain diffusion region 602 and two channels being parts of the VSTBs, a spacer 433 separates the upper part of the gate 900 from the source and the drain, the part, of the first trench dielectric 400 under the spacers 433 isolates the source and the drain from the gate, other part of the first trench dielectric 400 separates the source 500, the drain 600 and the gate 900 from the substrate 200 and from other transistors. The upper part of the VSTB is low or no doped channel portion of VSTB and the lower part of the VSTB (sub-Fin region) constitute the moderate to high doped diffusion region 401 of the substrate 200 at the bottom of the trench to keep the bottom leakage path under control if desired. The upper parts of the gate and the source and the drain surrounded by the interiayer dielectric stack 102 formed on the top surface of the dielectric STI cap 301 and the first trench dielectric 400. The gate 900 consists of a gate dielectric stack (GDS) 700 and a gate electrode 706, In the embodiment of the present invention the half of the channel width W_g 2 is equal to the VSTB height minus the thickness T_gs of the gate-to-substrate isolation 400.

[0149] The VSTB 100 formed from a bulk semiconductor substrate 200 such but not limited to crystalline silicon, germanium, gallium arsenide substrates and the like or from a crystalline or polycrystalline semiconductor in an isolation stack for example such as semiconductor-on-isolator (SOI). The VSTB 100 can be formed from any well-known semiconductor material, semiconductor-on-semiconductor stack, or semiconductor material -on-isoiator, including but not limited to crystalline (c-Si) or polycrystalline silicon (poly-Si), germanium (Ge), silicon germanium (Si_xGe_v), gallium arsenide (GaAs), GaP, GaSb, InSb and other multi -components compounds. The VSTB 100 can be formed from any known material which can be reversibly altered from an insulating state to a conductive state by exploiting the field effect which provides near-surface conductivity changes by applying external electric potential controls. The VSTB 100 is ideally a single crystalline film when the best electrical performance of the dVSTB-FET is desired. For example, the VSTB 100 is a single crystalline film when the transistor is used in Integrated Circuits (IC) with a high density for high performance applications, such as microprocessors and systems- on-chip (SOCs). The VSTB 100, however, can be a polycrystalline film when the transistor is used in applications requiring less stringent performance, such as in liquid crystal displays. The dielectric body 300 insulates the VSTB 100 from other transistors and forms interface with the VSTB that provides a good electrostatic control of the gate voltage over the entire body between Source and Drain, The dielectric body 300 is named the STI but it can be any dielectric body in equivalent sense further on in the description. In an embodiment of the present invention, the VSTB 100 is a single crystalline silicon film and has thickness in a range from lOOnm to lnm and even less down to a mono-atomic layer thickness for materials with high Density-Of-State (DOS) like Graphene. For high radiation hardness applications the VSTB 100 can be easily made as a SOI- VSTB. Process flows of the dVSTB-FET fabrication are described in details below. Single or multiple dVSTB- FET devices can be fabricated in a single active area with VSTB isolation made by using the iso- plugs method or the VSTB cut-mask method.

[0150] Basic process modules for formation of the VSTB, the Source/Drain, and the Gate are the same as described in the prior-art inventions. Brief summary for these modules is outline below. The VSTB formation: (i) A standard STI process having a deposition of Si02-pad and Si3N4-hard mask layers with non standard ratio of Si02-pad to Si3N4-hard mask thicknesses having the Si02 pad layer being the same or thicker than SiN hard mask layer; (ii) After STI etch area is opened the STI etch mask has an edge on the wall of which the VSTB hard mask can be formed using the standard spacer formation technique by depositing the VSTB hard mask (becoming the VSTB cap 101 later in the process) layer made of, for example, amorphous A1203 or other materials like this, followed by the anisotropic etch; (iii) a STI trench formation by etching away c-Si not covered by the VSTB cap and the STI hard mask; (iv) an STI liner formation by a silicon thermal oxidation and STI filling-in by a dielectric layer like HDP-Si02 deposition followed by CMP; (v) an STI cap layer 301 formation by the standard process of the cap formation by HDP- Si02 recess etch, cap material deposition, followed by CMP; (vi) removal of the STI hard mask in the active area selectively to the STI-cap and VSTB cap, followed by the silicon anisotropic etching almost the same depth as the STI depth; (vii) formation of the locally doped areas at the bottom of the active areas by zero degree dopant ion implantation into the substrate having n-type of dopant for p-MDSFET and p-type of dopant for the n-MDSFET, followed by a dopant activation anneal, to increase the parasitic threshold voltage V_th between the two VSTB-FETs in the same active area, if desired, and to dope a sub-Fin area to improve the gate electrostatic control over the VSTB at its bottom; (viii) the gate trench dielectric layer deposition like TEOS or HDP-Si02 followed by CMP. Thus two VSTBs are formed in the active area. If desired, a cut mask can be applied after the VSTB-hard mask formation and removal the hard mask where VSTBs are not needed for a particular product layout design. The VSTB cap thickness (determining VSTB thickness) is determined by the final device VSTB thickness plus the silicon budget for the STI liner formation by oxidation, VSTB walls cleanings, and for the gate interfacial thermal oxide formation. The Source/Drain formation module (see Fig. 30) is as following: (i) After the Source Drain holes, adjacent to the VSTBs and two-dimensionally self-aligned (referred as "2DSA process") to the Gate and to the VSTB cap are formed by applying a Lithography step and etching, a selective epitaxy of the highly in-situ doped material 104 (n-type for n-transistor and p-type for p-transistor) on the VSTB walls in the S/D holes or poly-Si deposition of highly in-situ doped material 104 (n- type for n-transistor and p-type for p-transistor) or doping is done with using a litho for dopant II for Source/Drain doping (n-type for n-transistor and p-type for p-transistor), followed by fRTA to form the source diffusion region 502 and the drain diffusion region 602 in the VSTB; (ii) a deposition of the contact metal barrier layers 503 (not shown) and metal 500 followed by CMP till the CMP stop layer top of the ILD 102; (iii) Recess metal in Source/Drain holes/trenches and fill in the recess with the capping dielectric layer 505, followed by CMP. Gate formation (see Fig. 29): (i) Litho step for the Gate area opening followed by the gate dielectric formation having the interfacial dielectric formed by a VSTB silicon ultra-thin oxidation and deposition of a high-k gate dielectric; (ii) deposition of the gate metal work function stack in a single work function process for both n- MOSFET and p-MOSFET or in a dual work function process having suitable work functions metal stacks different for n-MOSFET and p-MOSFET by a standard dual-work function process; (iii) Gate area metal filling-in process by gate metal deposition followed by CMP; (iv) The gate area cap layer formation, if desired, by using the standard cap formation process. Fig. 31 and Fig. 32 illustrate the about mid- VSTB height cross-sectional views of the key layers of the dVSTB-FETs fabricated according to the gate fist and gate last integrations scheme, correspondingly. [0151] Details of the specific process flow steps to form the Gate and Source/Drain for the "Gate first" method of dVSTB-FET 001 fabrication are illustrated in Fig. 33 and Fig. 34A through Fig. 341. The dVSTB-FET device has such an advantage that it is easy to be integrated with any advanced gate stack. The first dummy gate dielectric in the trench is recessed leaving a layer 400 at the trench bottom having the thickness Tgs needed for appropriate reduction of the gate-to-substrate capacitance, process 20 IP, Fig. 34A. Next the gate dielectric 700 and the gate electrode 706 are formed and a pianarization is done by CMP, process 202P, Fig. 34B. The gate dielectric 700 can be a simple dielectric or a dielectric stack including an interfacial layer 701 (such as an ultra thin Si02) and a high-k layer 702 (such as HfD2, Zr02, Hf02 and/or Zr02 silicates, and alloys like those). The gate electrode 706 can be made of a poly-Si layer appropriately and accordingly heavily doped or as a stack consisting of the 1^st metal gate layer 703 as the barrier layer inhibiting any interaction between the high-k and the work-function materials, 2^nd layer 704 providing the correct work functions for a n-channel VSTB-FET (being above 4 eV to 4,75 eV) and a p-channel VSTB-FET (being below 5 eV to 4.25 eV), and a barrier layer 705 or stack for suppressing an interaction of the work function determining gate material with the gate electrode filling 800 (such as W, or WSi2, or MoSi2, or poly-Si, or the like), a litho step to fonn the gate and simultaneously open the trenches for Source/Drain followed by an anisotropic etching of the gate electrode 706 and the gate dielectric 700 above the STI cap 301 and in the trench between VSTBs forming the gate and gate extensions being metal-zero interconnects on the top of the STI cap 301, see Fig. 34C. The next step is deposition of the second dummy gate dielectric 432 (such as SiOC or the like) or dielectric stack to fill in the space between the gates opened after the gate formation process 203P followed by CMP, if desired, the gate electrode 706 can be protected from oxygen and moisture by forming a gate cap 707 by a gate materials recess filled in with the gate capping dielectric, process 204P, Fig. 34D. Then the dielectric 432 is recessed till the top of the VSTB cap 101, process 205P, Fig. 34E. The spacers 433 are formed on opened gate walls (see Fig. 34F), and followed by a deposition of the interlayer dielectric or the dielectric stack 102 and CMP to planarize (see Fig. 34G). A litho step to define Source/Drain areas 500 and 600 is performed followed by the anisotropic selective etching of the ELD 102 till the top of the STI cap 301 followed by the anisotropic selective etching of the second gate trench dielectric 432 to form Source/Drain holes separated from the gate by the dielectric layer 432 under the spacer 433, Fig. 34H. The spacer 433 and the STI cap 301 and the VSTB cap 101 are used as hard masks to self-align Source/Drain to the gate and the VSTB, Fig. 341 shows the final structure view of the dVSTB-FET after Source/Drain formation having the Source/Drain isolated from Source/Drain of other dVSTB-FETs or having some S or/and D common for neighboring transistors. The process flows of formation of the source 500 and the drain 600 are similar for both dVSTB-FET 001 and dVSTB-FET 002 and described above and formed Source Drain contacts can be seen along the middle of the gate cross-section in Fig. 341 where only the contact barrier layer 503 like TiN (or other metal nitrides or Metal-Silicide) and the Source/Drain filing-in metal layer 504 are observable, the selective epitaxy option for fabricating the raised Source/Drain 104 and the source diffusion region 502 and the drain diffusion region 602 are shown in Fig. 30-Fig. 32, If desired a protective layer (cap) can be formed on the top of the Source/Drain metal filling-in layer by the standard cap layer formation technique.

[0152] Details of the particular process flow to form the Gate and Source/Drain for the "Gate last" method of a dVSTB-FET 002 fabrication are illustrated in Fig. 35 and Fig. 36 A through Fig. 36H. After the VSTB structure formation as described above, the interiayer dielectric or dielectric stack 102 is deposited on the top of the structure followed by a litho step and anisotropic etching of the interiayer dielectric 102 to form the gate trench, Fig. 36 A, process 401P. The Source/Drain-to-Gate isolation spacer 433 such as SiN or SiOCN is formed on the gate trench walls, Fig. 36B, process 402P, followed by a deposition of the dummy gate material 801, such as poly-Si, and its planarization by CMP till the top of the ELD 102, Fig, 36C, process 403P. A litho step is made to define Source/Drain areas 500 and 600 followed by an anisotropic selective etching of the ILD 102 followed by an anisotropic selective etching of the first dummy gate dielectric 400 to form the Source/Drain holes in the trench, Fig. 36D, process 404P. The spacer 433 and the STI cap 301 and the VSTB cap 101 are used as hard masks to self-align Source/Drain areas to the gate and the VSTB. Source 500 and Drain 600 can be formed by a few different methods as described above, then the dummy gate 801 is removed and an anisotropic selective etching of the first dummy gate dielectric 400 is fulfilled and the process is stopped by etching time when the dielectric thickness is reaches the spec for T_gs, process 405P. The cross-section view of the structure along the gate trench is shown in Fig. 36E and a cross-section view across the gate is shown in Fig. 36F. Next, the gate dielectric 700 and the gate electrode 706 are deposited and followed by CMP till the top of the ILD 102, process 406P, Fig. 36G. A gate protective dielectric 802 is formed by the standard technique by recess of the metal gate stack, filling-in the recess by the cap layer 802 deposition followed by CMP, process 407P, Fig. 36H.

[0153] All the inventions about manipulation of the work functions of the Source/Drains and Gates for the n-channel and p-channel VSTB-FETs described above are applicable for dVSTB- FET device design and methods of their fabrications and are not revisited here again in the description of various aspects of the illustrative implementations using terms commonly employed by those skilled in the ait to convey the substance of their work to others skilled in the art and specific details are set forth above in order to provide a thorough understanding of the present invention.

Π. SEMICONDUCTOR LOGIC AND MEMORY STACKABLE DEVICES MADE OF VERTICAL SUPER-THIN BODY SEMICONDUCTOR ON DIELECTRIC WALL. AND METHODS OF THEIR FABRICATION

[0154] In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to other skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practice without specific details. In other instances, well- known features are omitted or simplified in order not to obscure the illustrative implementations.

[0155] The present invention is a set of novel devices such as Vertically Stackable NAND (VS-NAND) Flash Array of FEMT (VSTB-FEMT) and methods of fabrication therein. In the following description numerous specific details are set forth in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor process and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention. [0156] 3D devices based on the VSTB-FET provide a significant increase of the devices density and shrinkage of an area per an IC function. To further increase the IC device density per area, a new approach has emerged which is the fabrication of multi-layered ULSI where many Integrated Circuit Layers (ICL) or Tiers are fabricated on the top of each other in a stack on the top of the basic IC fabricated in the semiconductor crystalline substrate. Such ICL's transistors have typically less performance requirements and can be typically made of a poiycrystailine semiconductor material. A VSTB-FET used in the ICL can have the VSTB made of, for example, a poiycrystailine Si (poly-Si) or amorphous semiconductor. If a method of fabricating a crystalline VSTB would be found it can be easily integrated in forming a crystalline VSTB in a tier. Such ICL's can be a SRAM: array, a NOR or an NAND Flash array or a stack of the array tiers, One Time Programmable (OTP) cell arrays, and many other standard cells and functional electronic modules, macros, and blocks. [0157] For many particular embodiments of the present invention, the two basic building structures can be used in many ways for forming the stackable tiers of ICL's with VSTB layer 20 fabricated, for instance, from poly-Si on walls of the Thick Dielectric Layer (TDL) 360 which placed on an isolating inter-tier layer 950 or on a stack of isolating inter-tier layer 950 and a conductive quasi-substrate 122 which are illustrated in Fig. 37 and Fig. 38, correspondingly. The stackable ICL comprises a plurality of different device design using the basic building structures,

[0158] An example of the basic building structure on isolator (BBS-OI) in accordance with a preferable embodiment of the present invention is illustrated in Fig. 37. The BBS-OI comprises the semiconducting low doped VSTB 120 connected to a vertical wall of a dielectric body, such as the TDL 360 on one side, connected to a vertical wall of the dummy isolation 121 on the opposite side, placed on the top of the inter-tier isolation layer 950 by the bottom side of the VSTB, and covered with the VSTB cap 101 at the top side, having a TDL protective cap 304, and the gate trench dielectric 121 protective cap 451 placed on their tops having all protective caps mutually selectively etchabie to allow using the two dimensional self-alignment (2D-SA) process. [0159] A method of fabrication of the BBS-OI in this particular embodiment is as follows: (i) First a inter-tier (inter-ICL) isolation layer 950 is deposited on the top of the planarized surface with a thickness range of 5nm to lOOnm having an IC or ICL under this layer; (ii) the TDL 360 like TEOS or HDP-Si02 is deposited with the thickness range of 10nm to 500nni on top of layer 950, (iii) the TDL dielectric cap 304 is deposited with the thickness in a range of 2nm to 20nm on top of layer 360; (iv) a litho step is done for patterning the TDL and etching away the TDL dielectric cap 304 and the TDL down to the inter-layer isolation layer 950 to form the trench comprising the VSTB-to-be and the Dummy isolation areas; (v) a undoped or slightly doped poly-Si is deposited and etched back like in a spacer processing to create the poly-Si VSTB with the thickness range of 2 to 10 nm attached to vertical walls of the TDL; (vi) a gate area dielectric layer 121 like TEOS or HDP-Si02 is deposited followed by CMP for plananzation of the surface till the TDL dielectric cap 304 top; (vii) a poly-Si VSTB is selectively recessed by etching; (viii) a VSTB cap 101 is deposited with the thickness range of 2nm to lOnm and planarized by CMP; (ix) a gate area dielectric layer 121 is recessed by selective etching, (x) a protective dielectric cap 451 is deposited with the thickness range of 2nm to lOnm and planarized by CMP. [0160] An example of the Basic Building Structure with a Built-in quasi -Substrate (BBS-

BS) in accordance with a preferable embodiment of the present invention is illustrated in Fig. 38.

The BBS-BS comprises the semiconducting low doped VSTB 120 connected to a vertical wall of a dielectric body, such as the TDL 360, on one side and the Dummy isolation layer 121 on the opposite side, having the electrical connections to the heavily doped semiconductor layer 122 as the quasi-substrate at the bottom side and to the VSTB cap 01 at the top side, where the TDL 360 has the connections to the semiconductor layer 122 at the bottom side and to the TDL protective cap 304 on the top and the trench dielectric 121 has the connections to the VSTB layers 120 at the left and right sides and placed on the quasi-substrate 122 at the bottom side with its protective cap 451 at the top side, and the semiconductor layer 122 deposited on the top of the inter-tier isolation layer 950, where the layer 360 has, if desired, the etch stop layer 123 embedded in to the TDL 360 to control the Source and Drain depth when forming SD to the FET channels and the Bit-Lines.

[0161] A method of fabrication of the BBS-BS is as follows: (i) First a inter-tier (inter-layer) isolation layer 950 with a thickness range of 5nm to lOOnm is deposited on the top of the planarized surface having an IC or ICL under this layer; (ii) a moderately to highly in-situ accordingly doped poly-Si or c-Si layer 122 with a thickness range of lOnm to lOOnm is formed on top of layer 950; (iii) the TDL 360 like TEOS or HDP-Si02 with a total thickness range of lOnm to 500nm is deposited on top of layer 122, (iv) the etch stop layer 123 with a thickness range of 2nm to 20nm is deposited on top of the first poition of TDL 360 (optional), (v) the second poition of the TDL layer 360 deposited on the top of the layer 123, (vi) the TDL dielectric cap 304 with a thickness range of 2nm to 20nm is deposited on the top of layer 360; (vii) a litho step is done for patterning the TDL and forming an opening for etching away the TDL dielectric cap 304, the TDL 360 and the layer 123 down to the poly-Si or c-Si layer 122 of the quasi-substrate; (viii) VSTB layer formation by deposition of an undoped or slightly doped poly-Si l ayer in the opened trench and etched back as in the spacer formation process; (vi) a gate area dielectric layer 121 like TEOS, High Temperature Oxide (HTO), or HDP-Si02 is deposited, followed by CMP till the TDL dielectric cap 304 top; (ix) a selective poly-Si VSTB recess etching; (viii) a VSTB cap 101 deposition followed by a planarization by CMP; (ix) a selective gate area dielectric layer 121 recess etching; (x) a protective dielectric cap 451 deposition planarized by CMP.

[0162] It is beneficial to form the VSTB poly- Si having the large grain size. To achieve it one can anneal the poly-Si after deposition step described above. The other method of fabricating the large grain poly-Si is based on a well known correlation which is the thicker the poly-Si layer deposited the larger the grain sizes are formed. So if desired, for both BBS-OI and BBS-BS structures one can form the VTSB as follows: (i) after the trench opening and etching away of the TDL, the thick poly-Si layer is deposited in to the trench followed by a high temperature anneal to form a larger grain size poly-Si, followed by CMP for surface planarization, (ii) poly-Si recess etch followed by the VSTB spacer layer deposition 115 and etching away (spacer formation process); (iii) large grain poly-Si selective anisotropic etching away forming VTSB 120 under the VSTB cal 115; (iv) Trench area filling with the Dummy isolation layer deposition 121 followed by the CMP to planarize the surface; (v) Dummy layer recess followed by the Dummy layer cap material deposition and CMP for forming the cap layer 451. For the BBS-OI structure the Gate and the SD can be formed on the opposite sides of the VSTB in any order or in a single side using the two- dimensional self-aligned (2DSA) process. Also the Gate can be formed in the TDL 360 and SD in the Dummy layer 121 or the opposite way. For the BBS-BS structure it is beneficial to form the Gate in the Dummy Isolation 121 whereas the SD can be beneficial to fonn on the opposite side of the VSTB in the TDL 360 using the 2DSA process. When the Gate trench is formed by etching the Dummy isolation 121 it is beneficial to leave a portion of the Dummy isolation layer of a certain thickness in a range from 5nm to 30nm at the bottom to form the Gate with a small Gate-to-quasi- substrate capacitance, A specialist experienced in the art can think of many schemes for devices design using these two basic building structures: BBS-OI and BBS-BS and many their modifications. [0163] A novel, stackable in tiers, vertical super-thin body (tVSTB) field effect transistor (tVSTB-FET) or, if desired, field effect memory transistor (FEMT) structure (tVSTB-FEMT) having the tVSTB 120 made of poly-Si in the preferable embodiment or any other semiconductor crystalline, polycrystalline, or amorphous material formed by a spacer formation process at the edges of a trench in a thick dielectric layer 360 (TDL) placed on the top of an inter-stack (inter-tier) isolation layer 950 or, if desired, a conductive layer 950 (conductive stack) and methods of fabrication therein are invented and a particular NA D Flash design embodiment is illustrated in Fig. 39, A tVSTB-FET is formed if the gate dielectric 705 is just a standard gate dielectric like amorphous silicon dioxide (a-Si02) or a stack of the interfacial layer a-Si02 and a high-k gate dielectric like Hf02. A tVSTB-FEMT based NAND or NOR Flash array is formed if the gate dielectric 705 is a memory stack comprising the standard memory structures like SONOS, FG- structure, or a ferroelectric having the typical known ranges of the dielectric and FG layer thicknesses. It is easy to think of a simple set of steps to deposit SONOS like memory stack. FG~ based VSTB-FEMT can be formed by a simple process modification of fabricating tVSTB-FEMT using on the BBS-OI. After the VSTB formation by any version of processes described above, the gate isolation layer is formed by the poly-Si thermal oxidation or a-Si02 deposition by any known methods followed by the second thin poly-Si layer deposition in to the gate trench and etched back like in spacer formation process forming a FG layer along the Bit-Line (BL). Then the inter-gate isolation layer is formed by the FG partial oxidation or by the deposition of a-Si02 or any dielectric stack made of a-Si02, SiN, A1203 and the like followed by the Control gate material deposition like poly-Si heavily accordingly doped followed by planarization step of CM³ ("gate electrode formation first" scheme). Next is a Litho step to open the iso-trench along the BL, etching the control gate, inter-gate isolation, and the FG followed by the iso-trench dielectric material deposition to isolate the control and floating gates. If desired, the gate dielectric is also removed totally or partially and Phosphor Silicate Glass (PSG) is deposited as the iso-trench dielectric material which forms the n-type doped layers of the virtual Sources between tVSTB-FEMT cells along the VSTB BL to reduce the parasitic resistance. After forming the iso-trenches, an interlayer isolation stack is deposited followed by the Litho step to make Word-Lines (WL) with fabrication contacting vias to the gate areas buried alone. If desired, an FG-based tVSTB-FEMT on the conductive quasi-substrate can be fabricated by a simple modification of the process flow describe above. If desired, an inverse integration scheme can be used ("gate isolation formation first" scheme) in which after the memory stack formation is done, the trench can be filled with a WL isolation dielectric layer followed by CMP so that the WLs are formed by forming the inter-layer dielectric stack followed by making the Litho the with mask like long WL strips followed by- etching the inter-layer dielectric stack with further etching the WL isolation layer in trenches followed by the WL- conductive layer deposition and CMP. The last process resembles the known "dual -damascene" process where instead of the vias the memory cell gate holes (or small trenches) are formed to deposit the gate electrode stack in there and the WL itself is nothing but compact metal-zero interconnect.

[0164] A novel stackable in tiers vertical super-thin body (tVSTB) field effect transistor (tVSTB-FET) or, if desired, field effect memory transistor (FEMT) structure (tVSTB-FEMT) having the tVSTB 120 made of poly-Si in the preferable embodiment or any other semiconductor crystalline, polycrystalline, or amorphous material formed by a spacer formation process at the edge walls of a trench in a thick dielectric layer 360 (TDL) placed on the top of an inter-stack (inter-tier) isolation layer 950 or, if desired, on a conductive layer 950 (conductive stack) isolated in this instance from the bottom tier by the isolation layer 951 and methods of fabrication therein are invented and a particular NAND Flash design embodiment is illustrated in Fig. 40, Fig. 41 A, and Fig. 41B. A tVSTB-FET is formed if the gate dielectric 705 is just a standard gate dielectric like amorphous silicon dioxide (a- Si 02) or a stack of the interfacial layer a-Si02 and a high-k gate dielectric like Hf02. A tVSTB-FEMT based NAND or NOR Flash array is formed if the gate dielectric 705 is a memory stack comprising the standard memory staictures like SONOS, FG- structure, or a ferroelectric layer having the typical known ranges of the dielectric thicknesses and a thin FG layer. A plurality of tiers having functional logi c or analog IC or memory IC like Flash or SRAM in a tier stacked one on the top of another is invented. The TDL thickness 360 can be varied in a range from lOnm to 500nm depending on a particular specification for an IC made in the tier. The inter-tier conductive layer can be fabricated from a moderately to heavily doped poly- crystalline Si in a thickness range from lOnm to lOOnm or a stack made of metal layer, metal nitride, or metal silicide layer made of metal W, Hf, Ti, Ta, Zr, and other metal having a low diffusivity in the poly-Si layer with thicknesses in a range from 3nm to 30nm sandwiched between of the poly-Si layers having if desired a barrier layer like WN, TiN, TaN and the like with thicknesses in a range from Inm to lOnm to prevent the metal contaminations from tlie metal and silicides in to the TDL and to the VSTB formed on the top. Using the inter-tier conductive layer can dramatically reduce the floating body effects in VSTB-FET and VSTB-FEMT, if desired, whereas using the inter-tier dielectric layer can improve the device decoupling in an IC tier, if the decoupling effects are needed to be enhanced for a particular product. In the following description numerous specific details are set forth in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor process and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present inventions. Note that in Fig. 40 the 1^st NAND Flash array tier (001) in formed in c-Si substrate but a specialist experienced in the art can place there SenseAmp's and other memory periphery IC for enhancing functions of the top Flash array tiers or any other arbitrary IC. Both "gate isolation formation first" scheme and "gate electrode formation first" scheme can be chosen, whichever is desired for particular application and process capabilities.

[0165] In an embodiment of the present invention illustrated in Fig. 40, Fig. 41 A, and Fig. 41 B, tlie 3D NAND Flash memory stack made of a plurality of the Flash-array layers as tiers having the l^s! Flash array layer fabricated in the bulk semiconductor c-Si 200 as the VSTB-FEMT based NAND Flash array with horizontal bit-lines made of the c-Si VSTB 100 and the integrated Word-Lines (WL) made of conductive stack 912 formed on the top of tlie work-function stack 860 and isolated by the isolation layer 951 from the following Flash array tiers (one or more tiers) fabricated on the isolation layers 950 having Integrated Circuit Layers or tVSTB-FEMT based NAND Flash array being vertically stacked, where the tVSTB-FEMT is fabricated using a poly-Si VSTB 120 on TDL 360 wails. The poly-Si tVSTB 120 as well as the vertical memory stack layers 705 are fabricated in a trench made in the TDL 360 by a spacer like process and the integrated WLs made of conductive stacks 912 placed on the top of a work-function stack 860. If desired, a NAND Flash can be fabricated using tlie tVSTB-FEMT device having a stack 705 formed as the gate memory stack. NAM) Fl ash non-volatile memory (NVM) stack 705 can be made of a trap-based media such as SONOS (consisting of poly-Si/Si02/Si3N4/Si02/Si), SNONOS (consisting of oly- Si/Si3N4/Si02/Si3N4/Si02/Si), or TANGS (consisting of TaN/A1203/Si3N4/SiQ2/Si) and the like, a ferroelectric polarization based media such as SrTi02 and the like, and the floating gate based NVM cell, if desired. A layout view of the stackable architecture with vertically drawn Bit- Lines (BL) 120 and horizontally drawn Word-Lines (WL) 912 in a plurality of the Flash-array tiers stacked vertically is illustrated in Fig. 41A with the BLs 120 going in one direction and WLs 912 going in the orthogonal direction. Repeating this array of cells to the left and to the right and to the top and to the bottom direction a NAND Flash array architecture can be formed with 2 bits per a super-cell, having 2 tVSTB-based BL in a single trench. Some details of fabrication of "the gate electrode formation last" scheme is shown in Fig. 41B where the dielectric layer 860 is deposited in between on the top of the memoiy stack 705 and only then the gate electrode trenches are opened and filled with the electrode material together with the WL trenches as the metal-zero interconnects.

[0166] It should be noted that quite a range of varieties of the NVM gate dielectric stacks are developed these days for different applications and to satisfy some integration requirements. Integration of such stacks into VSTB device concepts and fabrication methods is not sometimes straightforward. For example, if TANOS stack is taken as the basic NVM stack then when etching the gate dummy filled dielectric such as Si 02 in order to form the gate electrode there is no etching problem at all because TaN is a very good protection layer and TANOS stack is not damaged by Si02 etching. To the contrary if SONOS stack is used then for the same step of the dummy Si 02 etch there is no any etch stop layer and SONOS-stack oxide can be damaged and thickness is affected with less controllability. If desired, to avoid such an issue and provide a robust process integration scheme, it is advisable to use SNONOS stack with a very thin SiN layer (typically deposited at a higher temperature to reduce the trap concentration by, for example, ALD) or A1203 layer can be formed (constituting SAONOS memoiy stack) on the top of the SONOS-stack top oxide layer. Another example is that. It is commonly accepted that the gate electrode is made of the heavily doped n+-type poly-Si and the main improvement of the erase mode performance is achieved by engineering the barrier height and dielectric constant of the top dielectric layer. However, a stack of any conductive material with a specified work function such as TiN, TaN, TiAIN, and the like can be used as the gate material covered with poly-Si on the top of the NVM gate electrode stack. An optimal work function is actually the mid-gap work function which allows improving both the program and the erase operation and increase the retention time. Heavily p+- doped poly-Si is an extreme case of strong improving the erase mode if the program mode has enough margins and vice versa in using n+-doped poly-Si gate if the erase mode is robust and write mode needs to be improved. Resistance reduction requirements have resulted in usage a more elaborated gate electrode stacks such as a policide stack (poly-Si-WN-W) and the like, A specialist skilled in the art can use many modification of the basic structure to make it more manufacturable with no changing the essence of the invention. The optimal VSTB height of the Flash array does not have to be very high. To the contrary it is advised to make the VSTB height as small as possible ultimately trending to a nano-wire size because there is no need in a high read cun-ent. To the contrary, to reduce the power consumption, a requirement of having a smaller read current is needed. This is especially important for LP / IILP applications. The universality and flexibility of the tVSTB-FET device concept is so strong that if desired a PCM-based cell VM or NVM cell based on a Spin-Transfer Torque Magnetic RAM (STT-MRAM) memory element can be easily integrated in the same tier just above the VSTB-FET based IC for cell selection and addressing. PCM-based cell NVM and STT-MRAM cell need a high current for programming and so the higher aspect ratio of VSTB-FET is needed and easy to fabricate having flexibility of making the right current for different cell concept. If desired, plural variety of One Time Program (OTP) NVM cells and arrays based on them can be fabricated using, for example, some known phenomena of changing the poly-Si VSTB conductivity by pulsing a high current, a high voltage, and MUX (Metal Induced Lateral Crystallization) or a controlled gate dielectric breakdown phenomenon. OTP cross-point or RAM architectures of NVM can be design and fabricated using the VSTB as the basic constructing element and exploiting the e-fuse or anti-fuse types of the programming mechanisms like, for example, an e-fuse mechanism of an electromigration phenomenon in silicides fabricated by a partial nickel silicidation of VSTB (see C. Kothandaraman in Reference list for a planar OTP ceil operation mechanism).

[0167] A process integration flow for fabricating the NAM) Flash Stack with highly doped poly-Si Word-Lines and Source/Drains as a particular embodiment of the invention is illustrated in Fig. 42, Fig. 43, Fig. 44 and Fig. 45. The Flash-array tier with the poly-Si tVSTB 120 can be used not only on the top of the first Flash-array tier made of c-Si but as a single Flash-array tier or a plurality of the Flash-array tiers (like 2, 4, 8, 16, and so on) on the top of any functional ULSI modules, blocks, cells, or macros, if desired, having a planar isolation layer 950 deposited under the bottom of any Flash-array tier. A process integration flow of poly-Si tVSTB Bit-Lines and a memory stack of the NA D Flash Stack layer is as follows (Fig. 42). Process 101P: an isolation layer 950, for example LPCVD SiON, is deposited on the top of the first Flash-array tier or any functional area of a product followed by deposition of lOnm -500nm TEOS Si02 as the TDL 360 and deposition of PECVD Si3N4 as a protective dielectric layer 304, 102P: Lithography is performed to open a trench area for the two BLs (strings) followed by anisotropic etching the layers 304 and 360 and the photoresist removal, 103P: Deposition of a poly-Si layer and etching back to form a poly-Si VSTB 120 as the spacer on the trench wall followed by recessing the layer 950 at the trench bottom by lOnm to 25nm (the layer 304 and the poly-Si spacers 120 served as a etch hard mask) and filling in the trench by a TEOS Si()2 deposition followed by a planarization step by the CMP (Chemical Mechanical Polishing) till the top of the protective layer 304 to form the dummy layer 850, where the final poly-Si spacer thickness being tVSTB thickness has to be in the range from 4nm to 12nm and if desired, the tVSTB can be made using any semiconductor material like poly-Ge, crystalline or polycrystalline Graphene or stack like BGB (BN-Graphene-BN, where BN is the Boron Nitride), and others, even some amorphous semiconductors can be used; 104P: the tVSTB cap 115 having 5nm to 30nm height is formed by the recess of the poly-Si spacer made by selective etch of poly-Si followed by an A1203 deposition or the like dielectric material and planarization by CMP till the top of the layer 304; 105P: etch-back (removal) of the dummy layer 850 from the trench; 106P; Formation of the memory dielectric stack 705 by using spacer formation processes for all memory stack layers. The initial thickness of the layer 304 has to be optimized to have its final thickness in a range from lnm to lOnm. It should be noted here that the typical total physical thickness of the FG-cell stack or SONOS stack is about 20nm and cannot be scaled down and fabricated thinner if the retention time above 10 years is the spec bringing the physical limit for the scaling of the memory stack thickness. To mitigate the 2D effects in the gate electric field distribution in the memory stack and to reduce the non-uniformity of the after Program and Erase charge distributions along the tVSTB height, the gate vertical placement has to be at least by the memory stack thickness deeper (size "a" in Fig. 42) than the tVSTB bottom and by about the same thickness higher than the top of the tVSTB (size "b" in Fig. 42), By making these control gate device sizes and placement with respect to the location of the tVSTB an almost uniform charge distribution is achieved providing the robust Program and Erase states with no high leakage paths in the channel. This is an unique advantage of the tVSTB-FEMT structure if compared to the Tri-Gate FinFET type of structure if it to be used as the NVM cell where a lot of 2D effects at the bottom of the Fin and at the Fin ti occurs and proven to be scaling stoppers together with the more than 2x larger cell size due to placing memory stack around the Fin (on both Fin sides and on the Fin top) having the 2()nm minimal memory stack physical thickness limit which is getting much larger than achievable Tri-Gate channel (BL) pitch and World Line pitch. [0168] Schematics of a Word-Line (WL) formation sequence of the process integration is shown in Fig. 43. Process 107P: Deposition of a WL stack 912 being, for example, a highly doped p+-poly-Si (or n+-poly-Si, depending on Program and Erase state margin as discussed above) or any material stack providing the right Work function of the layer placed on the top of the memory stack and low resistance layer place on the top followed by CMP to pianarize. Process 108P: Lithography step to form the WLs followed by the etching the WL material in between of the WLs and the photoresist removal (a layout view is shown in Fig. 43 and a cross-sectional view along 44- 44 line is shown in Fig. 44 after the photoresist removal). If FG Flash cell is adopted an additional etch process is needed to cut FG poly-Si between the cells along the Bit-Lines. The FG cutting can be made in self-aligned fashion with the WLs by a proper choice of thin etch stop layers on the top of the VSTB gate dielectric and under the control gate. Process 109P: deposition of an LP-CVD or HDP-CVD Si02 layer to form isolation 970 between the WLs followed by CMP till the top of the WL. Process HOP; PECVD Si3N4 deposition as the protective dielectric layer 370. In the integration flow described the dielectric layer 970 is deposited on the top and in between of the poly-Si or metal conductor. In the latter, such a scheme has a potential issue of poly-Si strings growth catalyzed by the metal from Si-carrying precursor used for Si02 deposition. To mitigate or eliminate this issue one can deposit a very thin SiN adhesive layer on the metal followed by the Si02 deposition. Such a SiN layer can also protect the metal from oxidation during Si02 deposition and resistivity increase. A thin metal nitride barrier layer can be also deposited on the top of the metal gate before the Si()2 deposition. If desired, a "gate isolation formation scheme" can be adopted where the dummy oxide 850 can be covered with the interiayer dielectric and then both layer removed with a Litho step by opening the holes for the gate metal formation and trenches in the interiayer for the WL formation as metal-0 interconnect. Then the metal gate stack deposition follows by a CMP step to pianarize the surface which is a kind of dual damascene process. The last process integration flow might be more costly with respect to the first one, providing a very similar cell density.

[0169] Bit-Line Source Drain (SD) formation process steps are schematically shown in Fig. 45. Process 11 IP: Lithography step to open SD holes aligned to the Word-Lines (WL) followed by the anisotropic etching of the layers 370, 970 and 304 and the photoresist removal. The isolation spacers 116 formation between the SD holes and the WL made, for example, of a lower-k dielectric like LPCVD SiCN by deposition and anisotropic etch of isolation layer leaving the spacers 116 on the walls of the hole. The thickness of the spacers has to be optimized to reduce the parasitic capacitance and provide the low resistance electrical contact to the tVSTB 120. The spacer 116 isolation between the SD and the WL 912 is clearly seen to determine the parasitic capacitance as shown in the process step 11 IP in Fig. 45. Process 1 12P: Anisotropic etch of the TDL 360 till the top of the layer 950 to open the poly-Si VSTB vertical surface. 113P: Deposition of highly n+~ doped poly-Si followed by a CMP step of the poly-Si layer continuing making CMP step for the layer 370 till the top of poly-Si WLs 912 followed by a flash RTA to drive-in the doping into the poly-Si VSTB 120 to form the SD, 114P: Deposition of TEOS Si()2 to form a protective isolation layer 951. A cross-sectional view right after the spacer isolation 116 formation is illustrated in Fig. 46 along the line 46-46 through the SD's and St) contacts of the stackable Flash-array tier layers with poly-Si VSTB shown in the process step 1 IP in Fig. 45. [0170] If desired, instead of fabrication of the stackable NAND Flash tiers made as a stack of a plurality of such tVSTB-FEMT's, this structure can be fabricated as a standalone MOSFET or / and MOSFEMT using tVSTB-FET made of a poly-Si tVSTB 120 embedded in to the TDL 360 as shown in Fig. 40 having the Source and Drain formed in the TDL 360 being tightly 2D-self-aligned to the tVSTB cap 115 to provide an electrical contact with the tVSTB 120. These devices can be used for fabricating NOR-Flash array, SRAM array or stackable arrays of these types of memory in plurality of the tiers on the top of each other or, for example, an eDRAM array in a single TDL having them placed on the top of any functional IC made in c-Si substrate or in a previous ICL.

[0171] Plurality of the isolated tiers described above are not vertically aligned which brings the issue of the through-tier vias alignment and spending extra area for the alignment margins, A vertically integrated self-aligned multi-tiers NAM) Flash array, using a Single Gate VSTB-FEMT cell, having two VSTB 120 strips as the Horizontal Bit-Lines (BLs) in a tier formed from a semiconductor layer like poly-Si per one Horizontal BL having the Vertical Word-Lines (WL) 860 connected to the periphery IC through the via / contact 955 above the top tier is invented and a cross-sectional view of it is illustrated in Fig. 47. In this particular embodiment the Flash multi-tiers stack is placed on the top of some IC formed using the crystalline substrate which is marked by- number 001 and it is separated from the IC 001 by the dielectric layer 954. The multi-tiers stack comprises the bottom isolation layer 954 and repeating stack of the TDL's 360 and inter-tier isolation layers 950 having horizontal VSTB strips 120 of the BLs attached to the TDL 360 walls on one side and to the memory stack 705 on the opposite sides and isolated by the inter-tier isolation layers 950 on the top and on the bottom sides of the VSTB. The vertical WL 860 is formed on the top of the memory stack 705 and the WL is common for all the BLs in a particular trench filled with the gate electrode material or a gate electrode material stack 860. The gate electrode should have a certain work function to optimize the Program/Erase/Disturb margins which depend on the performance of the memory stack. If the Program operation provides a large enough \½_. shift which is typically correlated with low V shift by Erase operation then a low work function gate electrode is preferable and vice versa. It is important to note that the SONOS- and FG- based memory stacks are of the thickness about 20nm (actually in a range from 16nm to 24nm) and almost at the end of the scaling down due to 10 years retention requirement. Having such a thick gate dielectric memory stack results in strong 2D effects of the non-uniform electric field distribution across the gate memory stack in the Program / Erase / Disturb operational conditions because the VSTB height, VSTB-FEMT cell channel length, and the memory stack thickness are of comparable sizes. This non-uniform electric field distribution across the gate memory stack results in a non-uniform trapped charge distribution providing some leaky paths where the Vth shift is not the same as in the main portion of the channel. Another effect is that the Vui shift distributions in BL from the bottom to the top due to varying the horizontal BL body thicknesses of the Double Gate FEMT (see Fig, 13 of Prior Art and the discussion therein) make it very difficult to find the optimal read voltage for the entire vertical Word-Line. These effects have become the scaling limiting factors and have to be resolved. In the invention proposed these effects are mitigated or solved in a very comprehensive way. 2D effects in the very bottom tier are mitigated by placing the memory and gate electrode stacks deeper in to the isolation layer 954 by an appropriate distance indicated by "c" in Fig. 47 as the distance between the short-dashed lines being about 30% portion of the total memory stack thickness. The vertical V«, shift distribution due to the BL body thickness variation is reduced in the device invented due to feature of the processing of VSTB BL by using isotropic lateral etching of the TDL 360 when forming niches where the VSTB BLs are going to be formed. 2D effects in all other tiers are mitigated by choosing an appropriate optimal thickness of the inter- tier isolation layer 950 thickness to be about the same or by 30% less than the memory stack thickness. The key features of the VSTB-FEMT cell are that it is the Single Gate device with the Super Thin Vertical Body (VSTB) BL to the contrary of ail known 3D Flash ceils that belong of Double Gate or Gate-All-Around architectures with rather thick BL body. These two key features provide a much less area needed for a Flash cell, more uniform V^ distributions after Program / Erase, and better retention time distribution. Depending on the performance of the basic fabricati on modules like Litho alignment anisotropy and selectivity in etching multi-layers stack of different materials a number of tiers doable with an acceptable yield can be chosen from 2 or 4 to 8 or 16 or even more when the leaning cycle in a mass production allow to achieve more precision in fabrication. [0172] Principle key steps for fabricating the vertically integrated self-aligned multi-tiers NAND Flash array, using the Single Gate VSTB-FEMT ceil, are illustrated in Fig. 48 to Fig. 54. The control gate electrode formation first or the gate isolation formation first schemes can be used. Below the control gate electrode formation first integration scheme is explained in details. The total integration scheme is as follows, (i) Process 120P, Fig. 48: Formation of the total stack by sequence of deposition steps of layer 360 and 950 in turn on the top of the bottom isolation layer 954 which can be made of the same material as layers 950; (ii) Process 12 IP, Fig. 49: Litho step to open a long Bit-Lines (EL) trench strip followed by anisotropic etching the total stack with switching selectivity for different materials with continuation of a time control etch of a shallow trench in the layer 954; (iii) Process 122P, Fig. 50: Selective isotropic lateral etch of layers 360; (iv) Process 123P, Fig. 51: Deposition of a poly-Si layer with etching back like in the spacer formation process, the thickness of the poly-Si (or amorphous Si as "a-Si") layer deposited and the thermal budget for anneal are subjects of optimization to achieve as large as possible poly-Si grain sizes comparable with the VSTB-FEMT cell channel length; (v) Process 124P, Fig. 52: Deposition of the memory stack. It is obvious how to deposit SONOS type of stack, but in case of FG-cell the steps sequence includes: the first one is to form the gate dielectric from a-Si02 by a thermal oxidation or a high quality a- Si02 deposition or by first forming a thin interfacial oxide by thermal oxidation followed by the high quality oxide deposition by using for example, an HTO-process (High Temperature Oxide), then a thin poly-Si or a-Si with no need to form grains size is deposited and etched back like in the spacer formation process followed by the inter-gate dielectric formation by basically a high quality a-Si02 deposition; (vi) Process 125P, Fig. 53: Gate electrode formation step by deposition of a poly- Si layer appropriately heavily doped to provide the optimal work function followed by CMP. The BLs location with respect to the Word Line (WL) location is shown on a layout view in Fig. 54, The vertical WL comes up to the surface through vias 955 and the interconnections are configured accordingly by using metal interconnect capability for the addressing periphery of the WL. If "the gate isolation forrnation first" scheme is adopted then a thin protective layer is deposited on the top of the inter-gate isolation layer made for example of A1203 to provide the etching stop layer when etching the gate trench and forming the metal gate electrode later.

[0173] Tlie principle difference of "gate electrode formation last" (a) vs. "gate isolation formation last" (b) integration schemes is shown in the cross-sectional views in Fig. 55(a) and Fig. 55(b). The 2D electric field distribution in the isolation area between the cells along a Bit-Line (BL) is illustrated in Fig, 55(a) where the electric field induces the inversion layer in the VSTB-BL by the outer-fringing effect. The effect in general is capable of creating low enough parasitic resistance in between the cells so that the BL functions robustly. However, if the Litho capability does not allow to make the inter-cell distance small enough for such a robust operation a formation of the virtual Source/Drain 130 is necessary which can be done with local n-type doping of the VSTB areas between the ceils. This can be done by using "gate isolation formation last" scheme where after the gate material filled in and the structure is planarized the inter-gate electrode isolation needs to be formed. To do this a Litho step is applied and the trenches parallel to the Word-Lines are open and the gate electrode material is etched away from the inter-gate areas continued with etching away the memory stack with etch stop at the VSTB walls. Then a dielectric layer is deposited made of PSG with P concentration in a range from 0.1% to 3 % followed by an RTA to drive the P from the glass in to the VSTB and forming the virtual Source/Drain 130. In this structure, regardless of what the distance between the cells along a BL is, the parasitic resistance along the BL is guaranteed to be very small.

[0174] It might be beneficial to make the Vertical Word-Line (WL) connections to the periphery addressing and switching IC formed in the substrate tier 001. A particular invention for such architecture is shown by the cross-sectional views in Fig. 56 to Fig. 58. The device structure invented is very similar to the one discussed above referring to Fig, 47, The process flow features related to the formation of the interconnection to the very bottom tier 001 is shown in Fig. 57, Process 126P. In a simplistic way, a memory stack fomiation process is similar to the "spacer formation process" having the memory stack etched back after its deposition so that the bottom area of the trench is open at the bottom of the trench in about a middle of the layer 954 which is continued to be etched down to the top of 001 tier where some interconnections are pre-formed for making WL addressing and connecting to the high voltage sources (generators). Then as it is shown in Fig. 58, Process 127P, the control gate electrode conductive material is deposited and followed by a CMP to planarize the structure. A protective layer 957 is formed on the top (not shown in Fig. 58), see Fig, 56, as the final step, A specialist experienced in the art can think of many other ways of forming such devices which can not constitute a set of features for an invention.

III. VERTICAL GATE CMOS IS SEMICONDUCTOR DEVICES AND METHODS OF THEIR FABRICATION

[0175] In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to other skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practice without specific details. In other instances, well- known features are omitted or simplified in order not to obscure the illustrative implementations.

[0176] The present invention is a set of novel devices such as a CMOS IS made of a MOS- PD with a Vertical Gate (VG-MOS-PD) complemented with the pixel switching circuitry (PSC) transistors, marked as T_x, R_x, D_x, and S_x, fabricated as the standard planar MOSFET's or VSTB- FET's; and CMOS IS made of the VG-MOS-PD and Vertical Gates Charge Coupled Device (VG- CCD) structure for the charge transfer and methods of fabrication therein. In the following description numerous specific details are set forth in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor process and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention.

[0177] An example of the Basic Building Structure for Gate Based Devices (BBS-GBD) for the CMOS IS having a Vertical Gate MOS-PD and a Vertical Gate CCD in accordance with a preferable embodiment of the present invention is illustrated in Fig. 59. The BBS-GBD comprises a semiconductor substrate 200, and the semiconductor bar 450 being a part of the substrate and having a protective dielectric cap 451 and a VSTB cap 101 at the top and surrounded by a STI 300 having the STI dielectric cap 301 at the top and connected to the semiconductor substrate 200 at the bottom, and the VSTB cap 101 placed between the STI cap 301 and the protective cap 451 , The protective caps 451 and 301 can be made of different dielectric materials having high etching selectivity to the protective cap 101 and to each other. If desired and possible for certain process integration flows, the protective caps 451 and 301 can be made of the same dielectric material.

[01 8] A method of fabrication of the BBS-GBD is as follows: (i) depositing standard layers of a STI hard mask on the semiconductor substrate; (ii ) patterning the STI hard mask with a litho step; (iii) anisotropic etching the STI hard mask layers and a photoresist removal; (iv) forming the VSTB cap 101 in the standard spacer process on the STI hard mask edge walls; (vi) fabricating the STI 300; (iv) recessing the STI; (vii) filling in the recess with the STI cap 30 dielectric and a CM!³; (viii) removing the STI hard mask; (ix) filling in the recess with the protective cap 451 dielectric and a CMP. If needed, the STI hard mask can be used as the protective cap 451 and the steps (viii) and (ix) might be omitted.

[0179] The present invention is a Vertical Gate MOS-Diode (VG-MOS Diode) device having the vertical gate that is to the contrary of the typical well known horizontal gate MOS diodes. A cross-sectional view of the vertical gate VG-MOS Diode structure in accordance with a preferable embodiment of the present invention is illustrated in Fig. 60. The VG-MOS Diode comprises the semiconductor substrate 200 with the semiconductor bar 450 having the bar protective cap 451 at the top, the STI layer 300 having its cap 301, the gate electrode 087 made of heavily doped poly-Si or a metal layer (or stack of metal layers) providing the optimal work function having the gate protective cap 098 on the top being attached to the STI 300 and surrounded by the gate dielectric 086 along the bar 450 and substrate 200 sides, and the gate dielectric 086 formed between the gate electrode 087 and the semiconductor bar 450.

[0180] A method of fabrication of the VG-MOS Diode, using the BBS-GBD prefabricated as describe above, is as follows: (i) removal of the VSTB cap 101 of the BBS-GBD shown in Fig. 59; (ii) selective anisotropic etching of c-Si bar using the protective caps 301 and 451 as the hard masks to create a narrow trench; (iii) a thermal oxidation of c-Si to form a gate dielectric 086; (iv) deposition of a heavily p-doped or n-doped poly-Si followed by a CMP until reaching the top of the protective caps to form the thin gate 087 in the trench, having a preferred p-type doping for imaging applications, (v) poly-Si recess; (vi) fill in the recess with a dielectric 098 followed by a CMP until reaching the top of the protective caps 301 and 451 ; (vii) deposition of an interlayer dielectric 102 or a dielectric stack 102+103. Such a gate structure is of a rather high resistance, if a single contact is formed, and can be used if the resistance is acceptable, Experienced in the art engineers can use many methods of the contacts fabrication to the vertical gate MOS-Diode with the target to reduce the total resistance, for example, by using many gate contacts using a strapping architecture and so on.

[0181] The CMOS IS is designed in many known configurations which can be broken down in to two parts: Photo-Sensitive Device (PSD) and the Pixel Switching Circuitry (PSC). PSD is typically made of a Photo-Diode (PD) which consists of a buried n-doped layer in the p-substrate with one side of the PD going under the access transistor gate and being the Source of the planar access MOSFET (marked as T_x) so that when T_x is on two functions can be accomplished: a PD pre-charging or a PD accumulated charge reading, PSC is made of a few MOSFET' s and in this particular example PSC is made of 4 MOSFET' s: T_x (PD planar access MOSFET), D_x (Source follower), S_x (Select MOSFET), and R_x (Pre-charge MOSFET) and a planar Floating Diode (FD). But there are known PSCs with less or more than this number of the MOSFETs. This invention is not about the PSC configurations but about a replacement of the standard planar MOSFETs with VSTB-FETs which provides a much higher performance for an Image Sensor pixel. It is well known fact that the noise of the MOSFET is mainly determined by the interfaeiai trap density Da) under the gate and the lateral electric field depending on a channel doping. The D_¾ depends on a process integration features and the gate-channel interface quality. The channel doping is going up in a planar MOSFET when a CMOS IS is scaled down following so called Dennard's scaling law: the shorter the channel the higher the channel doping. Higher channel doping results in a higher channel lateral electric field resulting in higher leakage and noise. The higher channel doping results in an another negative effect due to a higher Random Dopant Fluctuations (RDF) related \½, variations and a higher channel electric field fluctuations and higher 1/f noise variability, related to RDF phenomenon. As a result, the V_th variability and the noise are becoming the limiters in getting a better IS performance with the scaling. The VSTB-FET has a key feature of having non doped channel which makes it the ideal device for analog circuit applications and in particular for PSC providing low variability and low noise. The less noise provides an increased dynamic range of the pixel signal. To take the advantages of the VSTB-FET analog performance, a CMOS IS can be designed in a simple way of using the VSTB-FETs for the PSC, for the ADC and the periphery IC, but keeping the planar PD design in place as a particular embodiment. [0182] A layout vi ew of an invention exemplary embodiment of a VSTB-FET-based CMOS IS pixel having two separate T_x access transistors being a circular VSTB-FET (one of them is marked by a dashed line rectangle A_t) and the planar PD 089 and the planar FD 083 is illustrated in Fig. 61 that comprises all the key elements of a pixel: two planar PDs 089, two circular VSTB-FET T_x where each of them has a Source 500 and both have a common Drain 600 connected to the FD 083, three VSTB-FET' s S_x, D_x, and R_x fabricated also as the circular VSTB-FET' s. Not shown in details are interconnects ν^, Y_i >, and V_Rx fabricated in Metal 2 level and interconnects Vs_¾ and V_out fabricated in Metal J level in orthogonal direction to the Metal 2 interconnect group to provide voltage pulsing to the pixel.

[0183] A detailed layout view of the circular VSTB-FET T_x in the outlined area Ai is illustrated in Fig. 62. The VSTB-FET has the key functional layers: the VTSB 100, the gate dielectric 700, the metal gate work function stack 703+704, the metal gate electrode 800, the Drain 600, and the STI isolation 300 with the STI cap 301. When T_x is on, the channel current can go through two paths being the top channel and the bottom channel marked by the curves with the arrows. If desired, one VSTB channel can be removed by using "cut" mask to remove the VSTB hard mask and etch away the VSTB 100 during the gate trench formation and use only the top or only the bottom channel which simplifies the transistor design a bit and reduces the VSTB-FET area. This approach can be applied also to other VSTB-FETs of a pixel. Specialists experienced in art can designed a plurality of the VSTB-FET structure versions for the PSC. As an example, a layout view of two VSTB-FET T_x fabricated in a single gate area with iso-trench 902 based isolation of the T_x transistors is illustrated in Fig. 63. If desired, the Sources 500 of T_x3 and T_x2 transistors can be filled in with a moderately to highly doped epitaxial c-Si which can be different than the Drains 600 doping level to reduce the junction leakage resulting in reduction of the PD dark current. Examples of placements and sizes of vias 350 are schematically shown in Fig. 61, Fig. 62 and Fig. 63.

[0184] Another set of embodiments of the invention can be made by using a VG-MOS-PD instead of a planar n-p-junction based PD. There are several ways to design the CMOS IS with the VG-MOS-PD such as: (i) the CMOS IS having VG-MOS-PD designed with planar MOSFETs for the PSC as shown in Fig. 64; (ii) the CMOS IS having VG-MOS-PD designed with the VSTB- FETs for the PSC as shown in Fig. 67; (iii) the CMOS IS having VG-MOS-PD designed with the VSTB-FET' s for the PSC having the electrical connection between the VG-MOS-PD channel and the FD by a CCD technique by fabricating the T_x transistors as VG-MOS Diodes in close proximity to the VG-MOS-PD channel as illustrated in Fig. 68. [0185] The planar PD, as it is outlined in the prior art section, has a significant performance drawback having a low total PD capacitance which limits the maximal integrated charge and the dynamic range of the CMOS IS. There are a lot of ideas patented how to increase the photodiode capacitance, like fabricating a vertical stack of plurality of n-doped areas constituting the common n-doped PD, at the expense of a more complex process integration. A MOS-structure which can be considered as the MOS-Diode shows inherently much higher capacitance per unit area due to using thin dielectric isolation instead of a thick SCR resulting from low doped layers of the PD n-p- junction on both sides. The MOS-Diode can work in a mode of a MOS-PD if a SCR under the gate is created by a short voltage pulse and a light irradiates the SCR. Unfortunately, the MOS-Diode being the MOS-PD in this context has a drawback when using any planar technology, because the conductive gate of the MOS-PD absorbs the light significantly, reducing the sensitivity at a low light intensity side. A solution of using a back side irradiation for the MOS-PD helps to improve the dynamic range but it brings its own process integration complications, also a blue light does not penetrate in c-Si deep enough to reach the MOS-PD which results in partial loosing the generated charge due to the charge diffusion mechanism. [0186] An idea to fabricate the PD as the vertical MOS-Diode with vertical gate buried along the PD area perimeter is suggested in this invention and named the VG-MOS-PD, A layout view of a CMOS IS pixel embodiment having the PSC made of planar MOSFET's and a photosensitive device being the VG-MOS-PD is illustrated in Fig. 64 where the right hand side gate portion of the transistor gate is partially removed to illustrate how the SCR channel of the VG- MOS-PD will be connected to the transistor channel. Also all cap layers and the interiayer dielectric stack shown in Fig. 60 are not shown here. The VG-MOS-PD comprises of the vertical gate electrode 087, the gate dielectric 086 and the band-gap engineered PD semiconductor body 450 having, if desired, a light absorption enhancer built in, for example, made of a SiGe layer embedded in to the c-Si substrate to increase a red light absorption effectiveness, where the gate dielectric and the gate electrode are fabricated between the STI 300 and the PD semiconductor body 450. The thickness of the light absorption enhancer made of c-SiGe depends on the Ge concentration and for the typical range of the Ge concentration from 10% to 50% the c-SiGe thickness can be in a range of lOOnm to lOnm and placed embedded deep in to the semiconductor body in a range from lOOnm to 500nm as a buried epitaxial layer which does not affect the green and blue light absorption but significantly enhances the red light absoiption efficiency and reduces its penetration depth in to the substrate thus reducing the red color coupling between pixels through the substrate. Some inevitable extended defects produced by SiGe layer formation step are of little effects on the dark current generated in depth of the PD semiconductor body but they can help for electron-hole pairs to recombine in the depth of the PD and also mitigates the red light coupling effect. To provide the correct functioning of the VG-MOS-PD an extra interconnection line is added VQ_PD where the Gate Voltage to the VG-MOS-PD is supplied to the vertical gates through contacts 350. Process fabrication features can be summarized by grouping the process integration in to 3 modules as follows. All the metal 1 and metal 2 interconnections (V_dcj, Vs_x and so on) are not shown accordingly in vertical and horizontal layout directions since this is not a part of invention and an expert experienced in the art can design them appropriately for a particular product,

[0187] The first module is the BBS-GBD structure formation process having such module process parameters that are targeted to achieve an optimal cap 101 width (see Fig. 59) in a range from 5nm to lOOnm. The module consists of the following steps: (i) deposition of an STI hard mask stack consisting for example of a thermal oxide pad (Si02) and LP-CVD SiN layer followed by a Litho step to open the STI area 300 followed by etching the STI hard mask stack; (ii) deposition of the VSTB hard mask dielectric material, for example, amorphous A1203 and the like, which has a good etch selectivity with respect to the STI hard mask material stack and c-Si or poly-Si; (iii) utilizing the "spacer fabrication process", removal the VSTB hard mask material anisotropically and selectively follows to form the VSTB hard mask at the edge of the STI hard mask becoming also the VSTB cap later in the process integration; (iv) anisotropic etching of c-Si in STI openings with depth in a range from 50nm to lOOOnm; (v) STI liner fabrication by thermal oxidation of STI c-Si walls followed by filling the STI trenches by a-Si02 such as HDP oxide, followed by planarization of the surface by CMP until reaching the top of SiN layer of the STI hard mask; (vi) if desired, etching HDP Si02 selectively for a recess formation in the STI area followed by deposition of STI protective cap 301 material, for example PECVD SiN or SiCON and the like, which has a good etch selectivity with respect to c-Si and the cap 101 material, followed by planarization step by CMP until reaching the top of SiN layer of the STI hard mask; (vii) removing the STI hard mask; (viii) filling in the recess with the protective cap 451 dielectric and a CMP. Having the basic structure with three different caps allows using a self-alignment fabrication method for forming the VG-MOS-PD gates as well as SD for VSTB-FETs. The best integration scheme is to make the same size of the VSTB cap 101 for fabricating VG-MOS-PD (see Fig. 60) and for the pixel and periphery VSTB-FETs being about 5nm to 15nm. If the gate trench 087 aspect ratio in a range from 10 to 50 is not achievable by a particular process capabilities due to the etch process performance, a wider trench needs to be made which needs a wider cap 101 width for the MOS-PDs vs. VSTB- FET caps. In this situation the cap 101 for the VG-MOS-PD and for the VSTB-FETs are formed of different sizes and have to be formed separately by applying extra Lithography steps. One, the most simple way of making different cap 101 widths, is forming it with the largest size and then trimming the spacer width by etching in locations where is has to be of a smaller width by applying a Lithography step to open those locations. This way a few different spacer 101 widths can be formed. The other way is a forming of a laminated (multi-layered composed, for example, of A1203, TaxSi02, SiN, or / and again A1203 and the like) staicture of the widest spacer and then by applying Lithography steps to open an appropriate location and etching the top most layer to have a smaller spacer width, followed by applying a second Litho step and etching the top second layer to form a third width of the spacer and so on to make as many spacer widths as needed. Another aspect of VG-MOS-PD performance improvement is related in an optimal fixed charge created by nature of the dielectric used for the bar cap 451. It is a very well know fact that a dielectric like SiN has typically a positive fixed charge whereas a dielectric like A1203 has typically a negative fixed charge. For a PD dark current reduction it is beneficial to have a net negative charge in the cap layer 451 since the negative charge pulls the surface potential in a direction reducing the dark current generation b the interfacial traps (by !¾) and repulses the electrons generated by the illumination and reduces the surface recombination of those electrons with the excess of holes also generated by the illumination thus reducing the quantum efficiency of the PD. Using a dielectric with the positive fixed charge can only reduce the generation but does not reduce the recombination. Another method to reduce the dark current generation is to use a screening layer as a thin higher p-type doped layer (up to lel8 cm-3) of the near interface region (lOnm to lOOnm) of the low doped bar right under the cap 451. The doping can be provided by a low energy ion implantation of Boron followed by annealing before the cap 45 formation or by exploiting a more controllable way of doping from a solid state. Thus a three-layered cap 451 structure is more beneficial having the cap layer made of first a BSG deposited, A1203 deposited, covered with SiN layer deposited on the top. Ever}' layer has its unique designation: BSG for Boron drive in to the screening layer in the semiconductor bar top sub-surface region, A1203 for bringing a negative charge to compensate for the harmful positive charge effect from SiN, and SiN having a selective etching capability as the cap with respect to other caps 301 and 101 (becoming the cap 098 in the VG-MOS-PD structures formed again, for example, from A1203). [0188] The second module is the vertical gate formation process for the VG-MOS-PD that consists of the following steps, similar to those to form a structure illustrated in Fig. 60: (i) Litho step to open the VSTB cap layer only around the PD areas; (ii) removal the VSTB 101 cap by its selective etch with respect to the STI protective cap 301 and the semiconductor bar cap 451 ; (iii) VSTB trench 087 formation by anisotropic etching of c-Si where the VSTB cap 101 was located; (iv) formation of the VG-MOS-PD gate dielectric by a thermal oxidation of c-Si wall in the trench or formation of any suitable gate dielectric stack in the trench along the VG-MOS-PD perimeter by combining a thermal oxidation and a deposition of any high quality dielectrics like Hf02 and the like; (v) deposition of a highly conductive gate electrode material having a certain as high as possible work function, for example, a heavily p+-doped poly-Si as in a simplest particular embodiment; (vi) planarization of the gate electrode to the caps surfaces by CMP; (vii) recess etching of the gate electrode with a depth in a range from 3nm to 30nm below the top surface level; (viii) dielectric deposition to fill in the recess with the VG-MOS-PD gate electrode dielectric protective cap 098 material (for example, A1203, HDP Si02 or SiON and the like) followed by planarization step by CMP until reaching the top caps surface level. Higher work function gate electrode material is desirable, for example, like p+-doped poly-Si to provide a built-in VG-MOS- PD depletion layer which is a photo-sensitive SCR. A high work function gate material brings a benefit of having a smaller VG-MOS-PD gate operational voltage. Also as small as possible doping concentration in the PD area is desirable.

[0189] The third module includes process steps to fabricate the planar PSC MOSFETs. The connection of the T_x channel to the VG-MOS-PD SCR is of a critical importance. To make the electrical connection of the VG-MOS-PD interfacial channel to the T_x channel the overlapping T_x gate over the MOS-PD is used as illustrated schematically in Fig. 65 with a cross-section view in Fig. 66. The overlap of the T_x gate with MOS-PD area is allowed to be rather significant being within the misalignment margins and is a subject of a engineering optimization. The module is a typical one for the planar MOSFET fabrication in the pixel and a periphery. The module consists of the following steps: (i) removal of the STI hard mask layers of SiN first and then pad Si02 by the typical wet etch with a typically slight recess of STI HDP and VSTB cap layers; (ii) a Litho step to open the PSC active areas of T_x transistors, FD, and D_x, R_x, and S_x active area followed by a p-type Ion Implantation to form the layer 077 for adjusting the of the PSC MOSFET s, having the misalignment margin for T_x transistor under the gate: (iii) a Litho step to open the VG-MOS-PD area followed by a p-type Ion Implantation into the top of the c-Si substrate to form another screening layer 078, if desirable, having the misalignment margin for the PD under the gate, to reduce the contribution of the interfaciai traps into a dark current from the top PD area surface then followed by RTA (optional) or / and performing a thermal oxidation to anneal the doping layers and to fabricate the gate dielectric by the thermal oxidation, (iv) deposition of poly-Si gate material or any other conductive material suitable for the gate, (v) a Litho step to form poly-Si gates by etching poly-Si away except for the MOSFET's gates 085: (vi) a Litho step to open n-channel MOSFETs in the pixel array area and in the periphery followed by the n-type LDD doping ion implantation layer 092 having noted that T_x transistors have only LDD at the Source electrode 092, which is assigned to be at PD side, having the misalignment margin as close as possible to the PD edge, (vii) formation of the Gate Spacer 550, followed by a Litho step to open the n-channel MOSFETs in the pixel array area and in the periphery and followed by heavy n-type doping of the Source and Drain areas 084 by Ion Implantation followed by RTA. The Drain electrode 084 of the T_x transistors is made with the common mask for fabricating FD 083 as well as Source-Drain layers 084 for all other n-type PSC MOSFETs. A standard coverage of the structure, having a relief shown in Fig. 66, with the Interlayer Dielectric (ILD) and a dielectric Etch Stop Layer (ESL) followed by a planarization step is the standard procedure of the planar technology. The contact making process in a pixel area is a typical process of the Planar MOSFET contacts fabrication process that is not discussed here for clarity purposes and the contacts are not shown in Fig. 65. All the key layers are indicated in Fig. 65 and Fig. 66: the VG-MOS-PD gate dielectric 086, the VG- MOS-PD gate 087, the isolating cap on the top of the vertical gate 098, the T_x gate dielectri c 152; the Τχ poly- Si gate 085, the low doped (like LDD n-type) T_x Source 092, T_x spacers 550, and the T_x Drain 084. If desired, one can argue, based on the semiconductor device physics, that the LDD doping layer 092 can be skipped in fabricating by making the n-type LDD Ion Implantation Litho mask edge at the midway of the gate 085 length provided having the cap layer 098 thickness just optimal for penetration of the T_x gate voltage to the VG-MOS-PD inversion layer which should enhance the dynamic range by reducing the minimal initial charge that can be collected by the VG- MOS-PD device. Note that the VSTB cap is also automatically formed along the STI perimeters of the FD and the common active area of S_x, D_x, and R_x MOSFET's being not shown in Fig. 64 for making the drawing clearer. If desired, this VSTB cap may stay there since it is just a part of the c~ Si active area or, if desired, it can be removed by using a cut mask to remove the VSTB hard mask in places where it is not necessarily. The light illumination coming to the VG-MOS-PD is marked by a lightning sign in Fig. 65 and Fig. 66.

[0190] A CMOS IS pixel embodiment having all PSC MOSFETs (T_xl, T^, D_x, S_x, and R_x) fabricated using VSTB-FETs, VG-MOS-PDs 088, and the planar FD 083 is invented and its layout view is illustrated in Fig, 67 where two VSTB-FET's T_x are fabricated in a single gate area and isolated from each other by iso-trench 902. The electrical interconnection between the VG-MOS- PD and the T_x channel is made by using the Source structure 500 which filled in with moderately to highly doped epitaxially grown c-Si or deposited poly- Si in the Source hole as in the VSTB-FET Source/Drain process without possibly using some extra, metallic conductor layers made of metal nitrides or metal silicides and pure metal like tungsten (W). Such an electrical interconnection has a good electrical connection to the Vertical channel inversion layer of the VG-MOS-PD. The Source Drain structures 600 have a highly doped poly- Si or highly doped epitaxial c-Si layer contacting the VSTB and some metal layers, if desired. To reduce the RDF related V_th variability and mismatch as well as to reduce the noise, VSTB-FETs are used which have a low or non-doped channel by definition. Plural embodiments of the principle structure design shown can be foreseen to choose from with the best performance after an experimental engineering optimization of different thinkable CMOS IS structures is accomplished. If desired, the FD 083 can be formed as a VG-MOS-Diode structure based on BBS-GBD generic structure as described above in Fig, 60 or a FD based on BBS-GBD staicture without the gate layer which would be BBS-Diode Based Device (DBD) which can be easily designed and integrated into plurality of versions of process integration flow,

[0191] In an invention embodiment, the CCD mechanism of a charge transfer is exploited to transfer a charge from the VG-MOS-PD inversion layer to the planar FD of the CMOS IS. It is a well known fact that CCD provides an almost perfect switching from high to low resistive interconnection during retention and transfer of the photo-generated charges. The CCD is nothing but a chain of closely placed MOS-capacitors with the inter-gate distance comparable to the gate dielectric thickness. In the invention embodiment, the two phase CCD structures comprise the VG- MOS-PD as the charge collecting device and the T_x vertical gate MOSFET in a closed proximity as the CCD-based charge transfer device having both devices formed without any doped junctions in the substrate between the two vertical CCDs. A layout view of a photosensitive part of a CMOS IS pixel embodiment having the VG-MOS-PD and the T_x MOSFET operating in a Vertical Gate CCD (VG-CCD) mode is illustrated in Fig. 68. The usage of the VG-CCD in CMOS IS pixel is not known by today and invented here for the first time. An integrated charge from the VG-MOS-PD is transferred to the planar Floating Diode 083 through two T_x VG-CCD structures operating instead of the T_x transistor with the vertical gates 099 connected to the T_x gate voltage. The key feature of such a structure is the inter-gate vertical isolation thickness 096, determining the charge transfer efficiency, and method of its fabrication for the vertical gates. Layer 096 is the inter-CCD gate isolation made in a similar fashion as the inter-CCD gate isolation in the planar CCD-chain but fabricated in vertical direction, not horizontal (planar) one.

[0192] Process integration flow features the following main process integration steps of fabricating the layers 086, 087, 096, 099: (i) a formation of the BBS-GBD prefabricated structure like shown in Fig. 59 and described above, (ii) a litho step to open the VSTB Cap 101 around the PD, the Fin (channel path) 097 from the PD to the FD 083, and a part of the FD 083 which is connected to the Fin 097; (iii) etching away the VSTB cap 101 and photoresist removal, (iv) anisotropic selective etching of c-Si to form a deep gate trench between 3 semiconductor devices such as c-Si PD bar areas 450, T_x Fin 097, and FD single side wall 083 and the isolation layer made of the STI area 300 (covered by the STI protective cap 301), (v) formation of the gate dielectric 086 by, for example, a thermal oxidation of the c-Si trench wall or/and by a gate dielectric stack deposition process; (vi) deposition of a heavily appropriately doped poly-Si 087 followed by CMP; (vii) a litho step to open areas of the vertical gate transistors T_x served as the CCDs and etching poly-Si away followed by photoresist removing; (vii) cleaning the gate oxide damaged by poly-Si etch; (ix) a thermal oxidation of c-Si and poly- Si 087 or/and a gate dielectric stack deposition to form the gate dielectric 086 and the inter-gate isolation layer 096; (x) a deposition of a heavily appropriately doped poly- Si layer 099 to form CCD gates 099 followed by CMP; (xi) a recess of poly-Si in 087 and 099 areas; (xii) a cap 098 isolation material deposition on the top of the gates 087 and 099 followed by CMP. All other of PSC can be fabricated as planar MOSFETs or as the VSTB-FETs in the same way as it is described for the structures illustrated in Fig. 61, Fig. 62, Fig. 63, Fig. 64 and Fig. 67. Contacts 351 to the gates 087 and 099 are done using the appropriate VSTB-FET Source/Drain electrodes formation process.

[0193] If desired, the semiconductor bulk substrate can be replaced with the thick SOI substrate which can provide some additional benefits of reduction of the color contamination effects as well as the ADC decoupling enhancement through the substrate isolation as illustrated in Fig. 69. To achieve these benefits the STI in the thick SOI layer is formed deep down but not touching the BOX, but touching the top of a moderate to high doped thin bottom SOI sub-layer 210 which provides an electrical connection to the ground and does not allow the PD outside potential to be floating. Thus SOI version of a product can be fabricated with no change of a product mask set at a cost of slightly complex process integration flow. The very thin highly conductive layer 210 helps also to reduce the parasitic leakage (dark) current generation at the BOX-SOI interface which has typically a high interfacial trap density (D_it) and to remove the holes generated by the light and collected at the bottom of the VG-MOS-PD SCR. If desired, the ultra-thin layer 210 in a range from 3nm to lOnm having a moderate to high doping level in a range from 3 el 7cm^"3 to 3el9cm^"' at the bottom of SOI thick layer can be formed by dopant drive-in process from the Boron Silicate Glass (BSG) thin layer 206 of thickness in a range from 5nm to lOnm, preformed on the top of the BOX, into the SOI bottom layer during high temperature anneal when baking a BOX carrier wafer and a SOI carrier wafer. Note that an optional layer 207 is shown in Fig. 69 where it is placed on the top of the BSG layer which helps keep the drive-in Boron diffusion from the BSG layer into the SOI layer under a tighter control. Usage of composite BOX having a thermal oxide 205 in a range from lOnm to lOOnm and a very thin BSG layer 206 in a range from 5nm to 20nm is beneficial in another aspect. The BSG layer 206 has significantly reduced critical viscous flow temperature vs. the thermal oxide which provides a significantly less baking temperature for a stable adhesion of the SOI to BOX. And the less baking temperature generates much less densities of the point defects in BOX and at the BOS-SOI interface which are the important performance parameters of SOI wafer responsible for a product reliability and a leakage current due to high ¾ at the BOX-SOI interface. Also the doped SOI bottom layer 210 can be used as the etch depth control layer when etching trench for forming the STI 300 or the gate trench 087 in the bar perimeter 450 or the CCD gate trench 099 by controlling B atom concentration in plasma outcome gas so that the end of the etching time is set at the moment when B signal appears. Other way of fabricating bilayer BOX is to implant high Boron dose in a range from 3el5 cm-2 to 3el6 cm-2 at low energy into the top portion of the BOX which is an easy method to make a buried Boron source instead of the BSG deposition on the top of thermal BOX oxide. The doped sub-layer in SOI bottom is optional and can be omitted, if desired, to simplify the process flow and using the standard SOI wafers but in this case the VG MOS-PD should have a contact to the floating body of the PD isolated by STI and BOX to collect the holes generated by the light illumination. The contact can be formed to the p~ doped bar 450 by forming a hole in STI self-aligned to the bar in a similar fashion as it described in the VSTB-FET prior art approach for fabricating the p-charmel VSTB-FET SD electrodes. The SD electrode hole can be placed on the bar side opposite to the T_x transistor or CCD-transfer device (see Fig. 68 and others) where the gate 087 is to be completely or partially removed. This device design and method of its fabrication does not allow to use the same mask set as for the bulk IS described above.

[0194] The method of SOI wafer fabrication with buried BSG layer can be extended for broader applications than only CMOS IS. Also, if desired, a multi-layered BOX having three different layers stacked can be form constituting the bottom thermal oxide 205, BSG layer 206, and the top thermal oxide 207. Such a multi-layered BOX SOI wafer can be formed in two ways as follows: (i) a BOX layers stack formation by the thermal oxidation to form the layer 205, followed by the BSG layer 206 deposition, followed by a very thin non-doped thermal oxide layer 207 deposition in a range from lnm to lOnm by using HTO dielectric deposition process or the like on the top of the BSG layer, followed by putting the SOI carrier wafer on the BOX carrier wafer and baking with no changing any steps in the standard SOI formation technology; (ii) the BOX earlier wafer having a BOX layer stack formed by the thermal oxidation of the layer 205, followed by the BSG layer 206 deposition and the SOI carrier wafer having a very thin thermal oxide layer 207 in a range from lnm to lOnm are put together and baked resulting in the BSG later placed in between. The very thin oxide 207 formed on the SOI carrier wafer results in a different than the standard SOI wafer formation technology. But BSG layer as a baking counter-layer for adhesion with the thermal oxide results in a significantly less baking temperature due to having a lower BSG viscous reflow temperature. This very thin oxide layer can help keep the doping layer formation process at the SOI bottom by a high temperature anneal under a tighter control. The multi-layered BOX SOI wafers can be likely used for much broader product types than only for CMOS-IS.

IV. VERTICAL GATE CCD IMAGING SEMICONDUCTOR DEVICES AND METHODS OF THEIR FABRICATION BASED ON VERTICAL SUPER-THIN BODY SEMIC NDUCTOR ON DIELECTRIC WALL [0195] The present invention is a set of novel devices for the CCD IS comprising the VG- MOS-PD light sensors and Vertical Gates Charge Coupled Devices (VG-CCD) for the charge retention and transfer to the charge-to-voltage converter then to the ADC and methods of fabrication therein. In the following description numerous specific details are set forth in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor process and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention. Described herein are different types of the Vertical Gate CCD IS devices and methods of their fabrication. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to other skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practice without specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0196] A widely used 3 -phase CCD Image Sensor has typically a string of the MOS-based Photo Diode (MOS-PD) surrounded by two CCD's on the both sides of the MOS-PD serving as the charge retention and transfer devices. It is a well known fact that CCD provides the best electrical performance of the CCD IS due to an almost perfect switching from high to low resistive interconnection between the MOS-PD and the CCD during the retention and transfer of the photo- generated charges. The CCD structures surrounding the MOS-PD are formed without having any doped junctions between the CCD gates in the substrate. The CCD is nothing but a plurality of closely placed MOS-eapacdtances in a chain with the inter-gate distance comparable to the gate dielectric thickness. In the invention embodiment the CCD principle of a charge transfer is exploited to transfer a charge from the VG-MOS-PD. The Vertical Gate CCD's are not known by now and invented for the first time. Key features of such a structure are (a) the inter-gate vertical isolation thickness, determining the charge transfer efficiency, and method of its fabrication for the vertical gates which is the inter-CCD gate isolation is formed in a similar fashion as the planar inter- CCD gate isolation 820 (Fig. 20) in the planar CCD-chain but fabricated in vertical direction in depth of the substrate, not horizontal one; (b) the Space Ch arge Region (SCR) of the VG-MOS-PD is not covered by the gate material to allow an absorption free light penetration.

[0197] Thus this invention solves two problems at once: (i) the minimal sensible light intensity is significantly lower than for the planar CCD due to lower dark current and absence of the light absorption in the poly-Si gates and (ii) the maximal charge is significantly larger due to the larger MOS-PD capacitance than for a p-n-junction type of a PD so that both features together significantly increase the dynamic range. Ma y different designs of CCD-IS can be designed by using the Basic Building Structure 1 (BBS-1) illustrated in Fig. 70 for forming the Vertical Gate CCD IS having the crystalline semiconductor Vertical Thick Body (VTB) in a shape of a semiconductor Bar 160 with its protective cap 451 and the STI isolation 300. The bar cap is needed for fabricating the MOS-PD and CCD gates self-aligned to the Bar and preventing the Bar surface from damages when making the gates by poly-Si gate depositions twice and etching the poly-Si after the first deposition in between the others gates. Keeping the bar surface free of damage is important to provide a high quality and low surface roughness interface in order to reduce the dark current of the MOS-PD and CCD.

[0198] The Vertical Gate three phases CCD Image Sensor pixel array (VG-CCD IS) with the -!, V₂, and V₃ gates made of poly-Si and the V₂ and V₃ CCD interconnects 821 made of poly- Si in a simple preferable embodiment having reduced the interconnect capacitance is invented comprising the multiple CCD string pairs 821 and 862 both formed on the top isolation layer above the Bar 160 and on the opposite vertical wails in the STI trench between the two neighboring c-Si bars 160 having the vertical gate dielectric 701, having common vertical gates 820, 821, and 862 placed between the gate dielectrics 701 and isolated by a dielectric 400 from the substrate 200 and isolated by the STI 300 from the neighboring c-Si bars, having the SCR 051 under the top surface of the VG-MOS-PD's covered only by the dielectric layers 966 and 951 to allow the free light penetration in to the SCR. The top layout view and cross-sectional views of the device are illustrated in Fig. 71, Fig. 72, Fig. 73, Fig. 74 and Fig. 75. By spatial translation of the fragment shown in Fig. 71 to the right and to the left directions as well as up and down, a plurality of CCD imagers can be formed constituting the CCD-based Image Sensor array.

[0199] A critical process and design feature of the VG-CCD IS pixel structure invented and being illustrated in Fig. 71 is related to both forming a thin inter-CCD-gate isolation layer and reducing the parasitic capacitances between the interconnections determined by the spacer thicknesses 809. The dielectric 400 is formed as a leftover of a STI dielectric etch process during a certain time. The V₂ and V₃ lines are fabricated, for example, from a highly doped poly- Si, being preferably p-type doped, and they are going across the CCD area in horizontal direction, and the gate interconnect Vi lines of the VG-MOS-PD are going in the vertical direction in, for example, Metal-1 layer. The VG-MOS-PD's are marked by the light strike sign. [0200] The process integration flow of a simple preferable embodiment of the VG-C CD-IS with the V_1; V₂, and V₃ gates made of poly-Si and the V₂ and V₃ CCD interconnects 821 made of poly-Si having reduced interconnect capacitance can be broken in to two modules. The first process module results in the Basic Building Structure 1 (BBS-1) which is illustrated in Fig, 70 as a cross- sectional view and has the following steps: (i) STI hard mask layers formation; (ii) a lithography step to form a STI hard mask; (iii) a photoresist removal, (iv) etching of c-Si substrate followed by the standard process of the STI dielectric formation of the liner by a thermal oxidation step followed by a filling with HDP Si02 deposition followed by the STI dielectric CMP step leaving the STI hard mask as the c-Si bar cap 451 (option 1); (v) a deposition of the interlayer dielectric 966 such as, for example, TEOS oxide. Thus a set of vertically oriented long c~Si bars 160 having the protective cap 451 on the top surface and isolated from each other by the narrow STI strips 300 and covered with the interlayer dielectric 966 is fabricated. The Option 1 results in a bi -layer of the cap having the STI hard mask pad oxide left and a thin SiN layer left out of the thick STI SiN hard mask layer by stopping CMP after a certain time having the thickness to be enough to provide a good protection of the Bar surface from etching poly-Si layers several times when forming VG- MOS-PD and CCD's. The cap should provide and keep a very good interface quality of the c-Si and high temperature thermal oxide. If desired, an Option 2 can be realized by selective etching away of the SiN layer followed by a short time high temperature thermal re-oxidation step (RTO) for improving the interface quality followed by depositing of another dielectric layer, for example, A1203 in the recess left after SiN removal, followed by the CMP to remove the A1203 layer from the top of the STI. It is known that AI203 dielectric has by nature a negative built-in charge whereas the Si 02 has by nature a positive charge, thus allowing by experimentation to provide an optimal surface potential which reduces the dark current generation by the top interface. Using a single SiN layer assumed in Option 1 does not allow such an optimization because it has by nature a positive charge.

[0201] The second process module which modifies the BBS-1 in to a particular device configuration as a preferable embodiment has the following steps: (i) the lithography step to open V₂ and V₃ interconnect 821 areas adjacent to the odd PD rows followed by etching the long horizontal trenches in the interlayer dielectric stack 966 stopping at the STI top and the c-Si bar cap 451 followed by the photoresist removal and fabrication of the dielectric spacers 809 on the trench edge walls serving as the isolation between the upper parts of the CCD gate interconnects made of, for example, SiOC or any other dielectric having high selectivity to the STI etching; (ii) a lithography step to open the CCD gate areas 823; (iii) a deep CCD gate areas anisotropic etching in the STI dielectric selectively to the c-Si bar and c-Si bar cap and to the spacers 809 having the etching process stopped by time and leaving at the STI bottom the leftover dielectric 400 to reduce the gate-to-substrate capacitances and to separate the CCD strings, followed by photoresist removal; (iv) the gate dielectric 701 formation by, for example, the thermal oxidation of the walls of the c-Si bar 160 followed by the gate electrode formation by, for example, p+-doped poly-Si deposition, followed by a CMP step to pianarize the surface down till the interlayer dielectric 966, thus having a half of the CCD gates and local interconnect lines 821 fabricated; (v-viii) repeating the steps (i-iv) for forming the CCD gates and interconnects adjacent to the even PD's thus having the dielectric 707 and the gates and interconnects 862 being fabricated having them self-aligned to the gates and interconnects 821. The next steps are related to the VG-MOS-PD gate formation: (ix) a lithography step is applied to open a location of the VG-MOS-PD gate 820 followed by selective etching the interlayer dielectric 966 and the deep anisotropic etching of the STI selectively to the c~ Si bar and to the spacers 809 having the etching process stopped by time and leaving at the STI bottom the leftover dielectric 400 to reduce the gate-to-substrate capacitances and to separate the CCD strings followed by photoresist removal, (x) a formation of the gate dielectric layer 701 and the dielectric layer 707 by the thermal oxidation of the walls of the c-Si bar 160 and the neighboring poly-Si gates 821 and 862, followed by the gate electrode formation by, for example, p+-doped poly-Si deposition, and finished by the CMP step to planarize the surface till the dielectric layer 966; (xi) if desired, a recess can be done in all poly-Si areas before the deposition of the protective dielectric layer 951 and the recess filled in with highly conductive layer made of a WSi2 layer or a stack of TiN or TaN and W layers or a stack like this to reduce the seri es parasitic resistance of the interconnections followed by a CPM to planarize the structure; (xii) if desired, the poly-Si gates and interconnects can be replaced by a stack formed from the work function layer (like p+-doped poly- Si) 860 covered with the low resistive material (like TiN+W bilayer) 861 as illustrated in Fig. 74; (xiii) if desired, a common protective cap layer 951 can be deposited on the top of the all layers to protect the metal interconnects from an oxygen and moisture contaminations in to the metals and resistivity increase, having in a simple and practical invention embodiment heavily p-type doped poly-Si gates and interconnects and as low as possible doped c-Si substrate 200 would be the optimal material choice; (xiv) a deposition of the interlayer isolation followed by the via-1 formation to the VG-MOS-PD gates 820 and to the V₂ and V₃ interconnects. Vj interconnect lines are done in the metal- 1 and go in the vertical direction. If desired, the V^"i interconnect line can be made going along the horizontal direction over the V₂ or V₃ interconnections. The layer 951 and the dielectric 966 are not shown in Fig. 71 for all device features illustration clarity. [0202] The Basic Building Structure 2 is illustrated in Fig. 76 which can be used for many- particular embodiments of the CCD IS arrays which is constructed from the bulk substrate 200 having the STI layers 300 and the bars 160 on the top where the STI has its own cap 301 whereas the Bar has three caps with two the same caps 101 adjacent to the STI caps and a cap 451 in between those ones. All three cap materials are mutually selectively etchable. [0203] The VG-CCD IS pixel structure with the reduced interconnect capacitance and a high charge transfer efficiency due to a reduced inter-gate isolation thickness is invented and the top layout vi ew and cross-sectional views of the structure are illustrated in Fig. 77 to Fig. 81, where the VG-MOS-PD's marked by the strike sign. The pixel structure comprises VG-MOS-PD, having the top surface of the SCR 051 covered only by the dielectric layers to allow the absoiption free light penetration in to the SCR, and CCD string pairs 355 with the common gate 355 per the pair for the charge retention and transfer formed on the opposite vertical walls of the two neighboring c-Si bars 160 having the gate dielectric 701, having poly-Si vertical gates 079 and 087 adjacent to the gate dielectric and isolated by the thin dielectric 096 from each other, having low resistive gate electrodes 351 and 355 placed between the opposite poly-Si gates, isolated by a dielectric 400 from the substrate 200, isolated by the STI 300 covered by the STI cap 301 from each other at the low portion of the gate electrode, isolated by the interlayer dielectric 952 from each other at the upper portion of the gate electrode where the upper portion serves as the local interconnects V₂ and V₃, having the STI 300 on the opposite to the gates sides serving for the CCD vertical channel string pairs isolation from the neighboring CCD vertical channel string pairs. By spatial translation of the fragment shown in Fig. 77 to the right and to the left directions as well as up and down, a VG-CCD IS array can be formed having plurality of the pixels.

[0204] V^'i interconnects are formed in Metal-1 layer in a particular embodiment. The thin dielectric isolation 096 between the vertical poly-Si CCD gates is a bit thicker but comparable with the gate dielectric 701 thickness in a typical range from 2 nm to 20 ran and made of a-Si02 (thermal oxide is preferable) or any other dielectric material providing the low Density of the Interfacial Traps (D_it) or a stack of a-Si02 and some high-k dielectrics, if desired. The highly conductive CCD gates have small parasitic capacitances between them due to the small area of capacitive coupling, where the dielectric is thin, but the thick dielectric between the gate electrodes where the coupling area is large. The SCR areas 051 are not covered by the gate conductive material to allow the absoiption free light penetration in to them. By spatial translation of the structure shown in Fig. 77 to the right and to the left directions as well as up and down a vertical gate CCD Image Sensor array can be formed. [0205] The first VG-CCD IS process module (Module 1) has the following steps: (i) STI hard mask layers formation typically made of a stack of the thermal pad oxide and SiN deposited; (ii) a lithography step to form a STI hard mask; (iii) a photoresist removal; (iv) etching of the hard mask stack; (v) a non-standard steps of the cap layer 101 formation by using spacer formation process comprising the spacer material layer deposition such as A1203 or a stack of a ultra-thin interfacial layer of thermal a-Si02 and A1203 or, if desired, a stack of a ultra-thin interfacial layer of a-Si02, an ultrathin SiN, and A1203 deposited by ALD method, followed by an anisotropic etch back leaving the spacer as a cap 101 at the edges of the STI hard mask; (vi) etching the c~Si substrate followed by the standard process of the STI dielectric formation by the liner thermal oxidation step followed by the HDP Si02 deposition followed by the STI dielectric CMP step, (v) a non-standard step of forming a recess in the STI; (vi) fiiiing-in the recess with the STI protective cap 301 dielectric layer such as SiOC, Ta_xSi_y02 or the like followed by CMP; (vii) option 1 : keeping the STI hard mask as a cap 451, or option 2: the STI hard mask material removal followed by filling-in the ultra-shallow trench with the c-Si bar protective cap dielectric 451 such as SiON and CMP till the top of the STI protective cap 301. A plurality of long c-Si bars 160 having the protective caps 451 and the spacer 101 on the top surface and isolated from each other by the STI 300 with the STI protective cap 301 is thus formed. The Module 1 results in Basic Building Structure 2 (BBS-2) that is shown in Fig. 76. If desired, a thin cap 101 can be formed at the edge of the STI protective cap 301, which is formed in the same way as described above, followed by a selective removal of the STI hard mask in between caps 302 resulting in a recess in between the STI caps, followed by the cap material deposition such as A1203 followed by the anisotropic etch after the STI hard mask removal, leaving a thin cap layer 101 next to the STI cap layer edges followed by tlie bar cap 451 formation by tlie cap material deposition followed by CMP leaving the cap in the recessed area. Guidance for choosing the former or the latter method comes from the practically achievable mutual etching selectivity for these three caps layers and thicknesses needed for making the devices.

[0206] The VG-CCD IS process integration is Module 2 which has the following steps; (i) a lithography step using a strip like mask is applied to open CCD gate areas and removing the spacer 101 followed by the anisotropic selective etching of c-Si away to form narrow gate trenches self- aligned to the STI isolation and to the c-Si bars 160 used to place the VG-CCD SCR' s to retain and transfer the light generated charges through the entire column; (ii) the gate dielectric 701 is formed by the thermal oxidation of the c-Si bar walls or a deposition followed by the 1^st heavily p+-doped poly-Si deposition 079 followed by a CMP to planarize the surface; (iii) a lithography step using a horizontal strip like mask is applied to open areas for odd gates 087 followed by the etching away of the 1^st poly-Si till the gate bottom to form the trench set of odd gates 087; (iv) removing the photoresist and removing the gate oxide damaged by 1 ^st poly-Si etching; (v) formation of the gate dielectric 701 on the c-Si bar 160 walls and the inter-gate dielectric 096 on the 1^st poly-Si walls of the even gates 079 by the thermal oxidation of c-Si bar or a deposition followed by the 2^nd heavily p+-doped poly-Si deposition; (vi) a CMP step of poly-Si till tlie protective cap 451 to planarize the surface and to finish the formation of the gates 079 and 087; (vii) the interlayer dielectric 952 deposition on the top of the CCD structures; (viii) a lithography step is used to open holes in the interlayer dielectric 952 for low resistive gate electrodes 351 and gate electrodes and interconnects 355 followed by the etching away the interlayer dielectric 952 selectively to the STI cap 301, to the c-Si bar protective cap 451 and poly-Si gates 087 & 079; (ix) a lithography step to open areas between the poly-Si gates for low resistive gate electrodes followed by a selective anisotropic etching of the STI protective cap 301 and the STI dielectric 300 leaving the STI left-over layer 400 to isolate the gate electrodes from the substrate; (x) deposition of a low resistive layer 351 and 355 self-aligned to the vertical poly-Si gates, for example, a metal stack made of a TIN barrier layer and a W layer followed by a planarization by CMP till the top of the layer 952 to form the local interconnect lines V₂ and V₃ and contacts to all the poly-Si vertical gates, (xi) deposition of the protective layer 951 to suppress an oxygen and moisture contamination of a metal conductor like W and resistivity deterioration.

[0207] For clarity of illustrating the VG-CCD pixel structure, the interlayer dielectric 952 and the layer 951 are not shown in Fig. 77. Also as indicated in Fig. 78, Fig. 80 and Fig. 81, there is no a cap layer on the top of the gates 087 and 079 since the selectivity of poly-Si, as the primary material for the gate, when etching Si02 or Si3N4 or other materials is very high. If desired, one can fabricated a gate cap layer by forming a recess in the gate 087 and 079 followed by a cap material deposition and CMP, Skilled in the art engineers can choose different sets of materials for the STI protective cap 301, the c-Si bar cap 451 and the spacer 101 having them mutually selective in etching to increase the manufacturability of the device.

[0208] The VG-CCD IS pixel array structure is invented to provide a higher VG-MOS-PD density. The invention illustrated in Fig. 82 and Fig. 83 comprises VG-MOS-PD, having the top surface of the SCR 051 covered only by the dielectric layers to allow the absorption free light penetration in to the SCR and CCD string pairs for the charge retention and transfer, having CCD gate layers 079 and 087 formed on the opposite vertical walls of the two neighboring c-Si bars 160 isolated by the gate dielectric 701 from the bars, having poly-Si vertical gates 079 and 087 adjacent to the gate dielectric and isolated by the thin dielectric 096 from each other, having the low resistive gate electrodes 351 placed between the two poly-Si gates, isolated by a dielectric 400 from the substrate 200, isolated by the STI 300 covered by the STI cap 301 from each other at the low portion and isolated by the interlayer dielectric 952 from each other at the upper portion of the layers being served as a part of local interconnects V₂ and V₃. A top layout view of this VG-CCD pixel structure is illustrated in Fig. 82 where dielectric layers 952 and 951 and the gate dielectric 701 adjacent to the bar 160 are not shown for clarity of the basic idea. The structure cross-sectional views are show in Fig. 83 and in Fig. 79. By spati al translation of the fragment shown in Fig. 82 to the right and to the left directions as well as up and down a plurality of the VG-CCD IS organized in an array can be formed. This is a design which takes a smaller area for the photosensitive devices (VG-MOS-PD), charge retention and charge transfer devices (CCD), and interconnections. VG- MOS-PD, marked by the lightening strike sign, being here VG-CCD-PD accumulates (integrates) a certain charge due to illumination proportional to the light intensity and an integration time while holding a high voltage pulse on the CCD gate 087 through Vj line. Then the charge is retained and transferred to reading IC through a vertical CCD-column on the left and right hand sides pulsed by- voltages through V₂ and V₃ lines together with V₃ line as 3 phase CCD system. Layer 096 is the inter-CCD gate isolation made in a similar fashion as for the inter-CCD planar gate isolation in the planar CCD-line but fabricated in vertical direction in to the c-Si substrate depth keeping the light absorption free open area above the CCD-PD for the illumination going through the dielectric stack on the VG-CCD-PD. A more dense VG-CCD-IS is created due to the absence of the STI isolation between the two PD SCR 051. This feature requires a certain distance between the two gates which is to be of two SCR thicknesses in a range from Ι μηι to 5μιη for the MOS-structures at the low substrate doping level in a range from lel4 cm^'3 to 3el6 cm^"3 and operation gate voltages in arrange from 1 V to 5 V or about.

[0209] The total process integration flow is very similar to that of the VG-CCD IS device illustrated in Fig. 77 to Fig. 81. The process Module 1 described above can be used as the first VG- CCD IS process module for this invention and BBS-2 can be used as a start structure for the second process module. [0210] Using BBS-2 as the initial structure, the process Module 2 for the dense VG-CCD IS has following steps: (i) a lithography step using a strip like mask is applied to open CCD gates areas and removing the spacer 101 followed by the anisotropic selective etching of c-Si away to form the narrow gate trenches self-aligned to the STI isolation walls and to the c-Si bars 160 walls; (ii) the gate dielectric 701 is formed by the thermal oxidation of the c-Si bar walls or deposition followed by the 1^st heavily p+-doped poly-Si deposition and CMP to planarize the surface; (iii) a lithography step using a horizontal strip like mask is applied to open areas for even gates 079 followed by the anisotropic etching away of the 1^st poly-Si to form the set of odd gate trenches 087, (iv) removing the photoresist and removing the gate oxide damaged by 1^st poly-Si etching; (v) the gate dielectric 701 on the c-Si bar 160 wails and the dielectric 096 on the 1st poly-Si walls of the odd gates 087 are formed by the thermal oxidation of c-Si bar or deposition followed by the 2^nd heavily p+~doped poly- Si deposition; (vi) a poly-Si CMP step till the protective cap 451 to planarize the surface thus forming the even gates 079; (vii) deposition of the interlayer dielectric 952 on the top of the CCD structure; (viii) a lithography step is used to open holes in the interlayer dielectric 952 for the low resistive gate electrodes 351, gate electrodes and interconnects 355 followed by the anisotropic etching away the interlayer dielectric 952; (ix) selective etching the STI cap 301 allows to form the gate electrodes in a self-aligned fashion to the vertical poly-Si gate layers having continued etching of the STI 300 selectively to the protective cap 451 and the poly-Si top surface, leaving the STI left- over layer 400 of a certain thickness by a certain etching time to isolate the gate electrodes from the substrate; (ix) deposition of a low resistive layer 351 and 355, for example, a metal stack made of a TIN barrier layer and a W layer followed by a pianarization by CMP till the top of the layer 952 to form the local interconnect lines V₂ and V₃ and contacts to all the poly-Si vertical gates; (x) deposition of the protective layer 951 to suppress an oxygen and moisture contamination of a metal like W and resistivity deterioration.

[0211] This device design, having two VG-MOS-PD's in the same wide c-Si bar 160, is less sensitive to the D,_t at the interfaces between the STI 300 to the c-Si bar 160 because there is little interaction between the SCR's 051 with the STI walls only in the SCR bottom areas to the contrary of the design illustrated in Fig. 77 to Fig. 81 having a large area of such an interaction where the SCR 051 is touching the STI isolation walls. This feature can be used as an advantage which reduces the process flow steps related to the it passivation by H2 or D2 like a forming gas anneal or a special anneal in H2 at elevated temperatures in a range from 400C to 450C and a time duration in a range from 30 min to 3 min right after the structure formation which would be the typical steps for that process (not discussed in any details since it is a typical method) and can be skipped in this process resulting in a simpler and less costly process.

[0212] The c-Si bar width in the horizontal direction has to be optimized. If the two SCR's edges in the middle of the c-Si bar 160, established after the Vi pulse is set in steady-state condition, are hardly touching each other, then there is no mutual coupling of two neighboring CCD-PD's. The criterion for "no touching" is an almost zero electric field near the SCR edges. One should realize that at the exact middle of the c-Si bar the electric field is zero at any initial biasing conditions. But if the edges are touching each other and competing for the space then a rather high electric field is created near the edges and when one CCD-PD is having a more intense light its SCR thickness reduces faster during the integration time than the other SCR thickness. In this situation the SCR of the CCD-PD with a less light intensity start spreading towards the other CCD- PD and a cross-contamination by the light occurs resulting in the cross-coupling effect and the image distortion which is not a desirable effect to be avoided by a proper design optimization. For a typical doping of the PD area in a range from 3el4 cm-3 to 3el5 cm-3 and typical gate voltage V_g at Vi phase in a range from 10 V to 1 V the SCR thickness is in a range from 1 μηι to 3 μηι or so. [0213] From the foregoing, it will be appreciated that specific embodiments of the inventi on have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Claims

1. A transistor device, comprising: a semiconductor substrate; a dielectric body, the dielectric body embedded in the semiconductor substrate and including sidewalls; a semiconducting vertical super-thin body ("VSTB") formed from the semiconductor substrate and supported by at least the sidewall of the dielectric body, the VSTB serving as a channel for the transistor device, the VSTB is at most low-doped and has a first side and a second side: a gate formed on the first side of the VSTB, the gate having a gate shadow where the gate shadow refers to the spatial region immediately opposite the gate on the second side of the V STB; and a Schottky junction source and drain pair formed on the second side of the VSTB, and the source and drain pair at least partially intersecting the gate shadow.

2. The transistor device of claim 1, the gate further comprising: a gate electrode; and a gate stack including a dielectric layer and a metal layer,

3. The transistor device of claim 2, wherein the dielectric layer and metal layer of the gate stack surround the gate electrode and the metal layer touches a plurality of sides of the gate electrode.

4. The transistor device of claim 2, wherein the dielectric layer of the gate stack is formed parallel to the length of the VSTB and extends beyond the dimensions of the gate electrode, while the metal layer of the gate stack only touches sides of the gate electrode which face the VSTB and extends to only the dimensions of the gate electrode.

5. The transistor device of claim 1 , wherein the Schottky junction aspect of the source and drain pair is formed with a silicide layer in contact with the second side of the VSTB and a metal layer in contact, with the silicide layer.

6. The transistor device of claim 1, wherein the Schottky junction aspect of the source and drain pair is formed with a silicide layer in contact with the second side of the VSTB and the silicide layer surrounding a metal layer.

7. A transistor device, comprising; a semiconductor substrate; a dielectric body, the dielectric body embedded in the semiconductor substrate and including sidewalls, a channel formed from the semiconductor substrate from semiconducting material and supported by at least the sidewall of the dielectric body, the channel is at most low-doped and extends from the semiconductor substrate having a first side and a second side; a gate formed on the first side of the channel; and a Schottky junction source and drain pair formed on the second side of the channel.

8. The transistor device of claim 7, the gate further comprising: a gate electrode; and a gate stack including a dielectric layer and a metal layer.

9. The transistor device of claim 8, wherein the dielectric layer and metal layer of the gate stack surround the gate electrode and the metal layer touches a plurality of sides of the gate electrode.

10. The transistor device of claim 8, wherein the dielectric layer of the gate stack is formed parallel to the length of the channel and extends beyond the dimensions of the gate electrode, while the metal layer of the gate stack only touches sides of the gate electrode which face the vertical channel and extends to only the dim ensions of the gate electrode.

11. The transistor device of claim 7, wherein the Schottky junction aspect of the source and drain pair is formed with a silicide layer in contact with the second side of the channel and a metal layer in contact with the silicide layer.

12. The transistor device of claim 7, wherein the Schottky junction aspect of the source and drain pair is formed with a silicide layer in contact with the second side of the vertical channel and the silicide layer surrounding a metal layer.

13. The transistor device of claim 11, wherein the silicide layer is formed at the expense of the thickness of the channel.

14. The transistor device of claim 8, wherein multiple transistor devices share a common gate electrode.

15. The transistor device of claim 7, wherein multiple transistor devices are stacked in tiers, and wherein the tiers are separated by a dielectric isolation layer.

16. The transistor device of claim 14, wherein the multiple transistor devices sharing a common gate electrode are a combination of both p-channel transistors and n-channel transistors.

17. A system of transistor devices organized in tiered layers, transistor devices within inner tiers each comprising: a semiconductor substrate; a dielectric body, the dielectric body embedded in the semiconductor substrate and including sidewalls; a semiconducting vertical super-thin body ("VSTB") formed from the semiconductor substrate and supported by at least the sidewali of the dielectric body, the VSTB serving as a channel for the transistor device, the VSTB is at most low-doped and has a first side and a second side; a gate formed on the first side of the VSTB, the gate having a gate shadow where the gate shadow refers to the spatial region immediately opposite the gate on the second side of the VSTB, a Schottky junction source and drain pair formed on the second side of the VSTB, and the source and drain pair at least partially intersecting the gate shadow; and a dielectric isolation layer electrically separating the transistor device from the semiconductor substrate of transistor devices on the tier above.

18. The system of transistor devices of claim 17, wherein each tier is configured as an integrated circuit with a specific function including any of:

SRAM; DRAM; microprocessor; system-on-chip; NAND Flash memory; NOR Flash memory; analog/RF; and

CMOS image sensors.

19. The system of transistor devices of claim 17, wherein multiple transistor devices share a common gate.

20. The system of transistor devices of claim 17, wherein the semiconductor substrate is a semiconductor-on-isolator (SOI) wafer, and the dielectric isolation layer of a first tier is the semi conductor substrate of a second, upper tier.

21. A method for constructing a transistor device within a semiconductor wafer, the method comprising: forming a dielectric body embedded in the semiconductor wafer and including sidewalls; forming a super-thin channel extending from the semiconductor wafer using semiconducting material from the semiconductor wafer in contact with the sidewail of the dielectric body, and without a high-temperature doping process; forming a gate abutting the channel, on the side of the channel opposite the dielectric body; and forming a Schottky junction source and drain pair within trenches in the dielectric body and abutting with the channel,

22. The method of claim 21, said forming the gate further comprising: forming a gate electrode; and forming a gate stack including a dielectric layer and a metal layer,

23. The method of claim 22, wherein the dielectric layer and metal layer of the gate stack surround the gate electrode and the metal layer touches a plurality of sides of the gate electrode.

24. The method of claim 22, wherein the dielectric layer of the gate stack is formed parallel to the length of the channel and extends beyond the dimensions of the gate electrode, while the metal layer of the gate stack only touches sides of the gate electrode which face the vertical channel and extends to only the dimensions of the gate electrode.

25. The method of claim 21, wherein the Schottky junction aspect of the source and drain pair is formed with a siiicide layer in contact with the second side of the channel and a metal layer in contact with the siiicide layer. 26, The method of claim 21, wherein the Schottky junction aspect of the source and drain pair is formed with a silicide layer in contact with the second side of the vertical channel and the silicide layer surrounding a metal layer.