WO2017008245A1

WO2017008245A1 - Transformer-less static synchronous series compensator and method therefor

Info

Publication number: WO2017008245A1
Application number: PCT/CN2015/083967
Authority: WO
Inventors: Tinho LI; Hailian XIE; Nicklas Johansson
Original assignee: Abb Technology Ltd
Priority date: 2015-07-14
Filing date: 2015-07-14
Publication date: 2017-01-19
Also published as: WO2017008245A9

Abstract

A transformer-less static synchronous series compensator for an AC electrical power transmission system having a transmission line carrying an AC current and a method therefor. The transformer-less static synchronous series compensator includes a multiple of voltage source converters (100a, 100b... 100n), each of which having DC input and AC output and being configured to generate an alternating voltage with controllable magnitude and controllable phase angle across the AC output; wherein the AC outputs of the multiple of voltage source converters are configured for parallel-injection of the generated alternating voltages into a phase of the transmission line (A, B, C). The AC transmission line phase current can be distributed to the multiple of inputting the alternating voltages in parallel into the phase of the AC transmission line, and thus the current handling capability requirement for power semiconductor switches used in each of the voltage source converter can be significantly reduced.

Description

TRANSFORMER-LESS STATIC SYNCHRONOUS SERIES COMPENSATOR AND METHOD THEREFOR

Technical Field

The invention relates to transformer-less static synchronous series compensator (SSSC) for AC electrical power transmission system， and more particularly to the SSSC with scalable power converters and the method therefor.

Background Art

In AC transmission systems， the load-ability of AC transmission lines is limited mainly due to existence of line reactance. Series compensation (SC) is an effective way to increase power transmission capability of AC transmission lines. It is known to insert fixed series capacitor (FSC) in series with the AC transmission lines. Such arrangement may compensate the reactance of the AC transmission lines， such that the transmission capacity can be improved and the voltage and angular stability of the connected systems can be enhanced. One difficulty with FSC compensation is that there exists a risk of sub-synchronous resonance (SSR) .

Concept of introduction of controllability to SC to mitigate the SSR has been proposed. An optional technology of controllable series compensation (CSC) is static synchronous series compensation (SSSC) . The compensator includes a transformer connected in series in an AC transmission line of AC electrical power transmission system， and a converter connected with the transformer in parallel. The converter can generate and inject into the AC transmission lines an alternating voltage with desired magnitude and phase angle. An example of SSSC is provided in U.S. Pat. No. 5,814,975 entitled “Inverter Controlled Series Compensator” . However， the transformer adds significantly to the cost and complexity of the apparatus and renders it less efficient.

Recently， the concept of a transformer-less static synchronous series compensator has been disclosed. An AC side of its converter can be electrically connected in series with a phase of the AC transmission lines without a coupling transformer of the conventional design. Such solution is described in “Static Synchronous Series Compensator (SSSC) ” ， CIGER B4-40， February 2009， ISBN： 978-2 85873-058-2. By eliminating the need for a series coupling transformer， the transformer-less SSSC has advantages， such as simpler configuration， smaller footprint， lower cost and loss， etc. It is also known to utilize a filter electrically coupled with the AC output of the converter in parallel for harmonic suppression. One approach to provide such filter is a combination of inductive element and capacitive element. In a transformer-less SSSC， the magnitude and phase angle of the AC voltage output through the AC side is controlled thus resulting in compensator supplying reactive power or absorbing reactive power from a phase of the AC transmission line. The converter of the transformer-less SSSC comprises at least four self-commutated power semiconductor switches， each of which is shunted by a revers or anti-parallel connected diode. IGBT is the popular power semiconductor switch due to the favourable characteristics of dynamic performance. The current handling capability of single conventional IGBT module is limited to around 2kA rms. IGCT can be alternative giving around 3.3kA rms current but the thermal resistance of the IGCT is roughly 2 times of IGBT， which limits the power density and requires much powerful cooling system. For high current applications especially when overcurrent handling ability is required in fault situations， it is desirable to increase current handling capability of the power converter.

It is known that by parallel-linking power semiconductor modules， it is helpful for reducing the current handling capability required for the individual module. The number of power semiconductor modules in parallel is proportional to the AC current rating of the system， and for high current application， consequently include a large number of modules. Paralleling of modules requires sophisticated gate driver to manage both the dynamic and steady-state current balancing issues between the modules. Failure of one module may over stress the rest of the modules in parallel. Subsequent failure may occur and reliability of the system is not guaranteed.

Brief Summary of the Invention

According to an aspect of the invention， it provides a transformer-less static synchronous series compensator for an AC electrical power transmission system having a transmission line carrying an AC current， including： a multiple of voltage source converters， each of which having DC input and AC output and being configured to generate an alternating voltage with controllable magnitude and controllable phase angle across the AC output； wherein： the AC outputs of the multiple of voltage source converters are configured for parallel-injection of the generated alternating voltages into a phase of the transmission line.

According to another aspect of the invention， it provides a method for compensating an impedance of a phase of a transmission line of an AC electrical power transmission system， including： (a) generating a multiple of alternating voltages each with controllable magnitude and controllable phase angle in consideration of measured value for alternating line current through the phase of the transmission line， measured value for alternating voltage injected into the phase of the transmission line and a predetermined reference value for effective impedance； and (b) injecting the generated multiple of alternating voltages in parallel into the phase of the transmission line so as to compensate its impedance.

In accordance with the present invention， the AC transmission line phase current can be distributed to the multiple of inputting the alternating voltages in parallel into the phase of the AC transmission line， and thus the current handling capability requirement for the power semiconductor switches used in each of the VSCs can be significantly reduced. Accordingly， as for high current applications especially when overcurrent handing ability is required in fault situations， the number of parallel-linked power modules for sharing the current flowing through phase legs of the VSC can be lowered dramatically.

Preferably， the transformer-less static synchronous series compensator further includes an AC measuring device， being configured to measure a value for alternating line current flowing through the phase of the transmission line； an alternating voltage measuring device， being configured to measure a value for the alternating voltage generated by the multiple of voltage source converters and injected into the phase of the transmission line； and a control system， being configured to control each of the multiple of voltage source converters to generate the alternating voltage across its AC output in consideration of the measured value for the alternating line current， the measured value for the injected alternating voltage and a predetermined reference value for effective impedance. Each of the voltage source converters includes at least one energy storage element being respectively coupled with its at least one DC input in parallel and at least one DC voltage measuring device being configured to respectively measure a value for DC voltage across its at least one DC input； and the control system is further configured to： control one of the multiple of voltage source converters as master in consideration of a predetermined master DC voltage reference and the measured value for the DC voltage across the DC input of the master； and control the other voltage source converter as slave in consideration of a filtered measured value for the DC voltage across the DC input of the master voltage source converter as slave DC voltage reference and the measured value for the DC voltage across the at least one DC input of the slave.

Preferably， based on the method for compensating an impedance of a phase of a transmission line， the alternating voltage generation step (a) includes： (al) generating one of the multiple of alternating voltages by a master voltage source converter in consideration of a predetermined master DC voltage reference and measured value for DC voltage of the master； and (a2) generating the other of the multiple of alternating voltages by a slave voltage source converter in consideration of a filtered measured value for DC voltage of the master voltage source converter as slave DC voltage reference and measured value for DC voltage of the slave.

By having the DC voltage reference for the slave depend on the DC voltage of the master， a coordination control of VSCs can be established for suppressing the circulating energy among the VSCs.

Preferably， the multiple of voltage source converters are configured to be modulated by PMW； and phase shifts are arranged among carrier signals respectively for the multiple of voltage source converters.

By phase shifting the switching pattern between the VSCs， their output voltage and current ripples reduction can be achieved. An appropriate angle of the phase shift can create the most significant ripple suppression effect. The size of the filter can be shrunk； meanwhile high quality of the output voltage and current waveforms can be obtained.

Brief Description of the Drawings

The subject matter of the invention will be explained in more detail in the following text with reference to preferred exemplary embodiments which are illustrated in the drawings， in which：

Figure 1 illustrates an AC transmission system compensated by a transformer-less static synchronous series compensator according to an embodiment of present invention；

Figure 2 depicts a circuit configuration of a transformer-less SSSC 10 electrically coupled with phase A of AC transmission line according to an embodiment of present invention；

Figure 3A shows a more detailed schematic of an embodiment in accordance of figure 2；

Figures 3B illustrates topology of NPC and T-type NPC；

Figures 4A， 4B and 4C illustrate the block diagram of the control system according to the embodiment of figure 3A and 3Bbbb；

Figure 5A shows the output voltage switching waveform of dc/ac VSC 100a before the output filter and the waveform after the output filter；

Figure 5B shows the harmonics spectrum’s magnitude and phase angle information corresponding to the voltage waveform after the output filter；

Figure 6A shows an example of the phase shifted carrier signals of the configuration with 3 VSCs in parallel；

Figure 6B shows the concept of the harmonics cancellation methodology；

Figures 7A and 7B show the normalized magnitude and phase information of the output voltage spectrum before the output filter；

Figures 8A and 8B show the magnitude of the spectrums and phase plots of the 3 VSCs；

Figure 9 shows a more detailed schematic of another embodiment in accordance of figure 2；

and

Figures 10A， 10B， 10C and 10D illustrate the block diagram of the control system according to figure 9.

The reference symbols used in the drawings， and their meanings， are listed in summary form in the list of reference symbols. In principle， identical parts are provided with the same reference symbols in the figures.

Preferred Embodiments of the Invention

In the following description， for purposes of explanation and not limitation， specific details are set forth， such as particular circuits， circuit components， interfaces， techniques， etc. in order to provide a thorough understanding of the present invention. However， it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances， detailed descriptions of well-known methods and programming procedures， devices， and circuits are omitted so not to obscure the description of the present invention with unnecessary detail.

Figure 1 illustrates an AC transmission system compensated by a transformer-less static synchronous series compensator according to an embodiment of present invention. As shown in figure 1， the AC transmission system 1 includes three phases of AC transmission line A， B， C respectively for carrying current I_A， I_B， I_C. Three

transformer-less SSSCs

10， 11， 12 are respectively electrically coupled with the respective phase A， B， C in series. The three

transformer-less SSSCs

10， 11， 12 are substantially similar both in circuit configuration and operation and can operate independently from each other.

Figure 2 depicts a circuit configuration of a transformer-less SSSC 10 electrically coupled with phase A of AC transmission line according to an embodiment of present invention. As shown in figure 2， the transformer-less SSSC 10 includes a multiple of

voltage source converters

100a， 100b ... 100n. Each of the multiple of VSCs 100a， 100b ... 100n has DC input and AC output. Each of the

VSCs

100a， 100b ... 100n can be controlled to generate an alternating voltage with controllable magnitude and controllable phase angle across its AC output， and thus they can inject the generated alternating voltages into phase A of the transmission line in parallel so as to compensate the impedance of phase A. The electrical-coupling paths along which the generated alternating voltages are in parallel fed into the transmission line phase A are indicated by the arrows Pa， Pb ... Pn in figure 2. The AC transmission line phase current can be distributed to the multiple of VSCs 100a， 100b ... 100n inputting the alternating voltages in parallel into the phase of the AC transmission line， and thus the current handling capability requirement for the power semiconductor switches used in each of the VSCs can be significantly reduced. Accordingly， as for high current applications especially when overcurrent handing ability is required in fault situations， the number of parallel-linked power modules for sharing the current flowing through phase legs of the VSC can be lowered dramatically. In the preferable embodiment， the paralleling of the power semiconductor modules becomes unnecessary， since a single power semiconductor module can meet the required current handling capability. Each of the paralleling VSCs has a controller controlling itself with respect to the given references， such as voltage， current， power and etc. Thus， no sophisticated gate driver is required as there is less or no current balancing problem between its power semiconductor modules.

The

VSC

100a， 100b ... 100c can include a plurality of power semiconductor module pairs， and the power semiconductor can be IGBT， GTO， and IGCT. An AC measuring device 102 measures a value for the AC transmission line current i_Lflowing through the phase A of the transmission line， using conventional current sensing device. An alternating voltage measuring devices 103 measures a value for the alternating voltage injected into the AC transmission line， which is generated by the multiple of

voltage source converters

100a， 100b ... 100n， by using conventional voltage sensing device. A control system 105 receives the measured value for the alternating line current i_L via a first control line 106 from the AC measuring device 102 and the measured values u_inj for the alternating voltage injected into the transmission line phase A via a second control lines 107 from the alternating voltage measuring device 103. In consideration of these inputs and a predetermined reference value X_SSSC， ref for effective impedance， the control system 105 controls each of the multiple of

voltage source converters

100a， 100b ... 100n via a

third control line

108a， 108b ... 108n to generate the alternating voltages across its AC output to the phase A of the AC transmission line. The control algorithm varies from different topologies of each VSC， and thus will be described accompanying figures 3 and 9 afterwards.

Figure 3A shows a more detailed schematic of an embodiment in accordance of figure 2. As shown in figure 3A， the

VSC

100a， 100b ... 100n uses topology of H-bridge without design of paralleling power semiconductor modules. The skilled person shall understand that other topology， such as NPC and T-type NPC as shown in figure 3B， is applicable as well. Each of the

voltage source converters

100a， 100b ... 100n includes at least one energy storage element being respectively coupled with its DC input in parallel. For example， a

capacitor

104a， 104b ... 104n is coupled to the DC input of VSCs 100a， 100b ... 100n in parallel for maintaining relatively constant DC voltage of the

VSCs

100a， 100b ... 100n. The

capacitor

104a， 104b ... 104n can store electrical power supplied from phase A of the transmission line and act as a DC power source. Alternatively， the skilled person shall understand other types of DC power source， such as batteries can be utilized for supplying the DC electrical power to the

VSCs

100a， 100b ... 100n. A DC

voltage measuring device

108a， 108b ... 108n measures the value for DC voltage u_{DC_a}， u_{DC_b} ... u_{DC_n} across the DC input of the

VSCs

100a， 100b ... 100n， by using conventional DC voltage sensing device. Preferably， in order to suppress the harmonics of the alternating voltages as generated by the

VSCs

100a， 100b ... 100n， filter circuit 109 can be inserted between the phase A of the transmission line and each VSC.

If the

VSCs

100a， 100b ... 100n are controlled individually without coordination thereof， measures need to be taken to suppress circulating energy though the VSCs. The embodiment of present invention adopts master-slave control algorithm， where one of the

VSCs

100a， 100b ... 100n is selected as the master and the others are selected as slaves； for example VSC 100a as master and VSC 100b ... 100n as slaves. The control system 105 controls VSC 100a in consideration of a predetermined master DC voltage reference u_{DC_a_ref} and the measured value for the DC voltage u_{DC_a} across the DC input of the master 100a and controls the slaves 100b ... 100n in consideration of a filtered measured value u′_{DC_a} for the DC voltage across the DC input of the master voltage source converter 100a as slave DC voltage reference and the measured value for the DC voltage across the DC input of the slave 100b ... 100n. By having the DC voltage reference for the slave depend on the DC voltage of the master， a coordination control of VSCs 100a， 100b ... 100n can be established for suppressing the circulating energy among the VSCs.

Figures 4A， 4B and 4C illustrate the block diagrams of the control system according to figure 3. As shown in figures 4A， 4B and 4C， the control system 105 takes the measured value for line current i_L， measured value for injected voltage u_inj， and the value for the measured DC voltage u_{DC_a}， u_{DC_b} ... u_{DC_n}， a predetermined value for the DC voltage reference for the master u_{DC_a_ref} and the reference reactance X_SSSC， ref that the converter should produce as the input to calculate and provide the alternating voltage reference u_{AC_a_ref}， u_{AC_b_ref} ... u_{AC_n_ref} for VSCs 100a， 100b ... 100n. The alternating voltage reference u_{AC_a_ref}， u_{AC_b_ref} ... u_{AC_n_ref} is sent to a PWM block PWMa， PWMb ... PWMn to generate gate signals for the

VSCs

100a， 100b ... 100n. There are two control objectives. The first objective is to control the effective reactance to a pre-set reference value. The second control objective is to control the dc side voltage to a reference value.

Control of effective reactance

As shown in figure 4A， a single phase phasor estimation (P.E.) block and a phase locked loop (PLL) are employed to work on the AC transmission line current i_L such that the current phasor aligns with the d axis in the dq frame. The phase current is assumed to contain a dc offset component

and a sinusoidal component

as shown below：

The single phase P. E. is utilized to obtain both the phasor component

and the offset component. The magnitude of the phasor component is then calculated as

The phasor of the injected voltage u_inj is also estimated using the same method and the angle from the PLL. The q component of the injected voltage divided by the magnitude of the current phasor gives the effective reactance X_SSSC of the SSSC in this single phase. The equivalent reactance is compared with its reference value X_SSSC， ref. The error is passed through a PI controller. The output of the PI controller gives the reference of the q component of the S S S C voltage u′_q， ref.

Control of DC voltage of the VSCs

In controlling the DC voltage of the

VSC

100a， 100b ... 100n， the energy stored in the

capacitor

104a， 104b ... 104n is controlled instead of the DC voltage itself. The DC voltage control uses the master-slave control structure. VSC 100a is the master unit and the other VSCs 100b ... 100n are the slave.

As shown in figure 4B， concerning the master control of VSC 100a， its capacitor energy is controlled by a PI controller. The control system 105 output gives the d component of the VSC voltage u′_{d， ref_a}. The reference of the d and q VSC voltage component are limited by the present DC voltage u_{DC_a}. The limited references are then transformed into αβ frame using the angle from the PLL. The real part (α component) is taken as the sinusoidal phase voltage and sent to the PWMa to generate gate signals for the power semiconductor modules of VSC 100a.

As shown in figure 4C， for the slave 100b ... 100n， a value for filtered measured DC voltage u′_{DDC_a} of the VSC 100a (the master) is taken as the reference for the slave control. For each of the slaves， for example VSC 100b， the value for measured DC voltage u_{DC_b} is compared with its own reference u′_{DC_a} in term of the capacitor energy. The error is delivered to a second PI controller. Depending on the compensation mode (capacitive or inductive) ， the sign will be adjusted. The output from the second PI controller will be added to the output u′_{d，ref_a} from the PI controller of the master controller. The sum， together with the reactive voltage reference u′_q， ref from the reactance controller， is passed to the limitation block to limit the reference according to the present DC voltage. The limited references are then transformed into αβ frame using the angle from the PLL. The real part (α component) is taken as the sinusoidal phase voltage and sent to the PWMb for generation of gate signals. Each of the

VSCs

100a， 100b ... 100n is modulated by pulse with modulation (PWM) . For the converter with effective operating frequency within the range of few hundreds hertz， passive filtering is not very effective. It is because from the passive filtering aspect， the switching frequency is close to the fundamental frequency (50Hz /60Hz) . Therefore， the switching component and its harmonics are difficult to be attenuated by passive filter due to the finite attenuation ability. Moreover， the physical size and cost of the filter increase accordingly with the current and voltage rating. Output voltage and current ripples reduction can be achieved by phase shifting the switching pattern between the VSCs. An appropriate angle of the phase shift can create the most significant ripple suppression effect. The size of the filter can be shrunk； meanwhile high quality of the output voltage and current waveforms can be obtained.

In order to suppress the output voltage harmonics effectively in the paralleled converter configurations， the proposed method is to phase shift the carrier signals between the VSCs by an appropriate angle. In particular， the power semiconductor modules of each VSCs 100a， 100b ... 100n changes its conducting state following the gate signals modulated by PWM signals， and phase shifts are arranged among the carrier signals respectively for the VSCs. Angle of the phase shift in the carrier signals has to be determined coordinately with the modulation method and the number of the VSCs in parallel. The phase difference between the output voltages of the VSCs should be equaled to

where N is the number of VSCs in parallel. The phase difference between the carrier signals is equal to k

f_{eff_L} is the effective operating frequency across the output filter inductor. For instance， k equals to 0.5 or 1 for the modulations scheme with or without frequency doubling effect respectively. Table I shows examples of the phase difference with bipolar and unipolar modulation for each of the H-bridges.

Table I Phase difference examples with bipolar and unipolar modulationfor each of the HBs

The above phase shifting modulation method can be applied directly to the topologies as shown in figure 3.

Application example of the proposed modulation strategy

Using H-bridge VSC with the configuration shown in Figure 3 as an example. The switching pattern of each VSC is following the comparison results between a control signal and carrier signal. In steady state， the control signals of the VSCs are very similar since operating conditions of the converters are almost the same. The top window of Figure 5A shows the output voltage switching waveform of dc/ac VSC 100a before the output filter while the bottom window shows the waveform after the output filter. Figure 5B shows the harmonics spectrum’s magnitude and phase angle information corresponding to the voltage waveform after the output filter.

Figure 6A shows an example of the phase shifted carrier signals of the configuration with 3 VSCs in parallel. The idea is to adjust the phase shift of the switching patterns between the VSCs to 120°. Therefore， the voltage harmonics components can be canceled effectively due to the magnitudes are similar. Figure 6B shows the concept of the aforementioned harmonics cancellation methodology.

Simulation is done with the configuration with 3 H-bridge dc/ac VSCs. Figure 7A and 7B show the normalized magnitude and phase information of the output voltage spectrum before the output filter. It can be seen the magnitude of the spectrums， in figure 8A， of the 3 VSCs are almost the same but the phase plots， as shown in Figure 8B， are different. Table II shows the angle information of the most signification harmonics orders of the 3 VSCs. It can be seen that the difference of the angles between the VSCs is almost 120° or 240° for all the mentioned harmonics orders. It verified the concept shown in Figure 6B. It is due to the fact that the switching patterns， and thus the phase plots， are shifting corresponding with the shift in the carrier signal. The shift is minimal when comparing to the period of the fundamental frequency， therefore the magnitude plots of the converters are almost the same.

Table II Angle information of the most signification harmonics of the 3 VSC units

Figure 8A shows the vector sum of the converters voltage spectrums before the output filter. It can be seen that the magnitude is very small. Figure 8B shows the output voltage waveforms after the output filter， waveform in blue is without the phase shift operation while the waveform in red is with the proposed phase shift operation. With the phase shift operation， the total harmonic distortion (vTHD) is 1.6％instead of 13.3％for the one without the phase shift operation.

Figure 9 shows a more detailed schematic of another embodiment in accordance of figure 2. The embodiment as shown in figure 9 is different from that of figure 3 in that the

VSC

100a， 100b ... 100n uses topology of series connected H-bridge without design of paralleling power semiconductor modules. In particular， each of the

VSCs

100a， 100b ... 100n includes a plurality of VSC cells whose AC outputs are coupled in series forming the AC output of the VSC. As shown in figure 9， VSC 100a includes VSC cells 100a1， 100a2 ... 100am； VSC 100b includes VSC cells 100b1， 100b2 ... 100bm； VSC 100n includes VSC cells 100n1， 100n2 ... 100nm. Each of the

voltage source converters

100a， 100b ... 100n includes a multiple of energy storage element being respectively coupled with its DC inputs in parallel. For example， a multiple of capacitors 104a1， 104a2 ... 104am are coupled to the DC inputs of VSC 100a， a multiple of capacitors 104b1， 104b2 ... 104bm are coupled to the DC inputs of VSC 100b ... a multiple of capacitors 104n1， 104n2 ... 104nm are coupled to the DC inputs of VSC 100n. A DC voltage measuring device 108a measures the value for DC voltage u_{DC_a1}， u_{DC_a2} ... u_{DC_am} across the DC input of the VSC cells of VSC 100a； a DC voltage measuring device 108b measures the value for DC voltage u_{DC_b1}， u_{DC_b2} ... u_{DC_bm} across the DC input of the VSC cells of VSC 100b； and a DC voltage measuring device 108n measures the value for DC voltage u_{DC_n1}， u_{DC_n2} ... u_{DC_nm} across the DC input of the VSC cells of VSC 100n. Preferably， in order to suppress the harmonics of the alternating voltages as generated by the

VSCs

100a， 100b ... 100n， filter circuit 109 can be inserted between the phase A of the transmission line and each VSC. The embodiment of present invention adopts master-slave control algorithm， where one of the

VSCs

100a， 100b ... 100n is selected as the master and the others are selected as slave； for example VSC 100a as master

and VSC 100b ... 100n as slave.

The control system 105 controls the VSC cells 100a1， 100a2 ... 100am of the VSC 100a (master VSC) in consideration of a predetermined master DC voltage reference u_{DC_a_ref} and values for the measured DC voltages across the DC input of the VSC cells of the master u_{DC_a1}， u_{DC_a2} ... u_{DC_am}. Taking VSC cell 100a1 as an example， it is controlled in consideration of the predetermined master DC voltage reference u_{DC_a_ref} and values for the measured DC voltages across the DC input of the VSC cells of the master u_{DC_a1}， u_{DC_a2} ... u_{DC_am}.

The control system 105 further controls a first VSC cell 100b1 ... 100n1 of the slave 100b ... 100n in consideration of an average value for the filtered measured DC voltages of the master u_{DC_a1}， u_{DC_a2} ... u_{DC_am} and a value for the measured DC voltage at the DC input of the first VSC cell of the slave u_{DC_b1} ... u_{DC_n1}. Taking the first VSC cell 100b1 as an example， it is controlled in consideration of the average value for the filtered measured DC voltages of the master u′_{DC_a1}， u′_{DC_a2} ... u′_{DC_am} and the value for the measured DC voltage at the DC input of the first VSC cell of the slave u_{DC_b1}.

Still further， the control system 105 controls a second VSC cell of the slave 100b2 ... 100bm， ... ， 100n2 ... 100nm of the slave 100b ... 100n in consideration of a value for the filtered measured DC voltage of the first VSC cell of the same VSC u′_{DC_b1} ... u′_{DC_n1} as reference and a value for the measured DC voltage at the DC input of the second VSC cell of the slave u_{DC_b2} ... u_{DC_bm}， ... ， u_{DC_n2} ... u_{DC_nm}. Taking VSC cell 100b2 as an example， it is controlled in consideration of the value for the filtered measured DC voltage of the first VSC cell of the same VSC u′_{DC_b1} as reference and a value for the measured DC voltage at the DC input of the second VSC cell of the slave u_{DC_b2}.

Due to similar reason as presented for figure 3， it is helpful for saving the mounting space， efforts on their adjustment and cost.

Figures 10A， 10B， 10C and 10D illustrates the block diagram of the control system according to figure 9. The embodiment according to figure 10A uses the same control algorithm of effective reactance control as that used for the embodiment according to figure 4. In order to avoid redundancy， it is not repeated here.

The control of the master VSC cell 100a1， 100a2 ... 100am shown in Figure 10B uses the same structure as that for the master VSC as shown in figure 4B. Each of the m H-bridges in the master VSC 100a controls its own DC voltage. The output from the PI controller is u′_{dref_aj} for the j^th H-bridge of the master 100a (j＝1 ... m) .

For the other parallel cells， a control structure shown in figures 10C and 10D are utilized.

Figure 10C is for the first H-bridge 100il in the slave VSC 100i (i＝b， ... n) . The reference value is the average of the filtered DC voltages of all the m H-bridges 100a1， 100a2 ... 100am in the master 100a， i.e.，

The measured DC voltage u_{DC_i1}of the first H-bridgel00il in the VSC 100i is compared with u_{dc， ref_i1} in term of the capacitor energy. The error is delivered to a second PI controller. Depending on the compensation mode (capacitive or inductive) ， the sign will be adjusted. The output from the second PI controller will be added to the output u′_{d， ref_P1}， which is the average of the m outputs from the m PI controllers of the master controller， i.e.，

The sum， together with the reactive voltage reference u′_d， ref from the reactance controller， is passed to the limitation block to limit the reference according to the present DC voltage. The limited references are then transformed into αβ frame using the angle from the PLL. The real part (α component) is taken as the sinusoidal phase voltage and sent to the PWM block for generation of gate signals.

Figure 10D is for the j^th HB in the VSC cell 100ij (i＝b ... n， j＝2 ... m) . The reference value is the filtered DC voltages u′_{DC_i1} of the first H-bridge in the same VSC 100i.

The measured DC voltage u_{DC_ij} of the jth H-bridge 100ij in the i^th VSC 100i is compared with u′_{DC_i1}in term of the capacitor energy. The error is delivered to a third PI controller. The output from the third PI controller will be added to the output u′_{d， ref_i1} ， which is the output from the second PI controller of the first HB.

The sum， together with the reactive voltage reference u′_q， ref from the reactance controller， is passed to the limitation block to limit the reference according to the present dc voltage. The limited references are then transformed into αβ frame using the angle from the PLL. The real part (α component) is taken as the sinusoidal phase voltage and sent to the PWM block for generation of gate signals.

The third and the second PI controller may share the same controller parameters.

For the topology shown in figure 9， there are multiple series connected H-bridges in each of the parallel VSCs. Further phase shifting can be applied to the series connected H-bridges in order to obtain even better output voltage quality. The phase shifting angle can be determined in a similar way as described above. Cell phase shifts are arranged among carries signals respectively for the plurality of VSC cells of the

VSC

100a， 100b ... 100n.

Though the present invention has been described on the basis of some preferred embodiments， those skilled in the art should appreciate that those embodiments should by no way limit the scope of the present invention. Without departing from the spirit and concept of the present invention， any variations and modifications to the embodiments should be within the apprehension of those with ordinary knowledge and skills in the art， and therefore fall in the scope of the present invention which is defined by the accompanied claims.

Claims

A transformer-less static synchronous series compensator for an AC electrical power transmission system having a transmission line carrying an AC current， including：

a multiple of voltage source converters， each of which having DC input and AC output and being configured to generate an alternating voltage with controllable magnitude and controllable phase angle across the AC output；

wherein：

the AC outputs of the multiple of voltage source converters are configured for parallel-injection of the generated alternating voltages into a phase of the transmission line.
The transformer-less static synchronous series compensator according to claim 1， further includes：

an AC measuring device， being configured to measure a value for alternating line current flowing through the phase of the transmission line；

an alternating voltage measuring device， being configured to measure a value for the alternating voltage generated by the multiple of voltage source converters and injected into the phase of the transmission line； and

a control system， being configured to control each of the multiple of voltage source converters to generate the alternating voltage across its AC output in consideration of the measured value for the alternating line current， the measured value for the injected alternating voltage and a predetermined reference value for effective impedance.
The transformer-less static synchronous series compensator according to claim 2， wherein：

each of the voltage source converters includes at least one energy storage element being respectively coupled with its at least one DC input in parallel and at least one DC voltage measuring device being configured to respectively measure a value for DC voltage across its at least one DC input； and

the control system is further configured to：

control one of the multiple of voltage source converters as master in consideration of a predetermined master DC voltage reference and the measured value for the DC voltage across the DC input of the master； and

control the other voltage source converter as slave in consideration of a filtered measured value for the DC voltage across the DC input of the master voltage source converter as slave DC voltage reference and the measured value for the DC voltage across the at least one DC input of the slave.
The transformer-less static synchronous series compensator according to any of the preceding claims， wherein：

the multiple of voltage source converters are configured to be modulated by PMW； and phase shifts are arranged among carrier signals respectively for the multiple of voltage source converters.
The transformer-less static synchronous series compensator according to claim 4， wherein：

the phase shift amounts to

N is the number of the voltage source converters coupled in parallel， f_c is frequency of the carrier signal， f_{eff_L} is effective operating frequency across inductor of the voltage source converter.
The transformer-less static synchronous series compensator according to any of the preceding claims， wherein：

each of the multiple of voltage source converters includes one energy storage element， one DC input， and one DC voltage measuring device.
The transformer-less static synchronous series compensator according to claim 3， 4 or 5，wherein：

each of the multiple of voltage source converters includes a plurality of voltage source converter cells whose AC outputs are coupled in series forming the AC output of the voltage source converter； and

each of the voltage converter cells includes the energy storage element being coupled with its DC input in parallel and the DC voltage measuring device being configured to measure a value for DC voltage across its DC input.
The transformer-less static synchronous series compensator according to claim 7， wherein：

the control of the master includes control of each of its voltage source converter cells in consideration of the predetermined master DC voltage reference and values for the measured DC voltages across the DC input of the voltage source converter cells of the master； and

the control of the other voltage source converter as slave includes a first voltage source converter cell of the slave is controlled in consideration of an average value for the filtered measured DC voltages of the master as reference and a value for the measured DC voltage at the DC input of the first voltage source converter cell of the slave and at least one second voltage source converter cell of the slave is controlled in consideration of a value for the filtered measured DC voltage of the first voltage source converter cell of the slave as reference and a value for the measured DC voltage at the DC input of the second voltage source converter cell of the slave.
The transformer-less static synchronous series compensator according to claim 8， wherein：

cell phase shifts are arranged among carries signals respectively for the plurality of voltage source converter cells of the voltage source converter.
A method for compensating an impedance of a phase of a transmission line of an AC electrical power transmission system， including：

(a) generating a multiple of alternating voltages each with controllable magnitude and controllable phase angle in consideration of measured value for alternating line current through the phase of the transmission line， measured value for alternating voltage injected into the phase of the transmission line and a predetermined reference value for effective impedance； and

(b) injecting the generated multiple of alternating voltages in parallel into the phase of the transmission line so as to compensate its impedance.
The method according to claim 10， wherein：

the alternating voltage generation step (a) includes：

(al) generating one of the multiple of alternating voltages by a master voltage source converter in consideration of a predetermined master DC voltage reference and measured value for DC voltage of the master； and

(a2) generating the other of the multiple of alternating voltages by a slave voltage source converter in consideration of a filtered measured value for DC voltage of the master voltage source converter as slave DC voltage reference and measured value for DC voltage of the slave.
The method according to claim 11， wherein：

the generation of the alternating voltage in step (al) includes generating a plurality of alternating voltages cascaded in series by a plurality of voltage source converter cells of the master in consideration of the predetermined master DC voltage reference and a value for the measured DC voltage of the voltage source converter cell of the master； and

the generation of the other alternating voltage in step (a2) includes generating a first alternating voltage and at least one second alternating voltage cascaded in series， wherein the first alternating voltage is generated by a first voltage source converter cell of the slave in consideration of an average value for the filtered measured DC voltages of the master as reference and a value for the measured DC voltage of the first voltage source converter cell， and the second alternating voltage is generated by a second voltage source converter of the slave in consideration of a value for the filtered measured DC voltage of the first voltage source converter cell as reference and a value for the measured DC voltage of the second voltage source converter cell.