WO2017025216A1

WO2017025216A1 - Dc-dc converter

Info

Publication number: WO2017025216A1
Application number: PCT/EP2016/063105
Authority: WO
Inventors: Lisa Maier
Original assignee: Robert Bosch Gmbh
Priority date: 2015-08-12
Filing date: 2016-06-09
Publication date: 2017-02-16
Also published as: EP3335306A1; CN107912079A; DE102015215354A1

Abstract

A DC-DC converter (10) and a method for converting a DC voltage are disclosed. The DC-DC converter (10) comprises a number of switches (16, 18) and a temporary storage device (28); an additional switch (34) is mounted in parallel to the intermediate storage device (28) in such a way as to be able to block in both directions.

Description

Description title

DC converter

The invention relates to a DC-DC converter and a method for converting a DC voltage, in particular with a

DC-DC converter of the type described.

State of the art

DC-DC converters, also referred to as DC / DC converters, are electrical circuits that convert a DC voltage to a DC voltage having a higher, lower or inverted voltage level. These are used, for example, in electric vehicles to convert an electrical voltage of a vehicle battery in voltages suitable for individual consumers.

A distinction is made between boost converters that convert a voltage to a higher voltage, also referred to as a boost converter, and down converters, which convert a voltage to a lower voltage, also referred to as a buck converter. Buck and boost converters refer to converters that can perform both down-conversion and up-conversion.

New components for automotive applications, especially for hybrid electric vehicles, have been introduced in recent years to integrate new systems designed to increase performance and efficiency. The main objectives are the

Energy saving and reduction of pollutant emissions, especially C0 ₂ reduction. This was a new embedded supply for a Voltage of 48 V presented to support the conventional 12 V battery and to enable regenerative braking with high performance. One then speaks of multi-voltage networks, in this case of a two-voltage network. The energy transfer between the two networks or networks in this two-voltage network can, for example, by a

bidirectional DC-DC converter are possible.

Steven Keeping, Contributed by Hearst Electronic Products, Aug. 5, 2014, provides a control circuit for a "zero-voltage switching and its importance to voltage regulation" publication

Down DC voltage converter that allows switching with switches without voltage drop across the switch. In this

DC-DC converter is an inductance provided as a buffer to which a simple switch is connected in parallel.

Disclosure of the invention

Against this background, a DC-DC converter with the features of claim 1 and a method according to claim 6 are presented.

Embodiments emerge from the dependent claims and the

Description.

Thus, a novel topology for a DC-DC converter is presented. This new topology is, for example, on a half-bridge configuration with a further or additional switch or auxiliary switch on the latch, eg. The inductance out, so that the current, for example. The inductance, can run freely when the main switch is not operated. In principle, a buffer can also be provided as a buffer. In the following the invention will be described in connection with an inductance,

in particular a coil, described without this being a limitation thereto.

There are still two modulation schemes, schema A and the

Scheme B introduced to allow ZVS and ZCS switching. ZVS (Zero Voltage Switching) refers to a de-energized switching of switches, such as, for example, switching transistors, in electronic circuits. ZCS (zero-current switching) refers to a currentless switching of switches, such as.

Switching transistors, in electronic circuits. The presented method and the described bidirectional

DC voltage converters are used in particular in multi-voltage systems, in particular in two-voltage systems, of motor vehicles. In these, for example, a 48 V supply and a 12 V supply are used in a network. An application is found, for example, in a regenerative braking.

The presented method has, at least in some of the embodiments, a number of advantages. So only small memory or inductors are required, which significantly reduces the necessary size. Due to the low

Switching losses, an increased power density is achieved. Therefore, the

Size of the components can be reduced. Due to the low losses, the efficiency can be increased. Furthermore, the peak ripple current for partial loads can be minimized.

In addition, operation at constant frequencies is possible because variable frequencies cause difficulty in sizing the components. In addition, various modulation schemes are possible, namely A, B, SCM (Synchronous Conduction Mode) and TCM (Triangular Conduction Mode). The regulation is kept simple. The modulation scheme can be calculated with algebraic equations.

Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawings.

It is understood that the features mentioned above and those yet to be explained below can be used not only in the respectively specified combination but also in other combinations or alone, without departing from the scope of the present invention.

Brief description of the drawings Figure 1 shows an embodiment of the described DC-DC converter.

FIG. 2 shows in a graph a profile of the induction current.

FIG. 3 shows in a graph a profile of the induction current and a profile of the voltage via a switch in the downward mode

Modulatory scheme A.

Figure 4 shows the current flow in the down mode in a first and second period.

Figures 5a to 5c show the current flow in the down mode in a third to eighth period.

FIG. 6 shows in a graph a profile of the induction current and a profile of the voltage via a switch in the up mode

Modulation scheme A.

Figures 7a to 7d show the current flow in the up mode in a first to eighth period.

Figure 8 shows the current flow in the up mode in a ninth and tenth period.

FIG. 9 shows in a graph a profile of the induction current and a profile of the voltage via a switch in the downward mode

Modulation scheme B.

FIG. 10 shows a back-to-back structure of the auxiliary switch. Figure 11 shows the structure of Figure 10. Embodiments of the invention The invention is based on embodiments in the drawings

schematically and will be described below with reference to the

Drawings described in detail.

FIG. 1 shows in a block diagram a DC-DC converter which is denoted overall by the reference numeral 10. This has a first terminal 12, to which the voltage Ui is applied, and a second terminal 14, to which the voltage U ₂ is applied. The two terminals 12 and 14 can each be either as an input or as an output of the bidirectional

DC voltage converter 10 serve. The DC-DC converter shown is set up such that a higher voltage is applied to the first terminal 12 than to the second terminal 14. If the DC-DC converter 10 is therefore operated as a down converter, the first terminal 12 constitutes the input and the second terminal 14 the output. If the DC-DC converter 10 is operated as an up-converter, the first terminal 12 constitutes the output and the second terminal 14 represents the input Thus, DC-DC converter 10 may up-convert in one direction and down-convert in the other direction.

The illustration also shows a first switch Si 16 and a second switch S ₂ 18, each of which is designed as a MOSFET (MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor). These are each shown in the equivalent circuit diagram with body diode 20 or 22 and capacitance C _oss i 24 and C _oss2 26, respectively.

Furthermore, the illustration shows a buffer 28, in this case a coil as inductive storage, and a first capacitor Ci 30 at the first

Anschlußl2 and a second capacitor C ₂ 32 at the second terminal 14. Parallel to the latch 28, a further switch 34 is provided, in this case, the third switch S _3rd This third switch S ₃ 34 includes a first MOSFET 36 and a second MOSFET 38, which are arranged in a back-to-back arrangement to each other, ie, the switch S ₃ can be controlled such that this in both directions, ie bidirectional, locks or blocks. In an embodiment, the two MOSFETs 36 and 38 are controlled independently of each other. It should be noted that the current flowing in the third switch S ₃ 34 is a maximum of about 10 A, where: 10 A = l ₀ : current flowing in the third switch S ₃ 34 in order to keep the ripple losses low , Since the frequency is preferably constant, it is achieved with the third switch S ₃ 34 to achieve a low current ripple for lower output powers, with which the current i _L at -l ₀ can be kept constant. Since, in the case that the inductance switch S ₃ 34 is turned on, the inductor current is only -10 A, the

Power losses caused by this additional switch S ₃ 34, relatively low.

Since the third switch S ₃ 34 is formed as a back-to-back MOSFET configuration, current conduction in both directions is to be avoided when S _{3 is} open due to the intrinsic antiparallel body diodes. The MOSFETs require the same operating voltage as the MOSFETs of the first and second switches, since for U ₂ = 0 V the MOSFET directly connected to the midpoint of the half-bridge will be exposed to the entire voltage Ui as the diode of the adjacent MOSFET would conduct , This back-to-back MOSFET switch structure will be discussed below.

The further figures refer to FIG. 1, in particular to the components of the DC-DC converter 10 shown therein. Reference is made to this by reference numerals.

FIG. 2 shows in a graph a profile of the induction current. In this case, the time is plotted on an abscissa 50 and the induction current i _L (t) is plotted on three ordinates 52. Furthermore, a first line 54, which indicates a current level + l ₀ , and a second line 56, which indicates a current level -l ₀ , registered. The graph shows waveforms of the induction current in buck mode, namely a first trace 60 at power P * 0, a second run 62 at medium power, and a third run 64 at higher power P =

Figure 2 shows the course of the induction current for three different levels of output power. The functional principle of the modulation scheme A in buck mode is described below.

FIG. 3 shows in a graph a first curve 80 which shows the course of the

Induction current i _L (t) reproduces, and a second curve 82, the course of the voltage U _S 2 (t) via the second switch S ₂ reproduces. Furthermore, waveforms reproduce the switch positions, namely a first waveform 84 the position of the first switch Si, a second waveform 86 the position of the second switch S ₂ and a third waveform 88 the position of the third switch S _3rd Value 1 represents a closed switch and value 0 an open switch.

Furthermore, time points are entered, namely a first time to 90, a second time 92, a third time ti 94, a fourth time tr 96, a fifth time t ₂₀ 98, a sixth time t ₂ 100, a seventh time ΐ ₂ · 102 and an eighth time T _p 104.

In addition, the level of the induction current -l ₀ 105, the level of the induction current + l ₀ 106, the level of the voltage U ₂ 107 and the level of the voltage Ui 108 are entered.

FIG. 4 shows, in the bidirectional DC-DC converter 10 with three switches from FIG. 1, the current flow in the downwards mode, wherein the

current-carrying lines and components with solid lines and the non-current-carrying lines and components are shown dotted.

In a first representation 110, the time period to- <t <ti is shown, a second representation 112 shows the period ti <t <tr.

FIGS. 5a to 5c show a representation corresponding to FIG. 4, in which six periods are reproduced. A first representation 120 shows the period tr <t <t ₂₀ , a second representation 122 shows the period t ₂₀ <t <t ₂ , a third representation 124 shows the period t ₂ <t <ΐ ₂ ·, a fourth representation 126 and a fifth representation 128 shows the period t ₂ '<t <T _p , a sixth

Representation 130 shows the time period to <t <.

The individual time intervals are discussed in detail below:

1st time interval before to

Prior to time to, switch S _{3 is} closed (plot 128), allowing the induction current to flow freely in its own closed path. The only resistor to which this current is exposed is the internal resistance of the inductor L and the resistor Rd _S ( ₀ n) of the back-to-back MOSFETs forming the switch S ₃ . FIG. 3 shows the ideal case in which the current remains constant at -l ₀ until S _{3 is} opened. In the real case, the current will slowly drop to zero due to the various resistances through this path. S ₃ will be open at a time prior to ti, with sufficient time for the capacitances Cossi = Coss and C _0S s2 = Coss to discharge to zero or charge Ui to ensure ZVS and ZCS of the switch Si. This transition can be seen in Chart 130.

2. Time interval to <t _ff

If S _{3 has been} turned off and the MOSFET output _capacitance has finished exchanging its charge, the upper diode will begin to conduct as it is forward _biased , C _0SS 2 and hence the anode of the diode has reached the input voltage Ui , During this period, before the induction current reaches zero and begins to flow in the positive direction, the upper switch Si may be turned on in ZVS and ZCS conditions.

3. Time interval <t

Once Si is on, the current can flow through it and rise to the peak current of the graph of FIG. The voltage across the inductor at this time is Ui - U ₂ . 4. Time interval ti <t

In this time interval, the upper switch is turned off, followed by a resonance phase. The upper capacity of the switch Si starts charging and the lower one discharging. When the lower capacitor C _0SS 2 is completely discharged, its parallel diode starts to conduct (display 120), so that a similar situation arises as in the second time interval. During this time interval, diode D ₂ conducts. Therefore, it is best to make this interval as short as possible to avoid unnecessary power losses across the diode. However, it should be ensured that the switch Si is completely turned off before S _{2 is} turned on.

5. Time interval tr <t ₂₀

The switch S ₂ now conducts a current that will drop to zero and the inductance L discharges via C ₂ . The voltage across the inductor is now -U ₂ (plot 120).

6. Time interval t ₂ o ^ t ₂ >

Once the induction current reaches zero since the switch S ₂ remains on, it will continue to flow in the opposite direction (Figure 122), resulting in negative values. As soon as it reaches the desired -l ₀ , the switch S ₂ switches off at the time t ₂ . When this happens, another resonant _phase follows, in which the capacitance C _0SS 2 begins to charge ( _plot 124). When this is left charging, its voltage can rise to Ui. At this moment, the diode D-ι would take over the power. However, since S _{3 is turned on} during this phase, the ideal time would be when C _0SS 2 reaches the voltage U _CO ss, 2 = U ₂ , considering that on the other hand accumulated over- _charge would flow to C _0S s2 via switch S ₃ which induces current spikes and therefore

Circuit losses caused by the internal resistance of S ₃ . The worst case would occur in the event that C _0SS 2 had reached voltage Ui before S ₃ is on. The ZVS condition is hereby achieved for S ₃ (plot 126), which shows the moment in which S _{3 is} turned on, while the capacitance bridge oscillates with the inductance L. The internal capacity of S ₃ will also charge and discharge depending on the condition in which the converter is located.

7. Time interval ΐ ₂ · ^ T _P

In this phase, the induction current is kept substantially constant by the switch S ₃ . The duration of this phase continues until the cycle ends. Before Si closes again for a new cycle, the voltage over it would again reach zero. This is achieved between turning off S ₃ and turning on Si, which causes the voltage U _C oss, 2 above the capacitance to continue rising when energy is still stored in the inductor, ie U _c oss, 2 = U ₂ rises to Ui. The opposite happens for Cossi, who is completely unloaded. At this time, the diode starts to conduct, causing the switch Si to turn on under ZVS and ZCS conditions.

Since the current flow in forward mode, the buck mode, is defined as positive, the boost mode function is correspondingly described with a negative current during the phase in which the inductor stores energy from the input voltage U ₂ .

The following describes the principle of operation of the modulation scheme A in boost mode.

FIG. 6 shows, in a graph, a first curve 180, which represents the profile of the induction current i _L (t), and a second curve 182, which reproduces the profile of the voltage U _S 2 (t) via the second switch S ₂ ,

Furthermore, signal curves reproduce the switch positions, namely a first signal curve 184 the position of the first switch Si, a second signal curve 186 the position of the second switch S ₂ and a third signal curve 188 the position of the third switch S ₃ . Position 1 is a closed switch and position 0 is an open switch again.

Furthermore, times are entered, namely a first time to 190, a second time 192, a third time ti 194, a fourth time tr 196, a fifth time t ₂₀ 198, a sixth time t ₂ 200, a seventh time ΐ ₂ · 202, and an eighth time T _p 204.

Also entered are the level of the induction current -l ₀ 205, the level of the induction current + l ₀ 206, the level of the voltage U ₂ 207 and the level of the voltage Ui 208.

The course of the induction current in the boost mode is thus shown in FIG. Similar to the buck mode, where there are three stages in which the energy is first stored in the inductor while S _{2 is} closed, later enabled to flow through Si to the output capacitance Ci and finally constant through the switch S _{3 is} held. The third switch is used in the same way to keep a current i _L low and to avoid losses in the switch Si.

Figure 7 shows in the bidirectional DC-DC converter 10 with three

Switches of Figure 1, the current flow in the up mode, the

FIGS. 7a to 7d show eight time periods, these being:

220: ίο · <ti, 222: ti t _r , 224: t _r <t ₂₀ , 226: t _r <t ₂₀ , 228: t ₂₀ <t ₂ , 230: t ₂ <t _z , 232 and 234: t ₂ . <T _p .

FIG. 8 is a representation corresponding to FIG. 7, where: 240: to <t _ff , 242: to <

The individual periods are described below:

1 . Time interval to <t _ff

Here, the switch S _{3 is} opened and after a resonance oscillation of the output capacitances, the diode D _{2 will} conduct, allowing S ₂ , turn on with ZVS and ZCS for the cycle starting. This can be seen in FIG.

2nd time interval h <

5 ₂ is conductive and the inductance is charged. The voltage across the inductor is -U ₂ . The various phases of the boost mode are shown in FIG. 7 in illustration 200.

3. Time interval ti <t _r

During this transition _phase , the capacitances C _oss i and C _0SS 2 exchange their charges ( _Figure 222). The diode D-ι begins to conduct with it as soon as the voltage Ui is reached via C _0SS 2.

4. Time interval t _r <t ₂

Now, the inductance voltage is Ui-U ₂ , so the current starts to rise and when it reaches zero, it flows in the positive direction and Si is left on until it reaches I ₀ (plot 228).

5. Time interval t ₂ ^ t ₂ >

At this time, resonant oscillation charges C _oss i and discharges C _0SS 2- Even in boost mode, the voltage across C _0SS 2 can only drop until it reaches U ₂ , so that S _{3 can be turned} on at zero voltage. Reference is made to illustrations 230-232.

6. Time interval t ₂ ^ Τ _ρ ·

5 ₃ remains conductive until the end of the period.

The functional principle of modulation scheme B is explained below: Thus, another control method is presented to achieve ZVS and / or ZCS for all switches of the converter. This modulation scheme effectively improves the transition from S ₂ to S ₃ and switching ringing, ie

Oscillation caused by the passage of current from one switch to another is avoided. Compared to the behavior in the 6.

It is not necessary to consider the time interval as in the case of modulation scheme A, that C _0S s2 reaches the voltage U ₂ in buck mode, since the transition occurs naturally here. The current is taken over by the auxiliary switch S ₃ without ringing. The same applies to boost mode (5th time interval t ₂ ^ t ₂ '): the current is taken over without ripple from Si to S ₃ . Complete ZVS and ZCS for all switches theoretically means no switching losses.

The new modulation scheme for the third switch, which separately controls the two MOSFETs Qi 300 and Q ₂ 302 (Figure 10), should be implemented in the following manner. FIG. 9 shows the new control signals in buck mode. The two switches Si and S ₂ are controlled in the same manner as before, however, the MOSFET Qi 300 turns on after S _{2 is turned} on at t _r 298.

FIG. 9 shows, according to FIGS. 3 and 6, in a graph, a first curve 280 which represents the profile of the induction current i _L (t), and a second curve 282 which shows the profile of the voltage Us ₂ (t) via the second switch S ₂ reproduces. Furthermore, waveforms reproduce the switch positions, namely a first waveform 284 the position of the first switch Si, a second waveform 286 the position of the second switch S ₂ , a third waveform 288a the position of the switch Qi 300, and a fourth

Signal curve 288b shows the position of the switch Q ₂ 302. Position 1 indicates a closed switch and position 0 an opened switch.

Furthermore, time points are entered, namely a first time to 290, a second time e 292, a third time ti 294, a fourth time tr 296, a fifth time tr 298 a sixth time t ₂₀ 300, a seventh time t ₂ 302 eighth time t ₂ '304 and a ninth time T _p 306. Also indicated are the level of the induction current -l ₀ 308, the level of the induction current + l ₀ 310, the level of the voltage U ₂ 312 and the level of the voltage Ui 314.

Figure 10 shows a back-to-back structure of the switch S ₃ 34 of Figure 1 in the equivalent circuit diagram. The illustration shows a first switch Qi 300, a second switch Q ₂ 302, a first capacitance 304, a second capacitance 306, a first diode D _Q1 308 and a second diode D _Q2 310. A first point A 312 and a second point B 314 are also designated.

Since at point in time t _r 296 at which S ₂ conducts, point A 312 in FIG. 10 has been pulled down to zero, third switch S ₃ will not conduct yet since diode D _{Q2 is operated} in the reverse direction and Q _{2 is} open. Therefore, Q-1 can be turned on without current load (time t _r 298), and therefore no circuit losses occur. Diode D _Q2 will block voltage U ₂ while S ₂ conducts.

As soon as the induction current -l reaches ₀ and S _{2 is} switched off (time t ₂ 302), the capacitances parallel to the MOSFET become their

Charge transitions begin and U _C oss 2 will begin charging from zero to U ₂ . Once the voltage has reached the output voltage at point A, the voltage will be equal to U ₂ and the diode D _Q2 will be operated in the forward direction, since the current will of course commute to Qi, which was previously turned on, and this will be Q-ι and D _Q2 flow. At this time, the MOSFET Q _{2 may be} turned on (time t ₂ > 304) to reduce conduction losses caused by the free-wheeling diode D _Q2 . Since the antiparallel diode D _{Q2 will} conduct the current, the MOSFET Q _{2 will} also be turned on without current and voltage stress.

This also applies to the boost mode, when the upper switch Si conducts and the induction current decreases, between t and t ₂ in Figure 6, the MOSFET Q ₂ can be switched to Si at any time since its series diode D _Q1 the Voltage Ui - U ₂ will block at this time, ie reverse operation of D _Q i. The MOSFET Q ₂ can therefore be turned on without current load and no current will flow through it as long as Si is turned on. When Si is turned off at time t ₂ , the resonant _{phase of} the capacitance starts and the capacitance C _0SS 2 starts to discharge from Ui to zero. When this process starts, point A in Figure 10 is Ui. Once the voltage in the node reaches U ₂ , the diode D _{Q1 is} forward biased, and since Q _{2 is} already on, the current will begin to flow smoothly through Q ₂ and D _Q1 , since the induction current will, of course, be through the shifter S ₃ will go and produces no vibration. During this phase Q-ι can be switched at any time. Also in this case, ZVS and ZCS are achieved because the antiparallel diode conducts current.

This converter can thus be controlled in such a way that almost no switching losses are recorded.

The switching times can be calculated in such a way that the required power is transmitted and achieved simultaneously for all switches ZVS. The following calculations apply on the condition that all components behave ideally, have no losses and delays, and have constant values.

Some assumptions must be made for the calculation of

Switch-on duration of the switches:

Neglecting the resonance phases t ₀ => t _ff , t-1 => t and t ₂ => t ₂ >,

Neglect of power losses,

constant voltages Ui and U ₂ ,

the minimum current I ₀ is always reached.

In the following calculations, the buck mode is considered in the conventional manner, with the input voltage U _e i _n = U i and the

Output voltage U _aU s = U ₂ .

First, the induction current and the induction voltage in the bucking mode are considered: Input and output voltage: Ui = U _e m (higher voltage); U ₂ = U

(lower voltage)

Assuming that the induction current begins before each new cycle at ii_ (to) = -lo, the induction current function for each switching stage may become:

Now consider the induction current and the induction voltage in boost mode:

Input and output voltage in the range: Ui = U _e m (lower voltage), U2 = Uout (higher voltage)

The voltage across the inductor in boost mode is defined as follows:

u 0 <t <t _l

U _L (t) u (3)

h <t <T _p

Similar to the buck mode, the induction current for the boost mode can be defined as follows:

The maximum power must be transmitted by the input and stored in the inductance until time t1. For the input power P1 applies:

wherein the input current I _avg (avg = Average) is also the current flowing through the switch Si. Based on this equation, the switch-on time of the switch Si can be calculated in buck mode:

The result is a quadratic equation for and since Pi = P ₂ = P holds:

Resolved by this gives:

On the basis of the so-called volt second equation, which takes into account the principle of the volt-second balance, the on-time of S ₂ , namely t _{2, (} can be calculated in a simple manner:

The third equation is obtained by the difference between the period T _p and the switch-on times t- ₁ + t ₂ , _e in = T _p -t _y -t 2, ON (10)

The effective induction current is calculated as follows:

L, rms, BUCK (1 1)

where U1 is the input voltage in buck mode on the high voltage side. The effective induction current is calculated as follows:

in which case the input voltage is determined for the input voltage U ₁ (lower voltage) in boost mode. The average induction current is determined by:

(13)

Figure 1 1 will explain the back-to-back structure of the third switch S _{3 in} more detail.

Figure 1 1 shows the third switch S ₃ 34 of Figure 10, wherein in addition a voltage drop Ui - U ₂ via the first switch Qi 300 is illustrated by an arrow 330.

It should be noted that a single MOSFET can only block the voltage in one direction. To block voltages in both directions, a diode should be placed in the path to one

to allow unidirectional flow of current. When the higher switch conducts Si and a current positively flows into the inductor, the voltage drop Ui-U _{2 is held} by a MOSFET 300 because the diode D would conduct _Q2 310 because its anode voltage Ui is higher than the cathode voltage U ₂ is. The opposite is true when the bottom switch is conducting. During this operation, the voltage at point A 312 is pulled down to zero while the voltage at point B 314 will be positive, namely U ₂ . Therefore, the diode D _{Q1 is operated} in the forward direction and would conduct if the switch Q _{2 were} not used.

Consequently, in order to block the voltage in both directions while allowing a bidirectional current flow, another MOSFET, that is a total of two MOSFETs for S ₃ , is required. In Modulation Scheme A, the two MOSFETs share the signal at the gate terminal and their source terminals are interconnected. In modulation scheme B, the two MOSFETs are controlled separately.

The operating voltage of the back-to-back MOSFETs must correspond to the high-side voltage, because if a MOSFET blocks in one direction, the diode of the MOSFET will conduct in series because it is forward-biased and therefore, the total reverse voltage drop will be applied to a single MOSFET Q, where i = 1, 2. The worst case reverse voltage condition occurs when the output capacitance is not yet charged and therefore the MOSFETs must endure the full maximum voltage (high side voltage), in this case Ui, where Ui> U ₂ .

Claims

claims

1. Bidirectional DC-DC converter (10) with a number of switches (16, 18, 300, 302) and a latch (28), wherein parallel to the latch (28), a further switch (34) is connected, wherein the further switch ( 34) is set up in such a way that it can block bidirectionally.

2. DC-DC converter according to claim 1, wherein the further switch (34) is realized with two back-to-back transistors, which are controlled separately.

3. DC-DC converter according to claim 1 or 2, wherein as

Latch (28) an inductance is used.

4. DC-DC converter according to claim 3, wherein the inductance is a coil.

5. DC-DC converter according to one of claims 1 to 4, a

Half-bridge structure has.

6. A method for converting a DC voltage with a

DC-DC converter (10) of the switches (16, 18, 300, 302) and a

Latch (28), to which a further switch (34) is parallel connected, which is adapted to bidirectionally lock, in particular with a DC-DC converter (10) according to one of claims 1 to 5, wherein in operation the further switch (34 ) is driven.

7. The method of claim 6, wherein the DC-DC converter (10) is operated in a modulation scheme A, in which the further switch (34) is driven with a signal.

8. The method of claim 6, wherein the DC-DC converter (10) is operated in a modulation scheme B, in which the two back-to-back transistors of the further switch (34) are controlled separately and comprise at least two different switching units.

9. The method according to any one of claims 6 to 8, wherein an up-conversion is performed.

10. The method according to any one of claims 6 to 8, wherein a down conversion is performed.