WO2017095331A1

WO2017095331A1 - Voltage reference and self-oscillating amplifier circuit

Info

Publication number: WO2017095331A1
Application number: PCT/SG2016/050585
Authority: WO
Inventors: Joseph Sylvester Chang; Tong GE; Linfei GUO
Original assignee: Nanyang Technological University
Priority date: 2015-12-03
Filing date: 2016-11-30
Publication date: 2017-06-08

Abstract

A voltage reference (200a) is disclosed, which comprises a voltage divider (202) arranged to be coupled to a voltage supply (204); and a filter circuit (206) arranged to be coupled to output of the voltage divider, the filter circuit includes at least one transistor (208) and a capacitive element (210). When in use, the transistor is configured to operate in cut-off mode to enable the filter circuit to function as an RC low-pass filter to attenuate supply noise of the voltage supply, and to enable the filter circuit to generate a reference voltage based on the voltage supply, the reference voltage substantially free of the supply noise.

Description

Voltage Reference and Self-Oscillating Amplifier Circuit

Field

The present invention relates to a voltage reference, and a self-oscillating amplifier circuit.

Background

• Problem 1

Class D amplifiers (CDAs) are becoming ubiquitous, largely due to their higher power efficiencies compared to their linear counterparts. FIG. 1 shows the schematics 100 of a typical CDA. However, a potential drawback of CDAs is their susceptibility to supply noise, which can be qualified and quantified as Power Supply Rejection Ratio (PSRR) and Power Supply Induced Intermodulation Distortion (PS-IMD). Poor PSRR and PS-IMD may result in undesirable audible noise generated at the output stage and is of particular pertinence when the CDAs are integrated in a system-on-chip (SoC), where the power supply used tends to be fairly noisy. To achieve high quality device performance by the SoC, it is thus imperative that both the PSRR and PS-IMD are high, preferably greater than 1 00 dB.

To achieve a high PSRR and PS-IMD, particularly for PSRR to be about 100 dB, it is imperative that the AC ground { V_AC) used is reasonably clean, i.e. the supply noise is highly attenuated in the AC ground. It is also imperative that V_AC is approximately half of the supply voltage, V_DD. This is because similar to many other designs (e.g. linear amplifiers), the range of Voo for CDAs is usually high. For instance, low power CDAs (i.e. 2 W rating) are normally designed to operate at a V_DD of between 2.5 V to 5.5 V. Any deviation of V_AC from 0.5 V_DD will result in reduced dynamic range of the CDA. Preferably, V_AC is to have high supply noise attenuation, and be approximately half V_DD. This can be easily achieved if the V_AC \s generated externally (i.e. off- chip), since a capacitor with large capacitance (e.g. a 1 F capacitor) can be employed. However, this is not the case when V_AC is generated internally (i.e. on-chip). Instead, a bandgap voltage reference (or its variations) has to be used. Although the bandgap voltage reference is virtually supply-noise-free, it is however largely a fixed voltage (independent of V_DD). An alternative is to adopt a voltage divider, which is used to provide an approximately half V_DD, but noise attenuation performance of the voltage divider is poor (particularly when the supply noise frequency is low, e.g. 21 7 Hz).

Other reported methods also include solutions based on a switched capacitor, or a mid-resolution (8-bit) DAC with a counter. Drawbacks of the former method include generating a large voltage droop at the output of the switched capacitor, due to the very low clock rate and presence of leakage current in the switched capacitor (i.e. it is to be noted that this is common in switched capacitor circuits but is usually inconsequential, if the clock rate is reasonably high). The voltage droop can be greater than 1 00 mV, which may result in degraded Total Harmonic Distortion plus Noise (THD+N) or affect the dynamic range of the CDA. On the other hand, drawbacks of the latter method include observing a situation where V_AC = 0.5 V_DD being true only when V_DD increases, but not when V_DD reduces. Specifically, when V_DD increases from 0 V to 5 V (and the circuit operates at V_DD = 5 V thereafter), a V_AC = 2.5 V (i.e. half V_DD) is generated. However, when V_DD reduces from 5 V to 2.5 V (and the circuit operates at V_DD = 2.5 V thereafter), V_AC cannot be adjusted to the desired 1 .25 V (i.e. 0.5 V_DD). unless the counter undergoes a reset, hence requiring further hardware to detect V_DD changes, and etc. Other drawbacks of both methods also include relatively complex hardware, and high power consumption - these problems are due to embodying the voltage reference generator and switched capacitor circuits in the former method, and then embodying the bandgap voltage reference and DAC in the latter method.

• Problem 2

Modulation techniques commonly used in CDAs include Pulse-Width-Modulation (PWM), Sigma-Delta Modulation, Bang-Bang control modulation, and etc. Amongst said modulation techniques, CDAs based on Bang-Bang control modulation (i.e. Bang-Bang control CDAs) are arguably the most advantageous for low-power power-critical applications. This is because Bang-Bang control CDAs have significantly higher power-efficiency (in part due to hardware simplicity), comparable fidelity (as qualified by THD) and higher noise immunity (as qualified by PSRR). Specifically, it was reported in literature that for certain micro-power applications, the power-efficiency of the Bang-Bang control CDAs is a high 53%, whilst that of competing and conventional PWM CDAs is substantially lower at 35%, at the nominal operating condition of Modulation Index, M = 0.15 (i.e. 15dB below the maximum due to the crest factor of audio/speech signal). Furthermore, in said reported design, the THD and PSRR of Bang-Bang Control CDAs are respectively 0.08% and 70 dB, whilst the THD and PSRR of the competing PWM CDAs are respectively 0.09% and 45 dB. In short, Bang-Bang control CDAs are arguably the most power-efficient architecture for low-power power-critical applications, and yet featuring comparable or better fidelity than PWM CDAs.

At this juncture, it is to be highlighted that the reported Bang-Bang control CDAs were configured to use the single-ended, or the 2-state Bridge-Tide-Load (BTL) architecture/topology. A major drawback of the single-ended and 2-state BTL Bang-Bang control CDAs however is that an output low-pass filter is required to filter out high frequency carrier components. Using the output low-pass filter is highly undesirable in this case, as the low-pass filter typically occupies more than 70% of the PCB area and adds 30% further costs, thus consequently undesirably substantially increasing the overall form factor and associated costs of the Bang-Bang control CDAs.

In relation, the schematics 500, 520 of the single-ended and 2-state BTL Bang- Bang control CDAs and their output waveforms 510, 530 are respectively depicted in FIGs. 5a to 5d. Briefly, the single-ended and 2-state BTL Bang-Bang control CDAs each comprises a Bang-Bang controller (realized using a hysteresis comparator), an output stage, an RC feedback network, a low-pass filter and a (resistive) loudspeaker load.

The operation of the single-ended and 2-state BTL Bang-Bang control CDAs is similar: the RC feedback network feeds back the output signal to the Bang-Bang controller. The Bang-Bang controller then controls an error signal ( V_err) between the input signal and output signal (ideally a replica of the input signal for Gain = 1 ), and generates digital-like switching signal(s) by comparing V_err with the hysteresis band. The output stage provides current to drive the loudspeaker load. The low-pass filter is configured to filter the high frequency switching components and to recover the desired output signal at the loudspeaker load. Further, it can be seen from FIGs. 5d and 5d that the respective output switching signals of the single-ended and 2-state BTL Bang-Bang control CDAs are effectively 2-state. Specifically, for the single-ended CDA, the output switching signal, V_SE, alternates between the two supply rails (i.e. V_DD and 0), regardless of the magnitude of the input signal. For the 2-state BTL CDA, the resultant output switching signal, V₂state__P-V₂stat_s n, alternates between V_DD and -V_DD, since two output signals (i.e. V₂state__P and V_2State_n) are always 180° out-of-phase. It is well-established that in 2-state output signals, the carrier components are large, and hence an output low-pass LC filter is thus required to filter these carrier components.

One object of the present invention is therefore to address at least one of the problems of the prior art and/or to provide a choice that is useful in the art. Summary

According to a 1^st aspect, there is provided a voltage reference comprising: a voltage divider arranged to be coupled to a voltage supply; and a filter circuit arranged to be coupled to output of the voltage divider, the filter circuit includes at least one transistor and a capacitive element, wherein in use, the transistor is configured to operate in cut-off mode to enable the filter circuit to function as an RC low-pass filter to attenuate supply noise of the voltage supply, and to enable the filter circuit to generate a reference voltage based on the voltage supply, the reference voltage substantially free of the supply noise. Advantageously, the disclosed voltage reference employs at least one transistor operating in the cut-off mode to realize a resistor with very high resistance (i.e. greater than 10 ΘΩ). Consequently, a large RC constant can be realized to enable the filter circuit to act as an RC low-pass filter, without requiring a large IC/PCB area or incurring high power dissipation.

Preferably, the transistor may be an n-type transistor or a p-type transistor.

Preferably, the capacitive element may include being in a series circuit arrangement with the transistor. Preferably, the voltage reference may further include a buffer circuit coupled to the filter circuit to receive and store the reference voltage from the filter circuit.

Preferably, the buffer circuit may be an amplifier configured in negative feedback arrangement.

Preferably, the at least one transistor may include at least first and second transistors in a parallel circuit arrangement. Alternatively, the at least first transistor may include a plurality of transistors in a series circuit arrangement.

Similarly, the at least second transistor may preferably include a plurality of transistors in a series circuit arrangement.

According to a 2^nd aspect, there is provided a method of generating a reference voltage using a voltage reference, which includes a voltage divider arranged to be coupled to a voltage supply, and a filter circuit arranged to be coupled to output of the voltage divider, the filter circuit includes at least one transistor and a capacitive element. The method comprises: operating the transistor in cut-off mode to enable the filter circuit to function as an RC low-pass filter to attenuate supply noise of the voltage supply; and generating the reference voltage by the filter circuit based on the voltage supply, the reference voltage substantially free of the supply noise.

According to a 3^rd aspect, there is provided a self-oscillating amplifier circuit comprising: a hysteresis controller for receiving a pair of input signals, the controller includes first and second hysteresis comparators to generate first and second output signals; a synchronization module configured to synchronize high frequency carrier components of the first and second hysteresis comparators by providing the first and second output signals as feedbacks to the second and first hysteresis comparators respectively; and first and second output stages respectively coupled to the first and second hysteresis comparators, and configured to generate third and fourth output signals based on the first and second output signals to provide a resultant switching signal for driving a load, wherein the resultant switching signal alternates between 3-states in dependence of the input signals.

Beneficially, the proposed amplifier circuit does not require usage of an output low-pass filter, because ability to generate the 3-state switching signal means the signal itself has significantly reduced carrier components, thereby eliminating need to include the output low-pass filter.

Preferably, the first and second hysteresis comparators may be configured in a parallel arrangement.

Preferably, the amplifier circuit may further comprise first and second feedback modules arranged to respectively feedback the third and fourth output signals. Specifically, each feedback module may be in an RC network configuration.

Preferably, the third and fourth output signals may include in-phase high frequency components, and out-of-phase low frequency components. Preferably, the synchronization module may comprise a pair of resistors in parallel circuit arrangement.

Preferably, each output stage may include a driver module coupled to an output module, which includes a pair of transistors.

Preferably, the 3-states may include V_DD, 0 V, and -V_DD.

According to a 4^th aspect, there is provided a method of generating a resultant switching signal that alternates between 3-states using a self-oscillating amplifier circuit, which includes a hysteresis controller having first and second hysteresis comparators, a synchronization module, and first and second output stages respectively coupled to the first and second hysteresis comparators. The method comprises: receiving a pair of input signals by the hysteresis controller to enable the first and second hysteresis comparators to generate first and second output signals; providing the first and second output signals as feedbacks by the synchronization module to the second and first hysteresis comparators respectively to synchronize high frequency carrier components of the first and second hysteresis comparators; and generating third and fourth output signals by the first and second output stages based on the first and second output signals to provide the resultant switching signal for driving a load, wherein the resultant switching signal alternates between the 3-states in dependence of the input signals.

It should be apparent that features relating to one aspect of the invention may also be applicable to the other aspects of the invention.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. Brief Description of the Drawings

Embodiments of the invention are disclosed hereinafter with reference to the accompanying drawings, in which:

FIG. 1 shows the schematics of a typical Class D amplifier (CDA), according to prior art;

FIG. 2a shows the schematics of a voltage reference, according to a first embodiment;

FIGs. 2b to 2f show the respective schematics of voltage references, according to variant embodiments;

FIGs. 3a to 3b show the respective schematics of voltage references, according to further variant embodiments;

FIG. 4 depicts a method of generating a reference voltage using the voltage reference of any of FIGs. 2a-2f, or FIGs. 3a to 3b;

FIG. 5a shows the schematics of a single-ended Bang-Bang control CDA, according to prior art, and FIG. 5b shows output waveforms generated by the single-ended Bang-Bang control CDA;

FIG. 5c is a schematic diagram of a 2-state Bridge-Tied-Load (BTL) Bang-Bang control CDA, according to prior art, and FIG. 5d shows output waveforms generated by the 2-state BTL Bang-Bang control CDA;

FIG. 6 is a block diagram of a self-oscillating amplifier circuit, according to a different embodiment; FIG. 7a shows the schematics of the amplifier circuit of FIG. 6, and FIG. 7b shows output waveforms generated by the said amplifier circuit;

FIG. 8 shows waveforms generated in the upper branch of a hysteresis controller used in the amplifier circuit of FIG. 6;

FIG. 9 depicts a method of generating a resultant switching signal that alternates between 3-states using the amplifier circuit of FIG. 6;

FIG. 10 is a table showing different sets of circuit parameters adoptable for components in the self-oscillating amplifier circuit of FIG. 6 for purpose of conducting evaluations;

FIG. 1 1 shows output signal waveform ( V_ouLp-V_ouLn) corresponding to the resultant switching signal generated; and

FIG. 12 shows results of Total Harmonic Distortion (THD) versus modulation index, M, based upon evaluation of the amplifier circuit of FIG. 6 using the different circuit parameters set out in the table of FIG. 10.

Detailed Description of Preferred Embodiments

• A Voltage Reference

FIG. 2a is a schematic diagram of a first voltage reference 200a, according to a first embodiment. The first voltage reference 200a comprises a voltage divider 202 arranged to be coupled to a voltage supply 204; and a filter circuit 206 arranged to be coupled to output of the voltage divider 202, the filter circuit 206 includes at least one transistor (Λ^ or M₂) 208 and a capacitive element (Ci ) (e.g. a capacitor, and referred to as such hereinafter) 210. When in use, the transistor 208 is configured to operate in cut-off mode to enable the filter circuit 206 to function as an RC low-pass filter to attenuate supply noise of the voltage supply 204, and to enable the filter circuit 206 to generate a reference voltage based on the voltage supply 204, in which the reference voltage is consequently substantially free of the supply noise. The voltage divider 202 comprises two resistors 202a, 202b (R_ref) arranged in circuit series, and the transistor 208 is a p-type transistor. Then, the capacitor 210 is in a series circuit arrangement with the transistor 208. Also, the first voltage reference 200a optionally includes a buffer circuit 212 coupled to the filter circuit 206 to receive and store the reference voltage from the filter circuit 206. In this case, the buffer circuit 212 is an amplifier configured in negative feedback arrangement. Also, output voltage generated by the buffer circuit 212 is labelled as V_AC. To explain, the transistor 208 is switched on (i.e. in active mode) when a supply voltage ( V_DD) from the voltage supply 204 increases, e.g. from 0 V to 5 V. The transistor 208 then charges the capacitor 21 0, and so (i .e. the voltage across the capacitor 210) and V_AC are also increased correspondingly. When Vi reaches about 0.5 V_DD, the transistor 208 turns off (i.e. in cut-off mode) and then functions as a resistor with an effective large resistance (R_eff) greater than 10 ΘΩ. Hence, the transistor 208 and capacitor 210 work in tandem to function as an RC low-pass filter to attenuate the supply noise. Depending on configured values of the transistor 208, voltage supply 204 and capacitor 210, the supply noise attenuation at 21 7 Hz may be greater than 40 dB.

When the supply voltage is reduced from 5 V to 2.5 V (where the first voltage reference 200a operates at 2.5 V thereafter), the transistor 208 remains in the cut-off mode, and the capacitor 210 then discharges at a very low current (e.g. tens of pA or even lower). Hence the first voltage reference 200a takes a longer time (i.e. about 1 s) to reach steady state operation (whose output V_AC is about 1 .25 V).

FIG. 2b shows schematics of a second voltage reference 200b, according to a second embod iment, and it is to be appreciated that the second voltage reference 200b is entirely similar in configuration to the first voltage reference 200a, except that an n-type transistor is now used as the transistor 208.

FIGs. 2c and 2d show respective schematics of third and fourth voltage references 200c, 200d, according to third and fourth embodiments. The third voltage reference 200c is based on the first voltage reference 200a, except that the p-type transistor is now configured differently as opposed to that in FIG. 2a. Specifically, in FIG. 2a, the source terminal of the p-type transistor is connected to the voltage divider 204, and the gate and drain terminals are connected to the capacitor 210. But in FIG. 2c, the gate and drain terminals of p-type transistor M₂ are connected to the voltage divider 204, whereas the source terminal of M₂ is connected to the capacitor 210. Then, the fourth voltage reference 200d is based on the second voltage reference 200b of FIG. 2b, except that the n-type transistor is now configured differently as opposed to that in FIG. 2b. More specifically, in FIG. 2b, the gate and drain terminals of n- type transistor Mi are connected to the voltage divider 204, while the source terminal of is connected to the capacitor 210. On the other hand, in FIG. 2d, the source terminal of the n-type transistor M₂ is connected to the voltage divider 204, whereas the gate and drain terminals are connected to the capacitor 210. The operations of the third and fourth voltage references 200c, 200d are largely similar to the first and second voltage references 200a, 200b, except that the transistor 208 is in the cut-off region when the supply voltage increases (e.g. from V_DD = 0 V to V_DD = 5 V and the third and fourth voltage references 200c, 200d respectively operates at V_DD = 5 V thereafter) and the transistor 208 is in the above-threshold region when the supply voltage decreases (e.g. from V_DD = 5 V to V_DD = 2.5 V and the third and fourth voltage references 200c, 200d respectively operates at V_DD = 2.5 V thereafter). As a result, the third and fourth voltage references 200c, 200d respectively take a longer time to charge the capacitor 21 0 for V† to reach about 0.5V_Do, but takes a shorter time (e.g. a few με) to reach steady state operation when the supply voltage decreases. It is to be appreciated that when the third or fourth voltage reference 200c, 200d approaches steady state (i.e. when the voltage from the voltage divider 204 is 0.5 VDD and the capacitor 210 is 0.5 V_DD ± the threshold voltage of the transistor 208), the transistor 208 electrically switches to then operate in the cut-off region, hence functioning as a large resistor.

FIGs. 2e and 2f show respective schematics of fifth and sixth voltage references 200e, 200f, according to fifth and sixth embodiments. The fifth voltage reference 200e is based on the first voltage reference 200a and the third voltage reference 200c, except that two p-type transistors in parallel circuit arrangement now replace the single p-type transistor used in FIG . 2a and FIG. 2c. This configuration ensures that the fifth voltage reference 200e takes a shorter time to reach steady state operation, when the supply voltage increases and decreases. Similarly, the sixth voltage reference 200f is based on the second voltage reference 200b and the fourth voltage reference 200d, except that two n- type transistors in parallel circuit arrangement now replace the single n-type transistor used as shown in FIG. 2b and FIG.2d.

Separately, it is to be highlighted that one potential drawback of the voltage references 200a-200f in FIGs. 2a to 2f is that the disclosed voltage references 200a-200f are able to provide high supply noise attenuation, only when the supply noise on the supply voltage is smaller than 2x of the threshold voltage of the transistor(s) 208. When the supply noise is larger than 2x of the threshold voltage, the transistor(s) 208 will then turn on, and hence the supply noise will undesirably appear at V_AC. This is usually inconsequential for designs intended for low power applications, as the supply noise is usually smaller than 200 mV and is substantially lower than 2x of the threshold voltage (e.g. 0.5 V) of the transistor(s) 208. But in cases when the supply noise on the supply voltage is potentially higher than 2x of the threshold voltage, two or more transistors can beneficially be connected in circuit series to provide increased supply variation tolerance, as depicted in seventh and eighth voltage references 300, 350, based on seventh and eighth embodiments (see FIGs. 3a and 3b). Simply, the seventh voltage reference 300 only differs from the first voltage reference 200a, in that the two separate rows of p-type transistors, each row in series circuit arrangement, are adopted as a configuration for the transistor 208, and more specifically, the two rows of p-type transistors are in parallel circuit arrangement to each other. Then, the eighth voltage reference 350 is largely similar to the seventh voltage reference 300, except that n-type transistors replace all the p- type transistors. In this fashion, the supply noise can be tolerated up to 2nx of the threshold voltage, where n is the number of (p-type/n-type) transistors within the series circuit arrangement of each row.

Referring to FIG. 4, there is disclosed a method 400 of generating the reference voltage, using the voltage reference 200a-200f, 300, 350, in which the method 400 comprises: at step 402, operating the transistor(s) 208 in cut-off mode to enable the filter circuit 206 to function as an RC low-pass filter to attenuate supply noise of the voltage supply 204; and at step 404, generating the reference voltage by the filter circuit 206 based on the voltage supply, in which the reference voltage is substantially free of the supply noise.

Hence, the proposed voltage references 200a-200f, 300, 350 address drawbacks of conventional voltage references, and have the following advantages: (i). simple hardware, (ii). negligible power dissipation, (iii). no voltage droop, and (iv). ability to track the supply voltage, when the supply voltage increases or decreases. In summary, the proposed voltage references 200a-200f, 300, 350 employ at least one transistor 208 (or a plurality of transistors) operating in the cut-off mode to realize a resistor with very high resistance (i.e. greater than 10 ΘΩ). As a result, a large RC constant (and hence a low cut-off frequency of smaller than 10 Hz, with high noise attenuation (e.g. at 217Hz)) is realized, without requiring a large IC/PCB area or incurring high power dissipation. The proposed voltage references 200a-200f, 300, 350 may usefully find usage in Class D amplifiers, or other suitable applications. · A Self-Oscillating Amplifier Circuit

With reference to FIG. 6, a block diagram of a self-oscillating amplifier circuit 600 (also known as a 3-state Filter-less Bang-Bang Control CDA) is depicted, according to a different embodiment. In relation, FIG. 7a shows schematics of the amplifier circuit 600 and FIG. 7b shows output waveforms 700 generated by the amplifier circuit 600. Broadly, the amplifier circuit 600 comprises a hysteresis controller 602 (also known as a Bang-Bang controller) for receiving a pair of input signals (provided by first and second input modules 604a, 604b as V_in, V_ip respectively - see FIG. 7a), the controller 602 includes first and second hysteresis comparators 606a, 606b to generate first and second output signals; a synchronization module 608 configured to synchronize high frequency carrier components of the first and second hysteresis comparators 606a, 606b by providing the first and second output signals as feedbacks to the second and first hysteresis comparators 606a, 606b respectively; and first and second output stages 610a, 610b respectively coupled to the first and second hysteresis comparators 606a, 606b, and configured to generate third and fourth output signals based on the first and second output signals to provide a resultant switching signal for driving a load 612 (e.g. a loudspeaker). The third and fourth output signals (i.e. V_out__p, V_out__n) share in-phase high frequency components, and out-of-phase low frequency components. It is to be appreciated that synchronizing the high frequency carrier components of the first and second hysteresis comparators 606a, 606b by the synchronization module 608 specifically means synchronizing the high frequency carrier components in the first and second output signals generated by the first and second hysteresis comparators 606a, 606b. The resultant switching signal alternates between 3-states (i.e. V_DD, 0 V, and - V_DD) in dependence of the input signals. That is, when the resultant input signal, Vip-Vjn, is positive, the generated switching signal, V_ouLp-V_out__n, alternates between V_DD

0. But when the resultant input signal, V_lp-V_in, is negative, the generated switching signal, V_out_p- V_out_n, then alternates between O and - V_DD. An advantage of the 3-state switching signal is having significantly reduced carrier components, thereby eliminating need to include an output low-pass filter in the proposed amplifier circuit 600. Moreover, it is to be appreciated that the third and fourth output signals are further arranged to be feedback to the first and second hysteresis comparators 606a, 606b respectively, via first and second feedback modules 614a, 614b respectively. Each feedback module 614a, 614b is arranged in an RC network configuration. More specifically, the first feedback module 614a, which is coupled to the negative input terminal of the first hysteresis comparator 606a, comprises a feedback resistor arranged in parallel with another feedback resistor R,_n1 and a capacitor C_M . Similarly, the second feedback module 614b, which is coupled to the negative input terminal of the second hysteresis comparator 606b, comprises a feedback resistor R_FB2 arranged in parallel with another feedback resistor R_IN2 and a capacitor C_FB2.

Further, it is to be appreciated that the first and second hysteresis comparators 606a, 606b are configured in a parallel arrangement, and also that the controller 602 also includes four feedback resistors (i.e. labelled as R_H , Rh2 RM 2 and R_H22 in FIG. 7a), where R^ ^ , Rh2i are arranged at the first hysteresis comparator 606a, and R_H and R_h22 are arranged at the second hysteresis comparator 606b. Particularly, R_H , and the first hysteresis comparator 606a forms the upper branch of the controller 602, whereas R_{M 2} and R_h22 and the second hysteresis comparator 606b then forms the lower branch of the controller 602. The synchronization module 608 includes a pair of resistors (i.e. labelled as f?_h31 and R ,32 in FIG. 7a) in parallel circuit arrangement. Then, each output stage 610a, 610b includes a driver module 614a, 616a coupled to an output module 614b, 616b (which is in the form of a pair of transistors in parallel circuit arrangement). For the amplifier circuit 600, the hysteresis ( V_h) of the controller 602 is generated by the feedback resistors, R_h2i , ft/, 12 and R_h22, and the synchronization module 608. The synchronization module 608 feeds back the output signal of the opposing branch of the controller 602 as inputs to the controller 602, and synchronizes the high frequency carrier components of the two branches of the controller 602, thereby generating the 3-state switching signal by comparing the error signal ( V_erri and V_err2) with the hysteresis band ( V_/, , V_/,i ⁺, V_h2 , V_h2 ⁺) of the first and second hysteresis comparators 606a, 606b. The nomenclatures V_h and are the hysteresis bands of the first hysteresis comparator 606a; V_M ^"\s the lower limit and V_h is the upper limit; and V_h2 and V_h2 ⁺ are the hysteresis bands of the second hysteresis comparator 606b. FIG. 8 shows waveforms 800 generated in the upper branch of the controller 602. For completeness, it is worth noting that in the reported single-ended and 2-state BTL Bang-Bang control CDAs, the synchronization module 608 is absent.

Consequent to the function of the synchronization module 608, the high frequency carrier components of the third and fourth output signals, V_ouLp and Vout_n, are in-phase, whereas the low frequency audio components are out-of- phase. Put simply, the resultant switching signal is 3-state (i.e. see FIG. 7b).

On the basis of FIG. 7a and adopting a derived analytical methodology disclosed in a journal paper: "T. Ge and J. S. Chang, "Bang-Bang Control Class-D Amplifiers: Power-Supply Noise," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, pp. 723-727, 2008", the On' and 'off period, t_on and t_off, can be derived as follows: t_on is the period when V_M = V_DD, and t_off is the period when V_M = -V_DD. By straightforward analysis, it can be shown that f_on1 and t_om respectively (as shown in FIG. 8), which are the On' and 'off periods for the upper branch of the controller 602 can be derived as follows: By application of Kirchhoff s Current Law,

By re-arranging and integration, dt

/

(2) errl

4- D I ''out p · ^' D 4- P in rrl

Tⁿfbl ^ ⁿml ' ^Kfbi wherein R_el = R_in //R_{fb l} is the equivalent resistance of and R_m in parallel. Hence,

(3) e ^e- f^¹- * const = mV_{cli t}__p + (1 - m)V_in-V_ervi

wherein m = is the resistance ratio.

During ii→r₂, which is the On' period f_on1 based on the waveform 800 depicted FIG. 8, the error signal V_err1 can be derived as follows:

At t = ,

errl hi

At t = t₂.

V errl = V hi ⁺

Hence, const in equation (3) and f_on1 and t_o can be derived as: const = mV_DD + (1— m)¥_f, (4)

Similarly, t_on2 and t_om, the 'on' and Off period of the lower branch of the controller 602, can be derived as:

mV_DD - (l - m)V_ipW_h2* (8) toff2 ~ Re z CfbZ [mV_DD - (l - m)V_ip+V_h2 wherein,

R

v fill Rfill

"hi = M

Rfell ft 21 ^l¾ll Ml

R hit i?

v, hi + (10) h21 fc-3i

From equations (9) to (12), it can be noted that the hysteresis band of the controller 602 is determined by the feedback resistors, R_h , /721 , Rh and R_h22, and the synchronization module 608. As mentioned, the synchronization module 608 synchronizes the high frequency carrier components by feeding the output signal of the opposing branch back to the controller 602. Hence, this feedback mechanism forces the synchronization of the signals at the two branches of the controller 602.

Based on the equations (5) to (8) and by using Taylor Series, when the input signal is 0, the idle switching frequency, f_sw can be easily derived as:

(13) wherein R_e and C_fb are the designed values of f?_e1 (or R_e2), C_fb1 (or C_fb2), respectively. V_h is the average value of ¼,/ and V_h2 ⁺ (or -V_h and -V/,₂ ^")-

So, with reference to FIG. 9, a method 900 of generating the resultant switching signal using the proposed amplifier circuit 600, comprises: at step 902, receiving the pair of input signals by the hysteresis controller 602 to enable the first and second hysteresis comparators 606a, 606b to generate the first and second output signals; at step 904, providing the first and second output signals as feedbacks by the synchronization module 608 to the second and first hysteresis comparators 606a, 606b respectively to synchronize high frequency carrier components of the first and second hysteresis comparators 606a, 606b; and generating third and fourth output signals by the first and second output stages 610a, 610b based on the first and second output signals to provide the resultant switching signal for driving a load, and feedback the third and fourth output signals to the first and second hysteresis comparators 606a, 606b respectively, wherein the resultant switching signal alternates between the 3-states in dependence of the input signals.

• Results and Verification

The proposed amplifier circuit 600 is evaluated by simulations using software from Cadence™ based on a commercial 65 nm CMOS process. Different sets of circuit parameters for simulating four cases (i.e. Cases 1 , 2, 3 and 4) of feedback and synchronization module block 608 designs of the amplifier circuit 600 are set out in a table 1000 depicted in FIG. 10 - the intention is to ascertain the important parameters thereto. Also, the input frequency f_in used is 2 kHz and supply voltage V_DD is 3.6 V.

FIG. 1 1 shows output signal waveform 1 100 ( V_out_p-V_out__n) corresponding to the resultant switching signal generated (based on Case 1 in the table 1000 of FIG. 10, M = 0.7), and as expected, the output obtained indeed is that of a filter-less 3-state Bang-Bang control CDA.

FIG. 12 shows evaluation results 1200 of Total Harmonic Distortion (THD) versus modulation index, M, of the amplifier circuit 600 for the four cases of circuit parameters provided in the table 1000 of FIG. 10. It can be seen from FIG. 12 that unlike conventional PWM and Sigma-Delta CDAs, the THD of the proposed amplifier circuit 600 increases with decreasing M. The comparison between Case 1 and Case 2 (or Case 3 and Case 4) shows that a lower hysteresis band results in a lower THD. The comparison between Case 1 and Case 3 (or Case 2 and Case 4) shows that a smaller value of C_ft1 and C_fb2 results in reduced THD. This is somewhat expected, because with a lower hysteresis band and a smaller value of C and C_fb2, the proposed amplifier circuit 600 switches at a higher frequency (i.e. refer to equation (13)), but at the cost of higher switching power loss at the output stages 610a, 610b.

Although the THD performance is somewhat compromised in all four cases - the best being Case 1 , the THD obtained is usually sufficient for a number of low- power power-critical applications. For example, as the signal-to-noise ratio/dynamic range of a sub-miniature loudspeaker in many wearable devices is smaller or equal to 40 dB, a THD of about 1 % is usually acceptable - particularly in view of the requirement of much desired hardware simplicity (with accompanying high power-efficiency).

In summary, the proposed amplifier circuit 600 is the first-ever filter-less 3-state Bang-Bang control CDA where an output low-pass filter (typically bulky in terms of PCB area needed, and also costly to make) is not required. Compared to the the single-ended and 2-state counterpart Bang-Bang control CDAs, the proposed amplifier circuit 600 features the simplest hardware (and highest power- efficiency), but with somewhat compromised fidelity. Nevertheless, the reduced fidelity is deemed sufficient for most ultra-low-power or power-critical applications such as in low-to-mid performance wearable devices, hearing aid devices, and the like.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary, and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed invention. For example, with reference to FIG. 6, the first and second feedback modules 614a, 614b can be optional in certain variant embodiments, and so there is therefore no feedback of the third and fourth output signals back to the first and second hysteresis comparators 606a, 606b for those cases.

Claims

1. A voltage reference comprising:

a voltage divider arranged to be coupled to a voltage supply; and

5 a filter circuit arranged to be coupled to output of the voltage divider, the filter circuit includes at least one transistor and a capacitive element,

wherein in use, the transistor is configured to operate in cut-off mode to enable the filter circuit to function as an RC low-pass filter to attenuate supply noise of the voltage supply, and to enable the filter circuit to generate a w reference voltage based on the voltage supply, the reference voltage substantially free of the supply noise.

2. The voltage reference of claim 1 , wherein the transistor is an n-type transistor or a p-type transistor.

15

3. The voltage reference of any preceding claims, wherein the capacitive element includes being in a series circuit arrangement with the transistor.

4. The voltage reference of any preceding claims, further includes a buffer0 circuit coupled to the filter circuit to receive and store the reference voltage from the filter circuit.

5. The voltage reference of claim 4, wherein the buffer circuit is an amplifier configured in negative feedback arrangement.

5

6. The voltage reference of any preceding claims, wherein the at least one transistor includes at least first and second transistors in a parallel circuit arrangement. 0

7. The voltage reference of claim 6, wherein the at least first transistor includes a plurality of transistors in a series circuit arrangement.

8. The voltage reference of claim 6, wherein the at least second transistor includes a plurality of transistors in a series circuit arrangement.

5

9. A method of generating a reference voltage using a voltage reference, which includes a voltage divider arranged to be coupled to a voltage supply, and a filter circuit arranged to be coupled to output of the voltage divider, the filter circuit includes at least one transistor and a capacitive element, the method comprises:

operating the transistor in cut-off mode to enable the filter circuit to function as an RC low-pass filter to attenuate supply noise of the voltage supply; and

generating the reference voltage by the filter circuit based on the voltage supply, the reference voltage substantially free of the supply noise.

10. A self-oscillating amplifier circuit comprising:

a hysteresis controller for receiving a pair of input signals, the controller includes first and second hysteresis comparators to generate first and second output signals;

a synchronization module configured to synchronize high frequency carrier components of the first and second hysteresis comparators by providing the first and second output signals as feedbacks to the second and first hysteresis comparators respectively; and

first and second output stages respectively coupled to the first and second hysteresis comparators, and configured to generate third and fourth output signals based on the first and second output signals to provide a resultant switching signal for driving a load,

wherein the resultant switching signal alternates between 3-states in dependence of the input signals.

1 1. The amplifier circuit of claim 10, wherein the first and second hysteresis comparators are configured in a parallel arrangement.

12. The amplifier circuit of any of claims 10-1 1 , further comprising first and second feedback modules arranged to respectively feedback the third and fourth output signals.

13. The amplifier circuit of claim 12, wherein each feedback module is in an RC network configuration.

14. The amplifier circuit of any of claims 10-13, wherein the third and fourth output signals include in-phase high frequency components, and out-of-phase low frequency components.

15. The amplifier circuit of any of claims 10-14, wherein the synchronization module comprises a pair of resistors in parallel circuit arrangement.

16. The amplifier circuit of any of claims 10-15, wherein each output stage includes a driver module coupled to an output module, which includes a pair of transistors.

17. The amplifier circuit of any of claims 10-16, wherein the 3-states include V_DD, 0 V, and -V_DD.

18. A method of generating a resultant switching signal that alternates between 3-states using a self-oscillating amplifier circuit, which includes a hysteresis controller having first and second hysteresis comparators, a synchronization module, and first and second output stages respectively coupled to the first and second hysteresis comparators, the method comprises:

receiving a pair of input signals by the hysteresis controller to enable the first and second hysteresis comparators to generate first and second output signals;

providing the first and second output signals as feedbacks by the synchronization module to the second and first hysteresis comparators respectively to synchronize high frequency carrier components of the first and second hysteresis comparators; and

generating third and fourth output signals by the first and second output stages based on the first and second output signals to provide the resultant switching signal for driving a load,

wherein the resultant switching signal alternates between the 3-states in dependence of the input signals.