A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or...http://www.google.fr/patents/US20060190636?utm_source=gb-gplus-shareBrevet US20060190636 - Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations
Method and apparatus for invalidating cache lines during direct memory ...
Numéro de demande: 11/054,183 Numéro de publication: US 2006/0190636 A1 Date de dépôt: 9 févr. 2005 Brevet délivré: US7451248 ( Date de délivrance 11 nov. 2008)
