A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as...http://www.google.fr/patents/US6333532?utm_source=gb-gplus-shareBrevet US6333532 - Patterned SOI regions in semiconductor chips
