A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect...http://www.google.fr/patents/US7512729?utm_source=gb-gplus-shareBrevet US7512729 - Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency
Method and apparatus for a high efficiency two-stage rotating priority ...
