A monotonic dynamic-static pseudo-NMOS logic circuit comprises a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input; and a static logic circuit having a clock bar input and having an output configured...http://www.google.fr/patents/US6649476?utm_source=gb-gplus-shareBrevet US6649476 - Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a ...
