A semiconductor structure formed on a substrate and process for preventing oxidation induced stress in a determined portion of the substrate. The structure includes an n-FET device and a p-FET device, and a shallow trench isolation having at least one overhang is selectively configured to prevent oxidation...http://www.google.fr/patents/US7847358?utm_source=gb-gplus-shareBrevet US7847358 - High performance strained CMOS devices
