A method and circuit for reducing the power up time of a phase lock loop (PLL). In one embodiment, the present invention cuts off a first voltage to the phase lock loop thereby powering down the phase lock loop. In power down, a second voltage is utilized to maintain the power requirements of the filter...http://www.google.fr/patents/US6667642?utm_source=gb-gplus-shareBrevet US6667642 - Method and circuit for reducing the power up time of a phase lock loop
Method and circuit for reducing the power up time of a phase lock loop
