A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline...http://www.google.fr/patents/US6065106?utm_source=gb-gplus-shareBrevet US6065106 - Resuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processing
Resuming normal execution by restoring without refetching instructions in ...
