A method and apparatus is provided to debug using replicated logic. A text representation of a circuit is compiled to generate a first register transfer level (RTL) netlist. The netlist may be mapped to a target architecture, such as a field programmable gate array (FPGA). The netlist may be used to...http://www.google.fr/patents/US6904576?utm_source=gb-gplus-shareBrevet US6904576 - Method and system for debugging using replicated logic
Method and system for debugging using replicated logic
