A method of multiplying 32-bit values includes decomposing each multiplicand into its 16-bit components. This approach leads to a processor core design which permits re-use of much of the logic in the multiplication unit. The multiplication unit includes a selector which can feed various-sized data formats...http://www.google.fr/patents/US6574651?utm_source=gb-gplus-shareBrevet US6574651 - Method and apparatus for arithmetic operation on vectored data
Method and apparatus for arithmetic operation on vectored data
