A method and logic for providing an asynchronous interface to a synchronous memory is disclosed. One embodiment of the present invention provides for a memory having a first logical unit which is operable to generate a synchronized clock signal in response to a chip select signal to the memory. The memory...http://www.google.fr/patents/US6948084?utm_source=gb-gplus-shareBrevet US6948084 - Method for interfacing a synchronous memory to an asynchronous memory interface and logic of same
Method for interfacing a synchronous memory to an asynchronous memory ...
