A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate....http://www.google.fr/patents/US20050121804?utm_source=gb-gplus-shareBrevet US20050121804 - Chip structure with bumps and testing pads
Numéro de demande: 10/730,834 Numéro de publication: US 2005/0121804 A1 Date de dépôt: 8 déc. 2003 Brevet délivré: US7394161 ( Date de délivrance 1 juil. 2008)
