In a method of testing a nonvolatile semiconductor memory integrated on a semiconductor chip comprising a memory cell array, a first register that stores an address of a defective region in the memory cell array, a plurality of internal voltage generator circuits, and a second register, the second register...http://www.google.fr/patents/US6819596?utm_source=gb-gplus-shareBrevet US6819596 - Semiconductor memory device with test mode
