Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including...http://www.google.fr/patents/US6260118?utm_source=gb-gplus-shareBrevet US6260118 - Snooping a variable number of cache addresses in a multiple processor system by a single snoop request
Snooping a variable number of cache addresses in a multiple processor system ...
