A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the...http://www.google.fr/patents/US5434997?utm_source=gb-gplus-shareBrevet US5434997 - Method and apparatus for testing and debugging a tightly coupled mirrored processing system
Method and apparatus for testing and debugging a tightly coupled mirrored ...
