The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element...http://www.google.fr/patents/US20020062436?utm_source=gb-gplus-shareBrevet US20020062436 - METHOD FOR PROVIDING EXTENDED PRECISION IN SIMD VECTOR ARITHMETIC OPERATIONS
METHOD FOR PROVIDING EXTENDED PRECISION IN SIMD VECTOR ARITHMETIC OPERATIONS
Numéro de demande: 09/223,046 Numéro de publication: US 2002/0062436 A1 Date de dépôt: 30 déc. 1998 Brevet délivré: US7159100 ( Date de délivrance 2 janv. 2007)
