A synchronous mirror delay (SMD) clock recovery and skew adjustment circuit for an integrated circuit is described, having a reduced circuit implementation. The SMD clock recovery and skew adjustment circuit incorporates a delay segment into the forward delay line (FDL) and backward delay line (BDL)...http://www.google.fr/patents/US6570813?utm_source=gb-gplus-shareBrevet US6570813 - Synchronous mirror delay with reduced delay line taps
Synchronous mirror delay with reduced delay line taps
