A cache coordination mechanism for a multiprocessor, shared-memory computer switches between a snooping mechanism where an individual processor unit broadcasts or multicasts cache coherence messages to each other node on the system and a directory system where the individual processor unit transmits...http://www.google.fr/patents/US20020133674?utm_source=gb-gplus-shareBrevet US20020133674 - Bandwidth-adaptive, hybrid, cache-coherence protocol
Numéro de demande: 10/037,727 Numéro de publication: US 2002/0133674 A1 Date de dépôt: 19 oct. 2001 Brevet délivré: US6883070 ( Date de délivrance 19 avr. 2005)
