A process for forming a DRAM cell having a capacitor adjacent a field effect transistor (FET), wherein the FET fabrication area is protected from adverse effects of the capacitor formation. The process is misalignment tolerant and provides FETs with appreciably lower defects in the substrate beneath...http://www.google.fr/patents/US4760034?utm_source=gb-gplus-shareBrevet US4760034 - Method of forming edge-sealed multi-layer structure while protecting adjacent region by screen oxide layer
Method of forming edge-sealed multi-layer structure while protecting ...
