A CPU communicates via an indirect memory access channel (IMA) to many devices on a high speed loop and an asynchronous low speed loop. The IMA connects to a loop adaptor (LAD) which connects to the primary parallel loop. A low speed serial loop is coupled to the primary loop through a general device...http://www.google.fr/patents/US4028667?utm_source=gb-gplus-shareBrevet US4028667 - Asynchronous, hierarchical loop communication system with independent local station control of access to inbound time portions without central control
Asynchronous, hierarchical loop communication system with independent local ...
