An apparatus including a sampling circuit to generate sampling clocks from a local clock and the sampling clocks to sample incoming data and a quarter clock, a phase detector to detect a phase difference between a data transition in sampled data and the local clock, and a delay line adapted to delay...http://www.google.fr/patents/US6775345?utm_source=gb-gplus-shareBrevet US6775345 - Delay locked loop based data recovery circuit for data communication
Delay locked loop based data recovery circuit for data communication
