One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing...http://www.google.fr/patents/US20020057104?utm_source=gb-gplus-shareBrevet US20020057104 - Method and apparatus for incorporating a multiplier into an FPGA
Method and apparatus for incorporating a multiplier into an FPGA
Numéro de demande: 10/043,958 Numéro de publication: US 2002/0057104 A1 Date de dépôt: 8 janv. 2002 Brevet délivré: US6573749 ( Date de délivrance 3 juin 2003)
