The invention involves new microarchitecture apparatus and methods for superscalar microprocessors that support multi-instruction issue, decoupled dataflow scheduling, out-of-order execution, register renaming, multi-level speculative execution, and precise interrupts. These are the Distributed Instruction...http://www.google.fr/patents/US6311261?utm_source=gb-gplus-shareBrevet US6311261 - Apparatus and method for improving superscalar processors
Apparatus and method for improving superscalar processors
