A buffer memory for use in the output queue of a packet switching network is described. The buffer consists of two separate memories (160, 170, 260, 270) connected through a multiplexer (310) to the output of the switch. A memory access control (120, 220) processes the incoming data which arrives on...http://www.google.fr/patents/US5224093?utm_source=gb-gplus-shareBrevet US5224093 - High-speed multi-port FIFO buffer circuit
