A method is disclosed for insuring that two semiconductor chips which have a 1-bit defect at the same chip address are not paired at any memory address by a fault alignment exclusion mechanism (FAEM) which functions to position chips having defects at different memory addresses. The FAEM employs an error...http://www.google.fr/patents/US4453248?utm_source=gb-gplus-shareBrevet US4453248 - Fault alignment exclusion method to prevent realignment of previously paired memory defects
Fault alignment exclusion method to prevent realignment of previously paired ...
