A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to...http://www.google.fr/patents/US20050251771?utm_source=gb-gplus-shareBrevet US20050251771 - Integrated circuit layout design methodology with process variation bands
Integrated circuit layout design methodology with process variation bands
