A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral...http://www.google.fr/patents/US5867735?utm_source=gb-gplus-shareBrevet US5867735 - Method for storing prioritized memory or I/O transactions in queues having one priority level less without changing the priority when space available in the corresponding queues exceed
Method for storing prioritized memory or I/O transactions in queues having ...
