A delay-locked loop includes a clock multiplier that generates a multiplied clock signal responsive to an input clock signal. The multiplied clock signal has a frequency that is a multiple of a frequency of the input clock signal. A variable delay circuit generates a delayed clock signal responsive to...http://www.google.fr/patents/US6930524?utm_source=gb-gplus-shareBrevet US6930524 - Dual-phase delay-locked loop circuit and method
